From 7eca665d684a734d55b0bb26c4f1831d399c5330 Mon Sep 17 00:00:00 2001
From: Francis Rowe Releases
-
- 6th release (pre-release, 3rd beta)
+ 6th release (pre-release, 4th beta)
Binaries (for flashing)
+ Binaries (for flashing) (right-click save as, or use wget)
-
- Source code (for hacking)
+ Source code (for hacking) (right-click save as, or use wget)
-
- Metadata (for re-creating the source archive)
+ Metadata (for re-creating the source archive) (right-click save as, or use wget)
-
Machines still supported (compared to previous release):
@@ -125,6 +126,9 @@
+ Also see future/index.html#t60_cpu_microcode. +
+A user with 2 T60's, each with a Core 2 Duo T7200 processor tried libreboot on each machine. One worked, one did not. It should be explained that in addition to the microcode (on the CPU), updates are usually supplied in coreboot (from Intel) which patch the onboard microcode to fix bugs. @@ -145,12 +149,6 @@
If reading this for 2nd beta, note that any debugging obtained so far will be included in the 3rd beta.
-- At the time of this pre-release, MacBook2,1 support is present but untested. I have ordered a MacBook2,1 - but it has not yet arrived at the time of writing. - I take it merely on faith that these images even work at all. Use at your own risk! -
+ Coreboot log when running Video BIOS (grub payload) and http://review.coreboot.org/5926. +
+
+ Result (ThinkPad X60): cbmem -c output
+ Config used on the X60 (grub payload and vbios): .config
+
+ With VBIOS
+ With native graphics (replay code).
+
+ Here is a crash dump from running native graphics (): /sys/class/drm/card0/error. +
+ ++Back then we had no idea that GTT address was incorrect, and we had no idea what was causing the issue. + +
+Note: see this fix for the initial fix that was found. + +not working yet +http://review.coreboot.org/#/c/5885/ + +untested. will test this. +checkout 5320. cherry pick 5345 on top. +mannually apply changes from 5884/1 and 5885/3 +make backlight changes as in #x60_native_notes and #t60_native_notes +test this on X60 and T60. + +If it works, manually apply 5885 to 5320 alone and then push with 5320 as dependency. +Rebase that new change ID, and rebase 5345 (pushing it as new change ID). +Manually merge the rebased 5345 into the new patch, and then push that. + +Boot with grub (obviosly!) and kernel 3.14.4 as before (with 17fec8a left untouched!). + +Note: tidy these notes! (so others can follow) + +get those logs: +Make a copy of these files: + * /var/log/dmesg + * /var/log/kern.log + * /var/log/Xorg.0.log + * /var/log/Xorg.0.log.old (If you have to restart gdm) + * /proc/ioports + * /proc/iomem +Record these outputs: + * sudo intel_reg_dumper + * uname -r + * lspci -vvnn +Do this first: $ sudo modprobe msr (then do as below): + * sudo inteltool -a --> in coreboot/src/util/inteltool +Make a copy of: + * coreboot serial output log. + --> Get it from serial port, or get it like that: + --> ./cbmem -c (under coreboot/util/cbmem) +Output from source tree: +$ git log -p | head -150 (localhost/x60gitlog) +$ git diff (localhost/x60gitdiff) +Make a copy of the .config from coreboot source tree + ^ (localhost/x60config) +3D acceleration test (test if 3.12+/stolenmem issue is fixed): + - Run openarena (1024x768 res), say if it works. (note: Press tilde, do /cg_drawfps 1) + - Run tuxcart (1024x768 res), say if it works. + - Run neverball (1024x768 res), say if it works. + - Run glxgears, report what you see. + +Some results on the X60 (3D still doesn't work, openarena and tuxkart were slow): +5885_logs.tar.gz +git diff: http://paste.debian.net/102618/ + +In src/northbridge/intel/i945/raminit.c +PaulePanter: fchmmr: In your next step could you please add +PaulePanter: printk(BIOS_DEBUG, "BSM = 0x%08x\n", pci_read_config32(PCI_DEV(0,2,0), BSM)); +PaulePanter: before +PaulePanter: pci_write_config32(PCI_DEV(0,2,0), BSM, (tolud * MiB - 64 * MiB) & 0xfff00000); +done +Also removing the #if statement around those 2 lines above. +Also adding it after that line aswell, per advice from PaulePanter + +Some new results on the X60 after doing the above (3D still doesn't work, openarena and tuxkart were slow): +5885_logs_2.tar.gz + +PaulePanter: fchmmr: No idea if you can write with `devmem2`. Never used it. +PaulePanter: fchmmr: It would indeed be interesting to know what value the BSM has with the vendor BIOS. +Note to self: do that. + +PaulePanter said: I have `& 0xfff00000` and phcoder uses `& 0xfffff000`, so it looks like I have the ordering incorrect. + + +Look at that discussion: +http://lists.freedesktop.org/archives/intel-gfx/2014-May/046309.html +http://lists.freedesktop.org/archives/intel-gfx/2014-May/046310.html +--> if BSM register is read-only, then is there something els ethat we might have missed? + ++ + + + + + + + + + + +
+ Some further notes to refer to later (WARNING: long! These are collected IRC logs for later reference. Most of the + logs are not useful or relevant, and will be deleted later): + +
+Note: see this fix for the initial fix that was found. + +see: http://www.coreboot.org/Board:lenovo/x60#Problems_in_native_graphics_code_exposed_by_recent_kernels +see: http://www.coreboot.org/Lenovo_x60x_vgainit_todos + +Non-coreboot (not even i945) platforms also have issues with 3.12+ +see: https://bugs.freedesktop.org/show_bug.cgi?id=76520 + +Is this relevant?: http://lists.freedesktop.org/archives/intel-gfx/2014-February/040771.html + + + +note: read below. +and note: on later kernels they also can't seem to init the GPU properly without vbios or native gfx, whereas older kernels could. + +PaulePanter: damo22: There is also a Linux and coreboot native graphics incompatibility documented in the Wiki (by samnob). +PaulePanter: http://www.coreboot.org/Board:lenovo/x60#Problems_in_native_graphics_code_exposed_by_recent_kernels +fchmmr: PaulePanter, that only exists with kernel 3.12 and above. +PaulePanter: fchmmr: Do you have time to report it to the Freedesktop Bugzilla? +funfunctor: patrickg: I think its related to recent changes we had done to toolchain.in +fchmmr: Yes. What info do you need ? +PaulePanter: fchmmr: It’s a regressions and these are normally not allowed with Linux’ no regression policy. +fchmmr: What do you think would happen then, after I made that report? +PaulePanter: fchmmr: https://01.org/linuxgraphics/documentation/how-report-bugs +fchmmr: You can look at it 2 ways: kernel broke, or kernel fixed a bug which broke coreboot. +PaulePanter: fchmmr: Hopefully they’ll fix it. +fchmmr: so: either coreboot is broken, or kernel is broken. +fchmmr: PaulePanter, kernel 3.12+ should work just fine on lenovo bios, so my opinion is that the native gfx in coreboot is what's buggy. +PaulePanter: fchmmr: You can also check with the developers in #intel-gfx. But first report the bug so you can reference it. +fchmmr: Do you think I should just copy what's in the coreboot wiki already? +PaulePanter: fchmmr: Does not matter. If it worked before 3.12, it should work afterward. +fchmmr: It seems pretty complete (as far as reporting it is concerned). +fchmmr: PaulePanter, my basic point is that I'm on the fence as to whether this is linux's problem, coreboot's problem, or both. +PaulePanter: fchmmr: That would probably help. If they need other information, the Intel folks will ask you for it. Daniel Vetter and the other Intel folks are very responsive in my experience. +fchmmr: So you think then that there would be a patch specifically for i915 + coreboot_native_init +PaulePanter: fchmmr: I do not know. They hopefully figure it out. +fchmmr: PaulePanter, I will do it. +PaulePanter: fchmmr: And as I wrote, it is a regression. As far as I understood it, even if the firmware/hardware is broken, Linux should not introduce regressions. +fchmmr: PaulePanter: at the very least, it might offer a new perspective. this whole issue has been very one-sided so far: it has only been coreboot community that talks about it. It has probably gone unobserved in kernel/intel community. +fchmmr: The intel/kernel people might even be able to (easily) spot a fix for coreboot. +fchmmr: I hadn't even considered this possibility before, I thought it was only a coreboot problem. Talking to those other people definitely makes sense. + +PaulePanter of #coreboot made the initial report to Freedesktop tracker: + +PaulePanter: fchmmr: Hi. Did you report the Linux regression to the Freedesktop bug tracker? +PaulePanter: fchmmr: Understood. Do you have an account for the Freedesktop bug tracker? +fchmmr: PaulePanter: I do not have an account for Freedesktop bug tracker, but I think I could get one? +PaulePanter: fchmmr: Yes, it is easy to register. +fchmmr: PaulePanter, there's reporting and there's reporting properly; I want to compile my report first, before I make it. +PaulePanter: fchmmr: As you do not know what they need, I think it is the wrong approach. +fchmmr: Since the people that I am reporting to will be unfamiliar with the issue, and might not even know about coreboot, or only vaguely know. +PaulePanter: fchmmr: I’ll report the issue and give you the URL. You can then add to it. +fchmmr: PaulePanter: Good point. I can make it brief describing it as best I can, and then I can answer any specific questions. +fchmmr: PaulePanter, you can use my notes at http://libreboot.org/howto.html#kernel312bugs if you like, it's a collection of insights plus links to those pages on the coreboot wiki that talk about the issue. +fchmmr: (in case there is anything in the notes that might be helpful) +fchmmr: PaulePanter, are the intel i915 devs of freedesktop also the ones working on the i915 code in kernel.org? (I'm slightly confused about this) + +THE REPORT: + +PaulePanter: fchmmr: The Wiki talks about crashes. +PaulePanter: fchmmr: https://bugs.freedesktop.org/show_bug.cgi?id=79038 + +PaulePanter: fchmmr: The Wiki talks about crashes. +PaulePanter: fchmmr: https://bugs.freedesktop.org/show_bug.cgi?id=79038 +fchmmr: PaulePanter, thanks. I'll add to it and help any way I can. +PaulePanter: fchmmr: Add `drm.debug=0x06` to the Linux command line (probably configuring in GRUB) and please add `/var/log/dmesg` to the bug report. (Or the output of `dmesg`.) +PaulePanter: fchmmr: They also need `/var/log/Xorg.0.log` and your distribution and exact Linux kernel version `uname -r`. +fchmmr: PaulePanter: there are basically 2 versions of native init: 3998 (based on replay, only works on X60 with XGA screen - also what libreboot currently uses) and 5320 (much better, works on more screens, 5345 can use it to enable T60 - not yet in libreboot) +fchmmr: PaulePanter: should I do this test on both versions? (libreboot and coreboot+5320+5345) + +fchmmr: PaulePanter: should I do this test on both versions? (libreboot and coreboot+5320+5345) +fchmmr: PaulePanter: nonetheless, I will do both, and make that report for you now. +fchmmr: Do I do this on pre-3.12 kernel or 3.12+ ? +PaulePanter: fchmmr: I’d say Linux 3.12+. +PaulePanter: fchmmr: Do you know which coreboot patches samnob used? + +fchmmr: PaulePanter: very well. http://jxself.org/linux-libre has latest kernels +fchmmr: I will install that. +fchmmr: I do not know what coreboot patches samnob used. Probably 3998 (this was a long time ago). +fchmmr: Definitely change ID 3998 (review.coreboot.org gerrit): http://review.coreboot.org/#/c/3998/ + + +fchmmr: PaulePanter: here is the information that you requested: http://libreboot.org/logs/3998_Xorg.0.log http://libreboot.org/logs/3998_dmesg http://libreboot.org/logs/3998_uname +fchmmr: PaulePanter: that bug in the report doesn't happen with the above -- it's an older kernel. +fchmmr: Do they want me to try 3.12+ instead? +fchmmr: PaulePanter: you should also give them these links to the lastest code for native graphics: +fchmmr: http://review.coreboot.org/#/c/5320/ + +PaulePanter: fchmmr: Thank you for getting the logs. Please register and upload the files yourself. +fchmmr: Yes, ok. I will also get the same logs again for a kernel that is broken (3.12+) +fchmmr: I will repeat both processes again for coreboot+5320+5345, as currently I am getting these on libreboot. +fchmmr: More logs can't hurt, the worst that can happen is they will ignore the ones they don't need. I want to make sure they have everything they need. + +samnob: fchmmr: samnoble.org/thinkpad/kernel/linux-image-3.14.4-gnuowen_1_i386.deb and http://samnoble.org/thinkpad/kernel/linux-image-3.14.4-gnu-stolenmem-owen_1_i386.deb latest linux-libre without and with 17fec8a reverted. +PaulePanter: fchmmr: Thanks. + +fchmmr: samnob, thanks. +fchmmr: but we are trying to get kernel 3.12+ to work without users having to patch it +fchmmr: either by fixing coreboot, or patching around coreboot in the kernel +fchmmr: eventually both +samnob: Yes, just providing you kernels for the bug. +fchmmr: ah right. +fchmmr: with and without. that is useful. i was going to use jxself kernels. that is useful. +fchmmr: I'll use yours then ;) +fchmmr: dpkg -i ? + +samnob: Though based on the devs comment in the bug I think you're hope of the driver working around it is unlikely. +fchmmr: can't hurt to try +samnob: dpkg -i will work fine. +samnob: (though gdebi is more fun.) +samnob: there's a version symlink_hook in that same folder that is handy for grub2 payload users too. +fchmmr: samnob we think it might be classed under linux "no regression" policy +fchmmr: PaulePanter's idea +samnob: can't hurt to try :) + +Here is the debugging results then: coreboot_native_3.12_bug.tar.gz + +--- + +http://undeadly.org/cgi?action=article&sid=20131120060004 was suggested +(also refer back te the datasheet) + +---- + +I have since been alerted to this bug report, which is unrelated to us +but shows that 3.12 also breaks later systems on Lenovo BIOS (as far as I can tell): + +https://bugzilla.kernel.org/show_bug.cgi?id=71391 + +-- + +PaulePanter: fchmmr: If you run the Lenovo X60 right now, could you just paste it now. It should not change between all your tests. +PaulePanter: fchmmr: It would really be helpful to have it now. +fchmmr: My workstation X60 is running coreboot+5320 (and modification for backlight control support) +fchmmr: Shall I take iomem output from that? +fchmmr: kernel 3.2 is in use +PaulePanter: fchmmr: Yes. Please. +fchmmr: For you record: +fchmmr: $ uname -r +fchmmr: 3.2.0-56-generic-pae +fchmmr: distro: trisquel 6 +fchmmr: PaulePanter: http://paste.debian.net/101404/ + +PaulePanter linked to this: +http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/3rd-gen-core-desktop-vol-2-datasheet.pdf +--------------- + +PaulePanter: patrickg: As the resident i945 export, do you know where the register GBSM (Graphics Base of Stolen Memory) should be set? +PaulePanter: patrickg: Is the VGA Option ROM responsible for that? +PaulePanter: damo22: You do not see any problems with the VGA Option ROM, right? +damo22: PaulePanter: i am running vga rom with updated kernel (after the patch) and experience no problems with video +PaulePanter: damo22: Thank you for the confirmation. +PaulePanter: src/northbridge/intel/i945/northbridge.c: printk(BIOS_SPEW, "Base of stolen memory: 0x%08x\n", +patrickg: PaulePanter: what's that, 0x5c? +patrickg: h, no +PaulePanter: + /* Almost universally we can find the Graphics Base of Stolen Memory +PaulePanter: + * at offset 0x5c in the igfx configuration space. On a few (desktop)patrickg: PaulePanter: I think we never configured that but left it to vgabios +patrickg: PaulePanter: we only configured the RAM side +PaulePanter: patrickg: Thanks. So with native VGA init, coreboot needs to do that too. +damo22: we just need to write the gfxstolen base to gma config space at 0x5c +damo22: that should fix it +damo22: because then the kernel will try to read that +damo22: hmm but if the generation of the gma is not >=3 it will assume it is above top of memory +patrickg: well, it is +damo22: patrickg: do you happen to know if the x60 gma is generation 2 or 3? how do i find out +PaulePanter: damo22: lspci ? +damo22: (rev 0x)? +PaulePanter: lspci -nn +damo22: never mind i will ctags the kernel tree +patrickg: but bbl +patrickg: damo22: code.metager.de applies openGrok on tons of open source projects. probably to linux, too +damo22: thanks patrickg +damo22: okay, i945g/gm is generation 3 +damo22: its nothing to do with the lscpi revision +PaulePanter: damo22: How did you check that? +PaulePanter: … it is 3rd gen? +damo22: PaulePanter: its in the i915_drv.c in the kernel +damo22: eg, i965g/gm is generation 4 +PaulePanter: Ok. +damo22: its also NOT valleyview +* pl4nkton is now known as pl4nkton`away +PaulePanter: damo22: ? +PaulePanter: Who said that? +damo22: im trying to figure out which path the kernel takes before and after the patch +damo22: it must be different +PaulePanter: damo22: https://bugs.freedesktop.org/show_bug.cgi?id=79038#c12 +PaulePanter: damo22: Before they calculate it manually and afterward they read out that register, which the firmware should program, right? +PaulePanter: src/northbridge/intel/i945/i945.h:#define TOLUD 0x9c /* Top of Low Used Memory */ +PaulePanter: Off topic, how do I make Vim and Ctags jump to the correct header definition. If I Ctrl + click on `TOLUD` in `src/northbridge/intel/i945/raminit.c` it jumps into the header of `intel/fsp_sandybridge/northbridge.h` instead of `src/northbridge/intel/i945/i945.h`. +PaulePanter: ? +damo22: i have the same problem, there is a way to configure it to pop up a list of matches so you can select the right one but i dont know how +PaulePanter: damo22: Ok. Good to know I am not the only one. + +damo22: okay, so for gen 3 i915, (i945/m) we can do what i said above and it should work +PaulePanter: Is “graphics datastolen memory size (PCI Device 0 offset 52 bits 7:4)” configurable and programmed by the firmware or is it fixed if the IGP is enabled and can just be read? +PaulePanter: damo22: Yes. +damo22: its just a matter of setting the base address in the register +damo22: i think the only difference is that in the kernel it is assumed that it is aligned to 0x100000 +damo22: kernel does this: base &= ~((1<<20) - 1); +damo22: but coreboot does this: pci_read_config32(dev, 0x5c) & ~0xf, +damo22: possibly a one liner +damo22: change ~0xf to ~0xfffff lol +samnob: fchmmr: samnoble.org/thinkpad/kernel/linux-image-3.14.4-gnu-stolenmem-owen_2_i386.deb and linux-image-3.14.4-gnuowen_2_i386.deb with CONFIG_STRICT_DEVMEM unset. No PAE as always. +samnob: damo22: thanks for looking into this. + +fchmmr: damo22: you are the most awesome person ever. I'm stilll preparing my dev/debugging environment and you speculate this already. I will try it soon. +fchmmr: samnob: thank you for confirming. +fchmmr: samnob: ok, /dev/mem support and non-PAE. excellent! +samnob: fchmmr: don't overlook that revision 2 those, are new debs with STRICT_DEVMEM unset +damo22: fchmmr: its much quicker to read and compare code than to compile kernels and flash firmware +PaulePanter: fchmmr: I think your testing is not needed until you get a patch. +PaulePanter: damo22: TOLUD (PCI Device 0 offset BCh bits 31:20) +fchmmr: PaulePanter ? +fchmmr: Yes I understand that. I was about to debug, but now we will test damo22's advice first. +damo22: PaulePanter: i think intel_gma_init is being called with unaligned physical address for graphics mem + +PaulePanter: fchmmr: BDSM—Base Data of Stolen Memory Register +PaulePanter: http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/3rd-gen-core-desktop-vol-2-datasheet.pdf + +PaulePanter: fchmmr: The methods you try just read it out and never set it. +PaulePanter: This register contains the base address of graphics data stolen DRAM memory. BIOS determines the base of graphics data stolen memory by subtracting the graphics data stolen memory size (PCI Device 0 offset 52 bits 7:4) from TOLUD (PCI Device 0 offset BCh bits 31:20). +damo22: PaulePanter: im pretty sure BDSM is only present in core iX cpus +fchmmr: PaulePanter, yes my method was to go about to be sure where it is set, and then try to set it properly in 5320. +PaulePanter: fchmmr: The problem is already present with native graphics in coreboot master, isn’t it? +fchmmr: damo22 took a shorter method to get the same result (hopefully. like you, i wait for him to confirm or deny success) +fchmmr: PaulePanter, yes the 3.12+ glitches exist in 5320 changeset aswell as 3998 (the old replay version, which 5320 is a re-write of) +PaulePanter: fchmmr: Sorry, I claim your tests would have never gotten any solution for the problem. +* martinr (~martin@8.36.227.227) has joined #coreboot +fchmmr: PaulePanter, that is quite possible, but it was a test anyway. +PaulePanter: damo22: Chris Wilson and the Linux commit say that the BDSM is present, don’t they? +PaulePanter: + if (INTEL_INFO(dev)->gen >= 3) { +PaulePanter: + /* Read Graphics Base of Stolen Memory directly */ +fchmmr: I actually did find where the stolen memory address was set, in /var/log/kern.log after using drm.debug=0x06 in those previous results i uploaded to freedesktop.org, but that was on coreboot/5320 with the address set incorrectly. +fchmmr: just search for the word "stolen" in the log and you'll find it on one of the lines. + +PaulePanter: fchmmr: It’s not *set* it is *read* in there. +fchmmr: Oh right. +fchmmr: But I thought when reading it, it has to know the address. So the address I saw must have been what was set? +fchmmr: What am I missing? +damo22: okay so there is something to clarify, i915 driver is the same for all intel gpus even some that are physically located in cpu + +PaulePanter: fchmmr: As it is not explicitely set beforehand it contains some incorrect value, which is then read. +PaulePanter: fchmmr: That is the whole problem. +fchmmr: I see. +fchmmr: So, +fchmmr: my tests would have been useless, then. + +damo22: it didnt work +(note: can still try to make other changes: see testing notes below) + +damo22: oh wait, X just didnt detect the LVDS +damo22: in fact nothing did +damo22: but there were no errors +damo22: ok so when i plug external monitor X freezes and gives errors +damo22: and internal display isnt active +damo22: wierd, when i rebooted i got vga fine +damo22: i think linux kernel i915 is trying to do something with vgarom because it says "invalid rom contents" as first boot line +damo22: no i need to find out if the kernel is doing something bad without rom present +damo22: and then figure out how to enable lvds, because vga is working +fchmmr: drivers/pci/rom.c: dev_err(&pdev->dev, "Invalid ROM contents\n"); +fchmmr: in that: size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size) +fchmmr: /* Standard PCI ROMs start out with these bytes 55 AA */ +fchmmr: if (readb(image) != 0x55) { +fchmmr: dev_err(&pdev->dev, "Invalid ROM contents\n"); +fchmmr: break; +fchmmr: } +damo22: i guess i should focus on the fact that coreboot did not initialise the gfx at grub screen +damo22: i mean seabios +damo22: its difficult because linux does some reinitialisation of gfx +damo22: i thought i had this one in the bag +CareBear\: damo22 : it does complete reinit +damo22: i flicked throught the kernel i915 driver and it looks like it reads VBT tables from romheaders or something +damo22: if we are using native gfx init, those are not present right? +samnob: damo22: I think you need to be using grub2 to test native gfx init, seabios needs at least a stub of a vgarom. +CareBear\: damo22 : correct +CareBear\: samnob damo22 : if you want to use SeaBIOS you can use the SeaVGABIOS which will pick up a native framebuffer initialized by coreboot +damo22: does SeaVGABIOS install VBT stuff in the vgarom area? +CareBear\: damo22 : probably not the kind the framebuffer driver looks for +damo22: then it will fail with linux +CareBear\: damo22 : yes +damo22: CareBear\: can we write a vgabios stub that passes the signature tests and also has native VBT tables, but executes nothing? +damo22: otherwise we need to patch the linux kernel to ignore certain models that have no vgabios +CareBear\: damo22 : let's first find out what information is used in those tables +damo22: i have the code in front of me +damo22: drivers/gpu/drm/i915/intel_bios.c (kernel) +damo22: fchmmr: no, i am trawling through linux driver code +fchmmr: damo22: are you aware that certain kernels can initialize the GPU on X60 without the native gfx or oprom? (you don't see payloads, but kernel/X11 shows display +damo22: i have a feeling the linux kernel currently tries to load the vgarom regardless of PCH existance + +damo22: i think there are two problems with native gfx init, one problem is that the lvds isnt coming up (coreboot issue), the other is is with the linux kernel i915 driver that tries to read the vgarom that isnt there + +fchmmr: damo22, what hardware are you testing your changes on? +fchmmr: Did you try 5320 without your changes? +fchmmr: (hardware: X60 or T60) + +Peter on 5320 talks about vga pipe not being enabled: this means that payload doesn't appear +on vga (only on lvds). OS can output on vga or lvds. so we need to get 5320 to output (during payload) on vga + +damo22: i just slept on it, and i think i know what the problem is + + * LVDS discovery: + * 1) check for EDID on DDC + * 2) check for VBT data + * 3) check to see if LVDS is already on + * if none of the above, no panel + + +1) it cant find the EDID because the i2c is failing to read with NAK +2) there is no VBT data because there is no vga option rom +3) coreboot is still not doing native init properly so the panel is still off + +Therefore linux assumes there is no LVDS. + +damo22: how do i enable cbmem console? i enabled it in menuconfig, do i need cbmem dynamically growing? +damo22: [*] Send console output to a CBMEM buffer\ +damo22: but i got nothing + +Guest-FR: Hi +Guest-FR: would you please check +Guest-FR: src/northbridge/intel/i945/gma.c +Guest-FR: function gma_func0_disable +Guest-FR: pci_write_config16(dev, GCFC, 0xa00) , sound wrong isn't it? + +damo22: Guest-FR: what do you think is wrong about it? +Guest-FR: per the datasheet (intel, so probably it is also wrong!) , the value should be "0x1b" +Guest-FR: page 74 +damo22: Guest-FR: can you link me to the datasheet +Guest-FR: damo22: congig16 is expecting 0x && 4 digits isn't it? +Guest-FR: damo22: e.i.: 0x1234 +damo22: Guest-FR: 0xa00 === 0x0a00 +damo22: same thing +Guest-FR: ok + +Guest-FR: here is the link for tha datasheet http://www.intel.com/Assets/PDF/datasheet/307502.pdf + +damo22: ty +damo22: Guest-FR: i am also working on this gma +damo22: Guest-FR: i am trying to figure out why native gfx init is not working on my X60 tablet + +Guest-FR: per gma.h, GCFC is 0xf0 /* Graphics Clock Frequency & Gating Control */ +damo22: Guest-FR: GCFC is missing from the datasheet +damo22: so how do you know its wrong +Guest-FR: it is my mistake.... I'm expecting to see 4 digits for conf16 +damo22: Guest-FR: ok, i would have expected GCFC to be on page 62 at the bottom but its missing +Guest-FR: probably we should make a dump to see the value we have with an original bios. what you think ? is it possible? +damo22: Guest-FR: however, GGC is mismatching between that datasheet and in coreboot gma +Guest-FR: intel is a fu*** company +damo22: ahh no, i looked up the wrong file +damo22: it matches +damo22: Guest-FR: i am assuming you are using patched gma to test? +Guest-FR: damo22: no, I use the original one +damo22: Guest-FR: http://review.coreboot.org/#/c/5320/ +Guest-FR: I try to port my board to coorboot https://github.com/coreboot-for-945g-m4/945g-m4 +Guest-FR: thx damo22 +damo22: Guest-FR: you need extra config in devicetree.cb with that +Guest-FR: damo22: http://review.coreboot.org/#/c/5762/ +damo22: Guest-FR: i cant view it +Guest-FR: oops, it is draft +Guest-FR: may I add you as a reviewer ? +damo22: Guest-FR: sure +Guest-FR: damo at zamodio? +damo22: correct +Guest-FR: done +Guest-FR: please feel free put comments (and be verbos, I'm not a developper :p ) +Guest-FR: probably my devicetree is not good, +damo22: it still wont load +Guest-FR: damien at zamaudio.com ? +damo22: yes +damo22: ok better +Guest-FR: probably you got an email ? +Guest-FR: for a review +damo22: Guest-FR: i dont see native gfx init +damo22: are you using vgarom? +Guest-FR: I'm using a PCIE card (Radeon X300) +damo22: dont you want to try to initialise the onboard gfx? +Guest-FR: why not, I'll give it a go :) +damo22: you showed me a whole bunch of code, but what is the problem? +Guest-FR: the serial is working, but it hang on "setting up static southbridge register ..." +Guest-FR: and some times, it went to "setting up Root Complex Topology" +damo22: Guest-FR: well, look for that message in the code and find the next message that should be displayed and you know the problem is between the two messaged +Guest-FR: there is some thing unstable +damo22: messages* +Guest-FR: ok +damo22: Guest-FR: if its too hard to find, add some printk's +damo22: i could really use a tip on how to enable cbmem console +damo22: im running blind + +Guest-FR: the msg ih at " src/northbridge/intel/i945/early_init.c " i945_setup_bars function +Guest-FR: so my problem is between "Setting up static southbridge registers..." and "Done" :) + +damo22: cat .config|grep CBMEM ===> http://paste.debian.net/101541/ why do i still not have any cbmem console? "No console found in coreboot table." +content of debian paste: +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_DYNAMIC_CBMEM is not set +CONFIG_CONSOLE_CBMEM=y +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +damo22: No coreboot CBMEM area found! +* Guest-FR (d5f5ab0b@gateway/web/freenode/ip.213.245.171.11) has joined #coreboot +Guest-FR: I'd like to understand: is there any difference betweent: pci_write_config16(LPC_DEV, 0x84, 0x0a01); + pci_write_config16(LPC_DEV, 0x86, 0x00fc); vs pci_write_config32(LPC_DEV, 0x84, 0x00fc0a01); +Guest-FR: for exemple: lenovo/x60/romstage.c we have: pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x1601); however in the ich7 datasheet page 364 it is a conf32 + +phcoder-screen: damo22: for C segment. boot with oprom, then dd if=/dev/mem bs=64k of=seg_cdef.bin skip=12 count=4 +damo22: ok +damo22: is that the VBT table? +phcoder-screen: part of it is +damo22: phcoder-screen: http://www.zamaudio.com/mbox2/seg_cdef.bin +damo22: it looks correct because it mentions calistoga +damo22: phcoder-screen: as a general solution, would it be possible to write a script that takes a vgarom as input and outputs a vgarom stub that will have no executable code but still have the VBT stuff and signatures to fool the OS that real vgarom is there, and will detect panels etc +damo22: or is there a better way? + +phcoder-screen: damo22: there is a better way: generate it in coreboot. I have a tool to partially parse the roms. Trying it with yours. +damo22: cool + +phcoder-screen: damo22: http://pastebin.com/GsYhSaNB +Content of that paste: +signature: <$VBT CALISTOGA > +version: 1.00 +VBT size: 0xea0 +VBT checksum: 0x0 +BDB version: 1.29 +section type 254, size 0xea + type: 0 + relstage: 64 + chipset: 1 + LVDS + No TV + rsvd3[0]: 0x8 + rsvd3[1]: 0x3 + rsvd3[2]: 0x31 + rsvd3[3]: 0x33 + Signon: 13Intel(r)Calistoga PCI Accelerated SVGA BIOS +Build Number: 1313d.dal PC 14.20 Dev 10/17/2006 0:22:30 +DECOMPILATION OR DISASSEMBLY PROHIBITED + + Copyright: + Code segment: a + DOS Boot mode: 0 + Bandwidth percent: c0 + rsvd4: 0x3 + Bandwidth percent: 8 + rsvd5: 0x4 +section type 1, size 0x5 +General features: + panel_fitting = 0x3 + flexaim = 0x1 + download_ext_vbt = 0x1 + *enable_ssc = 0x1 + *ssc_freq = 0x1 + *display_clock_mode = 0x0 + disable_smooth_vision = 0x0 + *fdi_rx_polarity_inverted = 0x0 + legacy_monitor_detect = 0x1 + *int_crt_support = 0x1 + *int_tv_support = 0x0 +section type 254, size 0x20 +section type 2, size 0xcb + *CRT DDC GMBUS pin: 2 + DPMS ACPI: 0 + Skip boot CRT detect: 0 + DPMS aim: 1 + boot_display: { 0, 0 } + 6 devices + *device type: 1009 (TV) + *dvo_port: 5 + *i2c_pin: 0 + *slave_addr: 0 + *ddc_pin: 0 + *dvo_wiring: 0 + edid_ptr: 0 + *device type: 1022 (flat panel) + *dvo_port: 4 + *i2c_pin: 0 + *slave_addr: 0 + *ddc_pin: 3 + *dvo_wiring: 0 + edid_ptr: 0 + *device type: 0 (Empty) + *device type: 0 (Empty) + *device type: 0 (Empty) + *device type: 0 (Empty) +section type 3, size 0x1 +section type 4, size 0x1c +section type 254, size 0x69 +section type 6, size 0x16d +section type 7, size 0x7 +section type 8, size 0x3d +section type 10, size 0xcb +section type 11, size 0xc7 +section type 12, size 0xf + *LVDS config: 1 + *Dual frequency: 1 +section type 13, size 0x3 +section type 14, size 0x9 +section type 15, size 0x8b +section type 16, size 0x84 +section type 17, size 0x8 +section type 18, size 0xc +section type 19, size 0x20 +section type 20, size 0x9e +section type 22, size 0x15 + *Panel type: 3 +section type 23, size 0x48 +section type 24, size 0x28 +section type 25, size 0x28 +section type 26, size 0x2 +section type 40, size 0x8 +section type 41, size 0x91 +section type 42, size 0x4a0 +section type 43, size 0x61 +section type 44, size 0x15 +damo22: phcoder-screen: does that mean for every supported board, an extra step will be needed to parse the roms so that the port can be done +damo22: *CRT DDC GMBUS pin: 2 +damo22: i think it is trying pin 3 +phcoder-screen: damo22: CRT is VGA +phcoder-screen: ddc_pin is 3 under lvds section +damo22: oh yeah +phcoder-screen: damo22: we already need some info in device tree to init. I think we can reuse it +phcoder-screen: I can upload my parser if you want +damo22: sure, i can parse my T60 and X60t +damo22: and eventually T61 +phcoder-screen: CL 5842 +damo22: thanks + +damo22: phcoder-screen: do you think the EDID is failing to read in linux because the VBT is missing? + +phcoder-screen: damo22: it's a likely explanation. I'd reput first 64k of your dump back to place +damo22: where does it belong in the flash? +damo22: c0000? +phcoder-screen: damo22: nowhere. c0000 is in RAM +damo22: so how do i ensure it gets loaded into ram at c0000 +phcoder-screen: damo22: memcpy +damo22: im convinced it will work if i do that +damo22: thats like loading the vgarom +damo22: but without executing it +phcoder-screen: damo22: yes +damo22: couldnt i just select it in menuconfig, but comment out the code that runs it? +phcoder-screen: yes +phcoder-screen: and keep in mind that oprom is self-modifying +damo22: yes so i need the final dump to load not the original +phcoder-screen: yes + + + +-- + +Side discussion (in #libreboot, not #coreboot as above): + +fchmmr: damo22: what was the problem? +damo22: EDID is not being read in linux +damo22: well it is, but it fails +damo22: probably because the VBT signature is missing from the oprom +fchmmr: oprom? +fchmmr: You mean native init code? +fchmmr: that it doesn't put the proper data in vbt +damo22: there is some special metadata in the oprom that native init doesnt put in +damo22: linux looks for it +damo22: thats how it knows where to read the EDID from +damo22: otherwise it uses a default address that could be wrong +damo22: in some cases it works +damo22: other cases like my X60t it fails +fchmmr: that would explain why "read-edid" utility deosn't work on natisev gfx at the mament +fchmmr: moment +fchmmr: Basstard` ^ + +damo22: fchmmr: phcoder wrote an experimental utility to parse some of the VBT tables from a vgarom +fchmmr: Did he share it with you? +damo22: yes +fchmmr: Did he upload it publicly? +damo22: http://review.coreboot.org/#/c/5842/ +fchmmr: Ok cool. +fchmmr: Do you think I should try it? + +damo22: you could use it to get more info from all your known boards, collect the parsed tables in a folder correctly named with the type of panel and the type of laptop +fchmmr: So as per #coreboot, my understanding is: move to new stolen memory address, find that metadata and how it's calculated and write that (memcpy/write32) in native init, get VBT tables parsed from ROM, replicate that in native gfx (stub code, just the addresses and pointers to the native init code) +fchmmr: Should this be run an a vgabios.bin, or on a system where vga bios is running (parse it in memory) ? +fchmmr: or both? +damo22: we havent got a solution for native init yet, but we do need to collect info from different models +damo22: to see how they compare +fchmmr: yes so, vgabios.bin (file) or running vga bios? +damo22: and also we can add it to devicetree.cb somehow later +damo22: preferably the running vgabios +fchmmr: ok +damo22: you can dump it with this command: +damo22: sudo dd if=/dev/mem bs=64k of=runningvga.bin skip=12 count=1 + +damo22: coreboot/util/intelvbttool + +damo22: gcc intelvbttool.c -o intelvbttool + +fchmmr: it would be good for you to run intelvbttool on vgabios.bin and runningvgabios.bin. (where vgabios.bin is extracted from lenovo rom, and runningvgabios.bin is dd'd from memory after it executed) +fchmmr: right? +fchmmr: (I will do the same) +fchmmr: just runningvgabios.bin ? +damo22: its useless in the factory bios +damo22: for the purposes of this test +fchmmr: ok +fchmmr: Can't hurt though (might be useful later). +damo22: not really, it might be modified at runtime and we wont know anything about it +damo22: we need final values +damo22: the rest is irrelevant +fchmmr: Yes. I was saying to run it on final dump, and factory dump. +fchmmr: but ok, i will only do it for final dump + +-- + +further discussion, continued in #coreboot: + +damo22:we could generate fake_vbt arrays for each model +damo22:fchmmr: whats the link to the vbt stuff again +fchmmr: http://review.coreboot.org/#/c/5396 for X230 +damo22:fchmmr: no on libreboot +fchmmr: I also added this to the notes at http://libreboot.org/howto.html#i945_vbt and http://libreboot.org/howto.html#intelvbttool_results for future reference. +fchmmr: on libreboot? I don't understand. +damo22:its possible that the VBT is modified by the vgarom depending on the panel it detects, assuming it can do that +damo22:only problem is, you need info from the VBT to know where to read the EDID, so how does the vgarom do it? +damo22:maybe its safe to assume that the EDID i2c will be the same for all panels +fchmmr: Might be hardcoded (what CareBear calls "stupid magic numbers") +damo22:so we should check all VBTs of the same laptop model and verify that the EDID i2c or ddc pin is the same for all panel types +fchmmr: Sorry, when you say VBT do you mean the runningvga.bin dump taken with dd when vgarom is running? +damo22:then we can hardcode that value into the coreboot devicetree.cb + +fchmmr: I see. it's an i2c bus that connects lvds/vga/vga out +kmalkki:damo22: in your opinion, where is this EDID eeprom physically located? +damo22:kmalkki: on the panel, or the transformer for the panel +kmalkki:damo22: what do you think is a transformer for the panel? +damo22:some circuitry that interfaces between the lvds connector and the panel itself +damo22:on the T60 there is a separate module afaik +damo22:on other models it might be incorporated into the panel idk +damo22:kmalkki: i believe that the VBT has information regarding which pin of the i2c to read for the EDID eeprom/storage +damo22:and it varies panel to panel +kmalkki:would it surprise you DDC signals are often not on the panel connector +damo22:hmm + +kmalkki:like, x60 schematics is easily available, do check on some alternative ways how these are done +damo22:ok + +kmalkki:damo22: for t60 however... LCD connector does have EDID lines +damo22:kmalkki: well it would be nice to have a general solution to EDID reading +damo22:i need to understand the wiring more and the VBT +kmalkki:DDC signals originate from the graphics device +kmalkki:that will be Intel for some, ATI for some T60 ? + +damo22:kmalkki: linux expects the VBT to be in the vgarom memory area, because it uses it to identify when a panel exists, so coreboot should provide VBT like a vendor bios ? + +damo22:when vgarom is used with coreboot there is no problem , but for native gfx init it doesnt always work +kmalkki:ok.. so we can ignore ATI case for now +damo22:kmalkki: is that because no native init will be done for that case? +damo22:so the vgarom will always work +kmalkki:ok.. so do you know VBT format? +damo22:kmalkki: phcoder has done lots of work on it already +kmalkki:and.. is there a problem in reading the EDID? +damo22:kmalkki: idk yet, i need to test +damo22:im having trouble building a coreboot rom that uses coreboots native framebuffer so i can see if it worked +damo22:linux reinits the gfx so its not a good test +damo22:but in any case, without the VBT, linux cant reinit my gfx +damo22:it fails to read the EDID +damo22:and without a dock, and cbmem console isnt working, i cant get the coreboot log to check what actually happened +kmalkki:what do you mean cbmem console not working? +damo22:kmalkki: i enabled it in menuconfig and built a rom, but when i run it on my X60t cbmem -c reports No console found +kmalkki:we should get it fixed then +kmalkki:paste your .config +damo22:http://paste.debian.net/101644/ + +kmalkki:git hash is from local tree.. it does work on master, right? +damo22:idk +damo22:i just cherry picked some native gfx patches +damo22:why would it affect cbmem console +kmalkki:mess up MTRRs or memory space mapping or UMA region... +damo22:ok +kmalkki:are those patches on gerrit you picked? +damo22:well i need these patches because that is why i need the console +damo22:yes +damo22:actually i did minor changes too +damo22::S +kmalkki:yep.. which patches exactly +damo22:5320 +damo22:then i changed 2 lines +damo22:a minor devicetree.cb line and this: +damo22:- intel_gma_init(conf, pci_read_config32(dev, 0x5c) & ~0xf, +damo22:+ intel_gma_init(conf, pci_read_config32(dev, 0x5c) & ~0xfffff, +kmalkki:ok.. also paste 'git log' so I find common hash from master +damo22:http://paste.debian.net/101645/ + +damo22:does anyone have better google xen than me, i cant seem to find a pdf of x60 schematics +Basstard' damo22: Do you mean this? http://www.computerservice.es/wp-content/uploads/2013/05/IBM-X60.pdf + +damo22:yep thanks +kmalkki:and now that I am awake, I see DDC signals on x60 LCD too +kmalkki:just.. no DDC or I2C in the signal name but EDID +damo22:yeah +damo22:what bus does the lvds connector use +damo22:is that i2c? +damo22:or should i say, how standard is that lcd connector they are using on the X60 +kmalkki:mainboard side is completely non-standard AFAIK +damo22:ohhh +kmalkki:panel side has a few variants on the LVDS input +damo22:ok +damo22:this is not easy to generalise then +damo22:SPWG_EDID_CLK and SPWG_EDID_DATA are the signals i found on the connector + +kmalkki:yes. and it looks like phcoder-screen has done all the work to read the EDID +damo22:yes but the address and pins required are stored in the VBT i think +kmalkki:solve your CBMEM console, please +damo22:yea +Basstard' damo22: Here's a cleaner one: http://pdf.datasheetarchive.com/indexerfiles/Datasheets-USER/DSAUPLD00006054.pdf +kmalkki:just verify 1315730 works +damo22:1315730? + +GNUtoo-irssi: fchmmr: hi, 0x58BF58BE works fine --- cool. (not related to these discussions, but GNUtoo is happy). + + +GNUtoo-irssi: phcoder-screen: if you're still working on native GPU init for i945(it seems so), I've an observation: +GNUtoo-irssi: gtt is not setup correctly anymore with your versions, the kenrel complains +GNUtoo-irssi: it was with a replay version, so if you're still working on it it may be an usefull hint +GNUtoo-irssi: I've added the code that works inside git, so if you want/need it, ping me +phcoder-screen:damo22: yes +GNUtoo-irssi: beside the kernel warning, the effect is slow 3D with a 3.10 lts kernel +damo22:GNUtoo-irssi: can you push it as a notformerge? +GNUtoo-irssi: ok, good idea +GNUtoo-irssi: ah sigh, again... +GNUtoo-irssi: ! [remote rejected] HEAD -> refs/for/master/NOTFORMERGE-reference-i915_gpu_init-x60 (change 3992 closed) +GNUtoo-irssi: I'll change the IDs +damo22:GNUtoo-irssi: have you seen 5230? +damo22:5320* +phcoder-screen:damo22: rank 0 of either channel is configured but not rank 1 +GNUtoo-irssi: let me look +GNUtoo-irssi: I've tried some recent branch for the t60 +GNUtoo-irssi: it works well, beside the gtt init issue I just described +damo22:GNUtoo-irssi: given that you were working on 3992 which is closed are you able to rebase your changes on top of 5320? +damo22:hmm 3992 was merged +damo22:phcoder-screen: my dimms are dual rank ++ + diff --git a/docs/future/dumps/x b/docs/future/dumps/x new file mode 100644 index 0000000..1ef5139 --- /dev/null +++ b/docs/future/dumps/x @@ -0,0 +1,1442 @@ + + +coreboot-4.0-6196-g1aa8cbd-7BETC7WW (2.08 ) Tue Jun 3 22:16:33 BST 2014 starting... + +Mobile Intel(R) 82945GM/GME Express Chipset +(G)MCH capable of up to FSB 800 MHz +(G)MCH capable of up to DDR2-667 +Setting up static southbridge registers... GPIOS... done. +Disabling Watchdog reboot... done. +Setting up static northbridge registers... done. +Waiting for MCHBAR to come up...ok +PM1_CNT: 00001c00 +SMBus controller enabled. +Setting up RAM controller. +This mainboard supports Dual Channel Operation. +DDR II Channel 0 Socket 0: x16DS +DDR II Channel 1 Socket 0: x8DDS +Memory will be driven at 667MHz with CAS=5 clocks +tRAS = 15 cycles +tRP = 5 cycles +tRCD = 5 cycles +Refresh: 7.8us +tWR = 5 cycles +DIMM 0 side 0 = 512 MB +DIMM 0 side 1 = 512 MB +DIMM 2 side 0 = 1024 MB +DIMM 2 side 1 = 1024 MB +tRFC = 43 cycles +Setting Graphics Frequency... +FSB: 667 MHz Voltage: 1.05V Render: 250Mhz Display: 200MHz +Setting Memory Frequency... CLKCFG=0x00010023, CLKCFG=0x00010043, ok +Setting mode of operation for memory channels...Dual Channel Assymetric. +Programming Clock Crossing...MEM=667 FSB=667... ok +Setting RAM size... +C0DRB = 0x20202010 +C1DRB = 0x60606040 +TOLUD = 0x00c0 +Setting row attributes... +C0DRA = 0x0033 +C1DRA = 0x0033 +DIMM0 has 8 banks. +DIMM2 has 8 banks. +one dimm per channel config.. +Initializing System Memory IO... +Programming Dual Channel RCOMP +Table Index: 3 +Programming DLL Timings... +Enabling System Memory IO... +jedec enable sequence: bank 0 +jedec enable sequence: bank 1 +bankaddr from bank size of rank 0 +jedec enable sequence: bank 4 +bankaddr from bank size of rank 1 +jedec enable sequence: bank 5 +bankaddr from bank size of rank 4 +receive_enable_autoconfig() for channel 0 + find_strobes_low() + set_receive_enable() medium=0x3, coarse=0x5 + set_receive_enable() medium=0x1, coarse=0x5 + find_strobes_edge() + set_receive_enable() medium=0x1, coarse=0x5 + set_receive_enable() medium=0x3, coarse=0x5 + set_receive_enable() medium=0x1, coarse=0x5 + add_quarter_clock() mediumcoarse=15 fine=f3 + set_receive_enable() medium=0x3, coarse=0x5 + find_preamble() + set_receive_enable() medium=0x3, coarse=0x4 + set_receive_enable() medium=0x3, coarse=0x3 + add_quarter_clock() mediumcoarse=0f fine=73 + normalize() + set_receive_enable() medium=0x0, coarse=0x4 +receive_enable_autoconfig() for channel 1 + find_strobes_low() + set_receive_enable() medium=0x3, coarse=0x5 + set_receive_enable() medium=0x1, coarse=0x5 + find_strobes_edge() + set_receive_enable() medium=0x1, coarse=0x5 + add_quarter_clock() mediumcoarse=15 fine=c5 + set_receive_enable() medium=0x3, coarse=0x5 + find_preamble() + set_receive_enable() medium=0x3, coarse=0x4 + set_receive_enable() medium=0x3, coarse=0x3 + add_quarter_clock() mediumcoarse=0f fine=45 + normalize() + set_receive_enable() medium=0x0, coarse=0x4 +RAM initialization finished. +Setting up Egress Port RCRB +Loading p + +*** Log truncated, 497 characters dropped. *** + +Adding CBMEM entry as no. 3 +Trying CBFS ramstage loader. +CBFS: loading stage fallback/ramstage @ 0x100000 (417848 bytes), entry @ 0x100000 +coreboot-4.0-6196-g1aa8cbd-7BETC7WW (2.08 ) Tue Jun 3 22:16:33 BST 2014 booting... +BS: Entering BS_PRE_DEVICE state. +BS: Exiting BS_PRE_DEVICE state. +BS: BS_PRE_DEVICE times (us): entry 0 run 2975 exit 0 +BS: Entering BS_DEV_INIT_CHIPS state. +BS: Exiting BS_DEV_INIT_CHIPS state. +BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 3324 exit 0 +BS: Entering BS_DEV_ENUMERATE state. +Enumerating buses... +Show all devs...Before device enumeration. +Root Device: enabled 1 +CPU_CLUSTER: 0: enabled 1 +APIC: 00: enabled 1 +DOMAIN: 0000: enabled 1 +PCI: 00:00.0: enabled 1 +PCI: 00:02.0: enabled 1 +PCI: 00:02.1: enabled 1 +PCI: 00:1b.0: enabled 1 +PCI: 00:1c.0: enabled 1 +PCI: 00:1c.1: enabled 1 +PCI: 00:1d.0: enabled 1 +PCI: 00:1d.1: enabled 1 +PCI: 00:1d.2: enabled 1 +PCI: 00:1d.3: enabled 1 +PCI: 00:1d.7: enabled 1 +PCI: 00:1f.0: enabled 1 +PNP: 00ff.1: enabled 1 +PNP: 00ff.2: enabled 1 +PNP: 164e.2: enabled 1 +PNP: 164e.3: enabled 0 +PNP: 164e.7: enabled 1 +PNP: 164e.19: enabled 1 +PNP: 002e.0: enabled 0 +PNP: 002e.1: enabled 1 +PNP: 002e.2: enabled 0 +PNP: 002e.3: enabled 1 +PNP: 002e.7: enabled 1 +PNP: 002e.a: enabled 0 +PCI: 00:1f.1: enabled 1 +PCI: 00:1f.2: enabled 1 +PCI: 00:1f.3: enabled 1 +I2C: 00:69: enabled 1 +I2C: 00:54: enabled 1 +I2C: 00:55: enabled 1 +I2C: 00:56: enabled 1 +I2C: 00:57: enabled 1 +I2C: 00:5c: enabled 1 +I2C: 00:5d: enabled 1 +I2C: 00:5e: enabled 1 +I2C: 00:5f: enabled 1 +Compare with tree... +Root Device: enabled 1 + CPU_CLUSTER: 0: enabled 1 + APIC: 00: enabled 1 + DOMAIN: 0000: enabled 1 + PCI: 00:00.0: enabled 1 + PCI: 00:02.0: enabled 1 + PCI: 00:02.1: enabled 1 + PCI: 00:1b.0: enabled 1 + PCI: 00:1c.0: enabled 1 + PCI: 00:1c.1: enabled 1 + PCI: 00:1d.0: enabled 1 + PCI: 00:1d.1: enabled 1 + PCI: 00:1d.2: enabled 1 + PCI: 00:1d.3: enabled 1 + PCI: 00:1d.7: enabled 1 + PCI: 00:1f.0: enabled 1 + PNP: 00ff.1: enabled 1 + PNP: 00ff.2: enabled 1 + PNP: 164e.2: enabled 1 + PNP: 164e.3: enabled 0 + PNP: 164e.7: enabled 1 + PNP: 164e.19: enabled 1 + PNP: 002e.0: enabled 0 + PNP: 002e.1: enabled 1 + PNP: 002e.2: enabled 0 + PNP: 002e.3: enabled 1 + PNP: 002e.7: enabled 1 + PNP: 002e.a: enabled 0 + PCI: 00:1f.1: enabled 1 + PCI: 00:1f.2: enabled 1 + PCI: 00:1f.3: enabled 1 + I2C: 00:69: enabled 1 + I2C: 00:54: enabled 1 + I2C: 00:55: enabled 1 + I2C: 00:56: enabled 1 + I2C: 00:57: enabled 1 + I2C: 00:5c: enabled 1 + I2C: 00:5d: enabled 1 + I2C: 00:5e: enabled 1 + I2C: 00:5f: enabled 1 +scan_static_bus for Root Device +CPU_CLUSTER: 0 enabled +DOMAIN: 0000 enabled +DOMAIN: 0000 scanning... +PCI: pci_scan_bus for bus 00 +PCI: 00:00.0 [8086/27a0] ops +PCI: 00:00.0 [8086/27a0] enabled +PCI: 00:02.0 [8086/27a2] ops +PCI: 00:02.0 [8086/27a2] enabled +PCI: 00:02.1 [8086/27a6] ops +PCI: 00:02.1 [8086/27a6] enabled +PCI: 00:1b.0 [8086/27d8] ops +PCI: 00:1b.0 [8086/27d8] enabled +PCI: 00:1c.0 [8086/0000] bus ops +PCI: 00:1c.0 [8086/27d0] enabled +PCI: 00:1c.1 [8086/0000] bus ops +PCI: 00:1c.1 [8086/27d2] enabled +PCI: 00:1c.2 [8086/0000] bus ops +PCI: 00:1c.2 [8086/27d4] enabled +PCI: 00:1c.3 [8086/0000] bus ops +PCI: 00:1c.3 [8086/27d6] enabled +PCI: 00:1d.0 [8086/27c8] ops +PCI: 00:1d.0 [8086/27c8] enabled +PCI: 00:1d.1 [8086/27c9] ops +PCI: 00:1d.1 [8086/27c9] enabled +PCI: 00:1d.2 [8086/27ca] ops +PCI: 00:1d.2 [8086/27ca] enabled +PCI: 00:1d.3 [8086/27cb] ops +PCI: 00:1d.3 [8086/27cb] enabled +PCI: 00:1d.7 [8086/27cc] ops +PCI: 00:1d.7 [8086/27cc] enabled +PCI: 00:1e.0 [8086/2448] bus ops +PCI: 00:1e.0 [8086/2448] enabled +PCI: 00:1f.0 [8086/27b9] bus ops +PCI: 00:1f.0 [8086/27b9] enabled +PCI: 00:1f.1 [8086/27df] ops +PCI: 00:1f.1 [8086/27df] enabled +PCI: 00:1f.2 [8086/0000] ops +PCI: 00:1f.2 [8086/27c4] enabled +PCI: 00:1f.3 [8086/27da] bus ops +PCI: 00:1f.3 [8086/27da] enabled +do_pci_scan_bridge for PCI: 00:1c.0 +PCI: pci_scan_bus for bus 01 +PCI: 01:00.0 [8086/109a] enabled +PCI: pci_scan_bus returning with max=001 +do_pci_scan_bridge returns max 1 +do_pci_scan_bridge for PCI: 00:1c.1 +PCI: pci_scan_bus for bus 02 +PCI: 02:00.0 [168c/002b] enabled +PCI: pci_scan_bus returning with max=002 +do_pci_scan_bridge returns max 2 +do_pci_scan_bridge for PCI: 00:1c.2 +PCI: pci_scan_bus for bus 03 +PCI: pci_scan_bus returning with max=003 +do_pci_scan_bridge returns max 3 +do_pci_scan_bridge for PCI: 00:1c.3 +PCI: pci_scan_bus for bus 04 +PCI: pci_scan_bus returning with max=004 +do_pci_scan_bridge returns max 4 +do_pci_scan_bridge for PCI: 00:1e.0 +PCI: pci_scan_bus for bus 05 +PCI: 05:00.0 [1180/0476] bus ops +PCI: 05:00.0 [1180/0476] enabled +PCI: 05:00.1 [1180/0552] enabled +PCI: 05:00.2 [1180/0822] enabled +PCI: 05:00.3 [1180/0843] enabled +do_pci_scan_bridge for PCI: 05:00.0 +PCI: pci_scan_bus for bus 06 +PCI: pci_scan_bus returning with max=006 +do_pci_scan_bridge returns max 6 +PCI: pci_scan_bus returning with max=006 +do_pci_scan_bridge returns max 6 +scan_static_bus for PCI: 00:1f.0 +WARNING: No CMOS option 'touchpad'. +PNP: 00ff.1 enabled +recv_ec_data: 0x37 +recv_ec_data: 0x42 +recv_ec_data: 0x48 +recv_ec_data: 0x54 +recv_ec_data: 0x33 +recv_ec_data: 0x37 +recv_ec_data: 0x57 +recv_ec_data: 0x57 +recv_ec_data: 0x04 +recv_ec_data: 0x03 +recv_ec_data: 0x00 +recv_ec_data: 0x11 +EC Firmware ID 7BHT37WW-3.4, Version 0.01B +recv_ec_data: 0x00 +recv_ec_data: 0x10 +recv_ec_data: 0x20 +recv_ec_data: 0x30 +recv_ec_data: 0x00 +recv_ec_data: 0xa6 +recv_ec_data: 0x01 +recv_ec_data: 0x30 +PNP: 00ff.2 enabled +PNP: 164e.2 enabled +PNP: 164e.3 disabled +PNP: 164e.7 enabled +PNP: 164e.19 enabled +PNP: 002e.0 disabled +PNP: 002e.1 enabled +PNP: 002e.2 disabled +PNP: 002e.3 enabled +PNP: 002e.7 enabled +PNP: 002e.a disabled +scan_static_bus for PCI: 00:1f.0 done +scan_static_bus for PCI: 00:1f.3 +smbus: PCI: 00:1f.3[0]->I2C: 01:69 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:54 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:55 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:56 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:57 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:5c enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:5d enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:5e enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:5f enabled +scan_static_bus for PCI: 00:1f.3 done +PCI: pci_scan_bus returning with max=006 +scan_static_bus for Root Device done +done +BS: Exiting BS_DEV_ENUMERATE state. +BS: BS_DEV_ENUMERATE times (us): entry 0 run 529332 exit 0 +BS: Entering BS_DEV_RESOURCES state. +found VGA at PCI: 00:02.0 +Setting up VGA for PCI: 00:02.0 +Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 +Setting PCI_BRIDGE_CTL_VGA for bridge Root Device +Allocating resources... +Reading resources... +Root Device read_resources bus 0 link: 0 +CPU_CLUSTER: 0 read_resources bus 0 link: 0 +APIC: 00 missing read_resources +CPU_CLUSTER: 0 read_resources bus 0 link: 0 done +DOMAIN: 0000 read_resources bus 0 link: 0 +Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000. +PCI: 00:1c.0 read_resources bus 1 link: 0 +PCI: 00:1c.0 read_resources bus 1 link: 0 done +PCI: 00:1c.1 read_resources bus 2 link: 0 +PCI: 00:1c.1 read_resources bus 2 link: 0 done +PCI: 00:1c.2 read_resources bus 3 link: 0 +PCI: 00:1c.2 read_resources bus 3 link: 0 done +PCI: 00:1c.3 read_resources bus 4 link: 0 +PCI: 00:1c.3 read_resources bus 4 link: 0 done +PCI: 00:1e.0 read_resources bus 5 link: 0 +PCI: 05:00.0 read_resources bus 6 link: 0 +PCI: 05:00.0 read_resources bus 6 link: 0 done +PCI: 00:1e.0 read_resources bus 5 link: 0 done +PCI: 00:1f.0 read_resources bus 0 link: 0 +PNP: 00ff.1 missing read_resources +PNP: 00ff.2 missing read_resources +PCI: 00:1f.0 read_resources bus 0 link: 0 done +PCI: 00:1f.3 read_resources bus 1 link: 0 +PCI: 00:1f.3 read_resources bus 1 link: 0 done +DOMAIN: 0000 read_resources bus 0 link: 0 done +Root Device read_resources bus 0 link: 0 done +Done reading resources. +Show resources in subtree (Root Device)...After reading. + Root Device child on link 0 CPU_CLUSTER: 0 + CPU_CLUSTER: 0 child on link 0 APIC: 00 + APIC: 00 + DOMAIN: 0000 child on link 0 PCI: 00:00.0 + DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 + DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 + PCI: 00:00.0 + PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf + PCI: 00:02.0 + PCI: 00:02.0 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 200 index 10 + PCI: 00:02.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 14 + PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 1200 index 18 + PCI: 00:02.0 resource base 0 size 40000 align 18 gran 18 limit ffffffff flags 200 index 1c + PCI: 00:02.1 + PCI: 00:02.1 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 200 index 10 + PCI: 00:1b.0 + PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 + PCI: 00:1c.0 child on link 0 PCI: 01:00.0 + PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 01:00.0 + PCI: 01:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10 + PCI: 01:00.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18 + PCI: 00:1c.1 child on link 0 PCI: 02:00.0 + PCI: 00:1c.1 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 02:00.0 + PCI: 02:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10 + PCI: 00:1c.2 + PCI: 00:1c.2 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 00:1c.3 + PCI: 00:1c.3 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 00:1d.0 + PCI: 00:1d.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1d.1 + PCI: 00:1d.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1d.2 + PCI: 00:1d.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1d.3 + PCI: 00:1d.3 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1d.7 + PCI: 00:1d.7 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 10 + PCI: 00:1e.0 child on link 0 PCI: 05:00.0 + PCI: 00:1e.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 05:00.0 + PCI: 05:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 + PCI: 05:00.0 resource base 0 size 1000 align 2 gran 2 limit ffffffff flags 100 index 2c + PCI: 05:00.0 resource base 0 size 1000 align 2 gran 2 limit ffffffff flags 100 index 34 + PCI: 05:00.0 resource base 0 size 2000000 align 12 gran 12 limit ffffffff flags 1200 index 1c + PCI: 05:00.0 resource base 0 size 2000000 align 12 gran 12 limit ffffffff flags 200 index 24 + PCI: 05:00.1 + PCI: 05:00.1 resource base 0 size 800 align 11 gran 11 limit ffffffff flags 200 index 10 + PCI: 05:00.2 + PCI: 05:00.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 + PCI: 05:00.3 + PCI: 05:00.3 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 + PCI: 00:1f.0 child on link 0 PNP: 00ff.1 + PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 + PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 + PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 + PNP: 00ff.1 + PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77 + PNP: 00ff.2 + PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 + PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 + PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64 + PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66 + PNP: 164e.2 + PNP: 164e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 75 + PNP: 164e.3 + PNP: 164e.3 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 164e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 164e.7 + PNP: 164e.7 resource base 1680 size 10 align 4 gran 4 limit ffff flags c0000100 index 60 + PNP: 164e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 164e.19 + PNP: 164e.19 resource base 164c size 2 align 1 gran 1 limit ffff flags c0000100 index 60 + PNP: 164e.19 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.0 + PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60 + PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.1 + PNP: 002e.1 resource base 3bc size 400 align 10 gran 10 limit 7ff flags c0000100 index 60 + PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.2 + PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 75 + PNP: 002e.3 + PNP: 002e.3 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 002e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.7 + PNP: 002e.7 resource base 1620 size 8 align 3 gran 3 limit ffff flags c0000100 index 60 + PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.a + PNP: 002e.a resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 60 + PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PCI: 00:1f.1 + PCI: 00:1f.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 + PCI: 00:1f.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 + PCI: 00:1f.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 + PCI: 00:1f.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c + PCI: 00:1f.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 + PCI: 00:1f.2 + PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 + PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 + PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 + PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c + PCI: 00:1f.2 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 + PCI: 00:1f.2 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 24 + PCI: 00:1f.3 child on link 0 I2C: 01:69 + PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20 + I2C: 01:69 + I2C: 01:54 + I2C: 01:55 + I2C: 01:56 + I2C: 01:57 + I2C: 01:5c + I2C: 01:5d + I2C: 01:5e + I2C: 01:5f +DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff +PCI: 00:1c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 01:00.0 18 * [0x0 - 0x1f] io +PCI: 00:1c.0 compute_resources_io: base: 20 size: 1000 align: 12 gran: 12 limit: ffff done +PCI: 00:1c.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 00:1c.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done +PCI: 00:1c.2 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 00:1c.2 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done +PCI: 00:1c.3 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 00:1c.3 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done +PCI: 00:1e.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 05:00.0 2c * [0x0 - 0xfff] io +PCI: 05:00.0 34 * [0x1000 - 0x1fff] io +PCI: 00:1e.0 compute_resources_io: base: 2000 size: 2000 align: 12 gran: 12 limit: ffff done +PCI: 00:1e.0 1c * [0x0 - 0x1fff] io +PCI: 00:1c.0 1c * [0x2000 - 0x2fff] io +PCI: 00:1d.0 20 * [0x3000 - 0x301f] io +PCI: 00:1d.1 20 * [0x3020 - 0x303f] io +PCI: 00:1d.2 20 * [0x3040 - 0x305f] io +PCI: 00:1d.3 20 * [0x3060 - 0x307f] io +PCI: 00:1f.1 20 * [0x3080 - 0x308f] io +PCI: 00:1f.2 20 * [0x3090 - 0x309f] io +PCI: 00:02.0 14 * [0x30a0 - 0x30a7] io +PCI: 00:1f.1 10 * [0x30a8 - 0x30af] io +PCI: 00:1f.1 18 * [0x30b0 - 0x30b7] io +PCI: 00:1f.2 10 * [0x30b8 - 0x30bf] io +PCI: 00:1f.2 18 * [0x30c0 - 0x30c7] io +PCI: 00:1f.1 14 * [0x30c8 - 0x30cb] io +PCI: 00:1f.1 1c * [0x30cc - 0x30cf] io +PCI: 00:1f.2 14 * [0x30d0 - 0x30d3] io +PCI: 00:1f.2 1c * [0x30d4 - 0x30d7] io +DOMAIN: 0000 compute_resources_io: base: 30d8 size: 30d8 align: 12 gran: 0 limit: ffff done +DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff +PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:1c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 01:00.0 10 * [0x0 - 0x1ffff] mem +PCI: 00:1c.0 compute_resources_mem: base: 20000 size: 100000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1c.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:1c.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:1c.1 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 02:00.0 10 * [0x0 - 0xffff] mem +PCI: 00:1c.1 compute_resources_mem: base: 10000 size: 100000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1c.2 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:1c.2 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:1c.2 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 00:1c.2 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1c.3 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:1c.3 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:1c.3 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 00:1c.3 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1e.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 05:00.0 1c * [0x0 - 0x1ffffff] prefmem +PCI: 00:1e.0 compute_resources_prefmem: base: 2000000 size: 2000000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1e.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 05:00.0 24 * [0x0 - 0x1ffffff] mem +PCI: 05:00.0 10 * [0x2000000 - 0x2000fff] mem +PCI: 05:00.1 10 * [0x2001000 - 0x20017ff] mem +PCI: 05:00.2 10 * [0x2001800 - 0x20018ff] mem +PCI: 05:00.3 10 * [0x2001900 - 0x20019ff] mem +PCI: 00:1e.0 compute_resources_mem: base: 2001a00 size: 2100000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem +PCI: 00:1e.0 20 * [0x10000000 - 0x120fffff] mem +PCI: 00:1e.0 24 * [0x12100000 - 0x140fffff] prefmem +PCI: 00:1c.0 20 * [0x14100000 - 0x141fffff] mem +PCI: 00:1c.1 20 * [0x14200000 - 0x142fffff] mem +PCI: 00:02.0 10 * [0x14300000 - 0x1437ffff] mem +PCI: 00:02.1 10 * [0x14380000 - 0x143fffff] mem +PCI: 00:02.0 1c * [0x14400000 - 0x1443ffff] mem +PCI: 00:1b.0 10 * [0x14440000 - 0x14443fff] mem +PCI: 00:1d.7 10 * [0x14444000 - 0x144443ff] mem +PCI: 00:1f.2 24 * [0x14444400 - 0x144447ff] mem +DOMAIN: 0000 compute_resources_mem: base: 14444800 size: 14444800 align: 28 gran: 0 limit: ffffffff done +avoid_fixed_resources: DOMAIN: 0000 +avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff +avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff +constrain_resources: DOMAIN: 0000 +constrain_resources: PCI: 00:00.0 +constrain_resources: PCI: 00:02.0 +constrain_resources: PCI: 00:02.1 +constrain_resources: PCI: 00:1b.0 +constrain_resources: PCI: 00:1c.0 +constrain_resources: PCI: 01:00.0 +constrain_resources: PCI: 00:1c.1 +constrain_resources: PCI: 02:00.0 +constrain_resources: PCI: 00:1c.2 +constrain_resources: PCI: 00:1c.3 +constrain_resources: PCI: 00:1d.0 +constrain_resources: PCI: 00:1d.1 +constrain_resources: PCI: 00:1d.2 +constrain_resources: PCI: 00:1d.3 +constrain_resources: PCI: 00:1d.7 +constrain_resources: PCI: 00:1e.0 +constrain_resources: PCI: 05:00.0 +constrain_resources: PCI: 05:00.1 +constrain_resources: PCI: 05:00.2 +constrain_resources: PCI: 05:00.3 +constrain_resources: PCI: 00:1f.0 +constrain_resources: PNP: 00ff.1 +constrain_resources: PNP: 00ff.2 +skipping PNP: 00ff.2@60 fixed resource, size=0! +skipping PNP: 00ff.2@62 fixed resource, size=0! +skipping PNP: 00ff.2@64 fixed resource, size=0! +skipping PNP: 00ff.2@66 fixed resource, size=0! +constrain_resources: PNP: 164e.2 +constrain_resources: PNP: 164e.7 +constrain_resources: PNP: 164e.19 +constrain_resources: PNP: 002e.1 +constrain_resources: PNP: 002e.3 +constrain_resources: PNP: 002e.7 +constrain_resources: PCI: 00:1f.1 +constrain_resources: PCI: 00:1f.2 +constrain_resources: PCI: 00:1f.3 +constrain_resources: I2C: 01:69 +constrain_resources: I2C: 01:54 +constrain_resources: I2C: 01:55 +constrain_resources: I2C: 01:56 +constrain_resources: I2C: 01:57 +constrain_resources: I2C: 01:5c +constrain_resources: I2C: 01:5d +constrain_resources: I2C: 01:5e +constrain_resources: I2C: 01:5f +avoid_fixed_resources2: DOMAIN: 0000@10000000 limit 0000ffff + lim->base 00001690 lim->limit 0000ffff +avoid_fixed_resources2: DOMAIN: 0000@10000100 limit ffffffff + lim->base 00000000 lim->limit efffffff +Setting resources... +DOMAIN: 0000 allocate_resources_io: base:1690 size:30d8 align:12 gran:0 limit:ffff +Assigned: PCI: 00:1e.0 1c * [0x2000 - 0x3fff] io +Assigned: PCI: 00:1c.0 1c * [0x4000 - 0x4fff] io +Assigned: PCI: 00:1d.0 20 * [0x5000 - 0x501f] io +Assigned: PCI: 00:1d.1 20 * [0x5020 - 0x503f] io +Assigned: PCI: 00:1d.2 20 * [0x5040 - 0x505f] io +Assigned: PCI: 00:1d.3 20 * [0x5060 - 0x507f] io +Assigned: PCI: 00:1f.1 20 * [0x5080 - 0x508f] io +Assigned: PCI: 00:1f.2 20 * [0x5090 - 0x509f] io +Assigned: PCI: 00:02.0 14 * [0x50a0 - 0x50a7] io +Assigned: PCI: 00:1f.1 10 * [0x50a8 - 0x50af] io +Assigned: PCI: 00:1f.1 18 * [0x50b0 - 0x50b7] io +Assigned: PCI: 00:1f.2 10 * [0x50b8 - 0x50bf] io +Assigned: PCI: 00:1f.2 18 * [0x50c0 - 0x50c7] io +Assigned: PCI: 00:1f.1 14 * [0x50c8 - 0x50cb] io +Assigned: PCI: 00:1f.1 1c * [0x50cc - 0x50cf] io +Assigned: PCI: 00:1f.2 14 * [0x50d0 - 0x50d3] io +Assigned: PCI: 00:1f.2 1c * [0x50d4 - 0x50d7] io +DOMAIN: 0000 allocate_resources_io: next_base: 50d8 size: 30d8 align: 12 gran: 0 done +PCI: 00:1c.0 allocate_resources_io: base:4000 size:1000 align:12 gran:12 limit:ffff +Assigned: PCI: 01:00.0 18 * [0x4000 - 0x401f] io +PCI: 00:1c.0 allocate_resources_io: next_base: 4020 size: 1000 align: 12 gran: 12 done +PCI: 00:1c.1 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff +PCI: 00:1c.1 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done +PCI: 00:1c.2 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff +PCI: 00:1c.2 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done +PCI: 00:1c.3 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff +PCI: 00:1c.3 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done +PCI: 00:1e.0 allocate_resources_io: base:2000 size:2000 align:12 gran:12 limit:ffff +Assigned: PCI: 05:00.0 2c * [0x2000 - 0x2fff] io +Assigned: PCI: 05:00.0 34 * [0x3000 - 0x3fff] io +PCI: 00:1e.0 allocate_resources_io: next_base: 4000 size: 2000 align: 12 gran: 12 done +DOMAIN: 0000 allocate_resources_mem: base:d0000000 size:14444800 align:28 gran:0 limit:efffffff +Assigned: PCI: 00:02.0 18 * [0xd0000000 - 0xdfffffff] prefmem +Assigned: PCI: 00:1e.0 20 * [0xe0000000 - 0xe20fffff] mem +Assigned: PCI: 00:1e.0 24 * [0xe2100000 - 0xe40fffff] prefmem +Assigned: PCI: 00:1c.0 20 * [0xe4100000 - 0xe41fffff] mem +Assigned: PCI: 00:1c.1 20 * [0xe4200000 - 0xe42fffff] mem +Assigned: PCI: 00:02.0 10 * [0xe4300000 - 0xe437ffff] mem +Assigned: PCI: 00:02.1 10 * [0xe4380000 - 0xe43fffff] mem +Assigned: PCI: 00:02.0 1c * [0xe4400000 - 0xe443ffff] mem +Assigned: PCI: 00:1b.0 10 * [0xe4440000 - 0xe4443fff] mem +Assigned: PCI: 00:1d.7 10 * [0xe4444000 - 0xe44443ff] mem +Assigned: PCI: 00:1f.2 24 * [0xe4444400 - 0xe44447ff] mem +DOMAIN: 0000 allocate_resources_mem: next_base: e4444800 size: 14444800 align: 28 gran: 0 done +PCI: 00:1c.0 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.0 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.0 allocate_resources_mem: base:e4100000 size:100000 align:20 gran:20 limit:efffffff +Assigned: PCI: 01:00.0 10 * [0xe4100000 - 0xe411ffff] mem +PCI: 00:1c.0 allocate_resources_mem: next_base: e4120000 size: 100000 align: 20 gran: 20 done +PCI: 00:1c.1 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.1 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.1 allocate_resources_mem: base:e4200000 size:100000 align:20 gran:20 limit:efffffff +Assigned: PCI: 02:00.0 10 * [0xe4200000 - 0xe420ffff] mem +PCI: 00:1c.1 allocate_resources_mem: next_base: e4210000 size: 100000 align: 20 gran: 20 done +PCI: 00:1c.2 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.2 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.2 allocate_resources_mem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.2 allocate_resources_mem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.3 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.3 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.3 allocate_resources_mem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.3 allocate_resources_mem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1e.0 allocate_resources_prefmem: base:e2100000 size:2000000 align:20 gran:20 limit:efffffff +Assigned: PCI: 05:00.0 1c * [0xe2100000 - 0xe40fffff] prefmem +PCI: 00:1e.0 allocate_resources_prefmem: next_base: e4100000 size: 2000000 align: 20 gran: 20 done +PCI: 00:1e.0 allocate_resources_mem: base:e0000000 size:2100000 align:20 gran:20 limit:efffffff +Assigned: PCI: 05:00.0 24 * [0xe0000000 - 0xe1ffffff] mem +Assigned: PCI: 05:00.0 10 * [0xe2000000 - 0xe2000fff] mem +Assigned: PCI: 05:00.1 10 * [0xe2001000 - 0xe20017ff] mem +Assigned: PCI: 05:00.2 10 * [0xe2001800 - 0xe20018ff] mem +Assigned: PCI: 05:00.3 10 * [0xe2001900 - 0xe20019ff] mem +PCI: 00:1e.0 allocate_resources_mem: next_base: e2001a00 size: 2100000 align: 20 gran: 20 done +Root Device assign_resources, bus 0 link: 0 +pci_tolm: 0xd0000000 +Base of stolen memory: 0xbf800000 +Top of Low Used DRAM: 0xc0000000 +IGD decoded, subtracting 8M UMA +Available memory: 3137536K (3064M) +Adding PCIe config bar +DOMAIN: 0000 assign_resources, bus 0 link: 0 +PCI: 00:00.0 cf <- [0x00f0000000 - 0x00f3ffffff] size 0x04000000 gran 0x00 memGNUtoo-irssi: i am not too familiar with gerrit, but that error message seems to indicate that you should not try to push 3992 again because it is already merged... rebasing the remains of your changes on top of that (or origin/master) should fix that *i guess* + +URL to topic: http://review.coreboot.org/#/q/status:open+project:coreboot+branch:master+topic:NOTFORMERGE-reference-i915_gpu_init-x60,n,z +(note: this is old code, not *directly* useful but might be useful later. put this somewhere else in howto.html later) + +GNUtoo-irssi: done, NOTFORMERGE-reference-i915_gpu_init-x60 +GNUtoo-irssi: yes, I've removed the Ids +GNUtoo-irssi: so they were regenerated +GNUtoo-irssi: the goal is not to rebase at all here +GNUtoo-irssi: that's a reference code +GNUtoo-irssi: it's not for merge either +GNUtoo-irssi: If I start modifying it, I'll need to spend time testing it again +GNUtoo-irssi: I've no time right now +GNUtoo-irssi: maybe I'll have later in theses two weeks +GNUtoo-irssi: but not right now +damo22:GNUtoo-irssi: mainboard/lenovo/x60/i915* has been removed in favour of northbridge/intel/i945/gma.c in 5320 +damo22:i thought you had changes for that +GNUtoo-irssi: yes, I know +GNUtoo-irssi: what I just pushed is a *reference code* where the GTT setup works +GNUtoo-irssi: it's old +GNUtoo-irssi: it's not meant to be merged +GNUtoo-irssi: it's not rebased +GNUtoo-irssi: it's just frozen code where it's known to work +GNUtoo-irssi: that's all + +damo22:ok +GNUtoo-irssi: it doesn't even handle backlight +GNUtoo-irssi: even with devmem2... +damo22:i'll see if i can find the gtt stuff and compare to 5320 +damo22:could be a one liner +damo22:physbase -> uma_memory_base+256*KiB +phcoder-screen:damo22: yes and rank 1 config failed +damo22:phcoder-screen: ok, so i'll get you that mchbar dump +phcoder-screen:damo22: no need yet. I found out that in another ram config my X230 fails as well. I'll investigate this first + +kmalkki:GNUtoo-irssi: please abandon the duplicates in your gerrit space +kmalkki:also any microcode files will not be removed until working copies are in 3rdparty/ + +kmalkki:we probably want to keep the old version in gerrit, with all the comments made previously + +damo22:kmalkki: all those patches are noformerge +damo22:not* +kmalkki:damo22: still they are duplicates of already reviewed patches +kmalkki:why the heck the new change-ids +damo22:maybe a git diff to a pastebin would have been better + +GNUtoo-irssi: ls +GNUtoo-irssi: oops + hunter2 +kmalkki:GNUtoo-irssi: please explain your motivation to push that stuff on gerrit +kmalkki:it is not even rebased to current but 6 months old HEAD +GNUtoo-irssi: GTT is setup badly on x60 +GNUtoo-irssi: with the recent changes from phcoder +GNUtoo-irssi: what I pushed is a version that is known to have the GTT setup correctly +GNUtoo-irssi: it's for reference +GNUtoo-irssi: so people working on i945 native GPU init would use it to fix that issue faster +GNUtoo-irssi: like diff both +GNUtoo-irssi: or something like that +GNUtoo-irssi: kmalkki: do you have a better description for the topic branch name that describe what I just said? +kmalkki:well gerrit is not for the purpose of storing references +kmalkki:most of those patches already had Change-IDs +kmalkki:now we have duplicates.. and comments can end up in either place +kmalkki:it was already a havoc with native init before +GNUtoo-irssi: ok, so instead I should remove that branch, and push on gitorious? +kmalkki:all of You working on it, try to work a setup that suits you all well +GNUtoo-irssi: briefly: it's for tracking a regression + +kmalkki:well I do not do i915 gfx stuff.. but clearly you have a lot of problems trying to keep and follow each others work +kmalkki:and what works and where the regressions have happened +PaulePanter: GNUtoo-irssi: Hi. Do you know if the amount memory reserved for i945 IGD is always constant or if that is configurable? +PaulePanter: GNUtoo-irssi: I did not see a table in the 3rd Gen datasheet. +PaulePanter: http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/3rd-gen-core-family-mobile-vol-2-datasheet.pdf +GNUtoo-irssi: PaulePanter: you mean the GSM? +GNUtoo-irssi: (Graphics stolen memory) +PaulePanter: GNUtoo-irssi: Yes. + +PaulePanter: Section 2.5.33 BDSM—Base Data of Stolen Memory Register +GNUtoo-irssi: If I remmeber well it's configurable, but we use the values advised by the datasheet +GNUtoo-irssi: which are derived from the ammount of RAM +PaulePanter: This register contains the base address of graphics data stolen DRAM memory. BIOS determines the base of graphics data stolen memory by subtracting the graphics data stolen memory size (PCI Device 0 offset 52 bits 7:4) from TOLUD (PCI Device 0 offset BCh bits 31:20). +PaulePanter: GNUtoo-irssi: Yes, I am unable to find the advised values. +damo22:PaulePanter: are you sure thats the right datasheet for the cpu inside the X60? + +GNUtoo-irssi: ok +GNUtoo-irssi: I can look +PaulePanter: damo22: Not 100 %. +damo22:afaik, BSDM is something kinky in the core iX processors +GNUtoo-irssi: uma_size = 1024; +PaulePanter: Chris Wilson from the Intel graphics Linux driver team said that BDSM ist incorrectly set up. +PaulePanter: … on the i945. +PaulePanter: … by coreboot. +PaulePanter: This is Volume 2 of the Datasheet for the following products: +PaulePanter: Mobile 3rd Generation Intel ® CoreTM processor family +GNUtoo-irssi: in pci_domain_set_resources in northbridge.c +PaulePanter: Mobile Intel ® Pentium ® processor family +GNUtoo-irssi: ok +PaulePanter: Mobile Intel ® Celeron ® processor family +PaulePanter: GNUtoo-irssi: Thanks. So it is constant for now. +PaulePanter: GNUtoo-irssi: So just 1 MB graphics memory? + +damo22:i dont remember him mentioning BDSM in the bug report, but he did say the GTT was incorrectly set up? +damo22:graphics stolen stuff +GNUtoo-irssi: no it's not +GNUtoo-irssi: read the function +PaulePanter: “Stolen memory has been set up incorrectly by coreboot.” +PaulePanter: GNUtoo-irssi: Ok. +PaulePanter: GNUtoo-irssi: No idea, if you are aware of https://bugs.freedesktop.org/show_bug.cgi?id=79038 . +GNUtoo-irssi: http://paste.debian.net/101662/ +[ 0.764084] input: Video Bus as /devices/LNXSYSTM:00/device:00/PNP0A08:00/LNXVIDEO:00/input/input3 +[ 0.771023] pci 0000:00:00.0: Intel 945GM Chipset +[ 0.771075] pci 0000:00:00.0: detected gtt size: 262144K total, 262144K mappable +[ 0.771669] pci 0000:00:00.0: detected 8192K stolen memory +[ 0.771738] [drm] Memory usable by graphics device = 256M +[ 0.772124] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). +[ 0.772126] [drm] Driver supports precise vblank timestamp query. +[ 0.772133] i915 0000:00:02.0: Invalid ROM contents +[ 0.772141] [drm] failed to find VBIOS tables +[ 0.772192] [drm] GPU crash dump saved to /sys/class/drm/card0/error +[ 0.772196] [drm] GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace. +[ 0.772198] [drm] Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel +[ 0.772200] [drm] drm/i915 developers can then reassign to the right component if it's not a kernel issue. +[ 0.772202] [drm] The gpu crash dump is required to analyze gpu hangs, so please always attach it. +[ 0.772207] vgaarb: device changed decodes: PCI:0000:00:02.0,olddecodes=io+mem,decodes=io+mem:owns=io+mem +[ 0.772217] i915: render error detected, EIR: 0x00000010 +[ 0.772224] i915: page table error +[ 0.772227] i915: PGTBL_ER: 0x00000012 +[ 0.772233] [drm:i915_report_and_clear_eir] *ERROR* EIR stuck: 0x00000010, masking +[ 0.772247] i915: render error detected, EIR: 0x00000010 +[ 0.772252] i915: page table error +[ 0.772255] i915: PGTBL_ER: 0x00000012 +[ 0.924707] [drm] initialized overlay support +[ 1.126501] fbcon: inteldrmfb (fb0) is primary device +[ 1.360027] tsc: Refined TSC clocksource calibration: 1828.749 MHz +[ 1.482148] Console: switching to colour frame buffer device 175x65 +[ 1.490507] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device +[ 1.490510] i915 0000:00:02.0: registered panic notifier +[ 1.490522] [drm] Initialized i915 1.6.0 20080730 for 0000:00:02.0 on minor 0 +[ 1.491931] console [netcon0] enabled +[ 1.491933] netconsole: network logging started +[ 1.494021] ACPI: bus type USB registered +GNUtoo-irssi: that is the regression ^^^^ +GNUtoo-irssi: See PGTBL_ER +GNUtoo-irssi: The bits are documented +damo22:i have compared GNUtoo-irssi's patchset with the 5320 stuff that phcoder did, and i found that 1 line needs to be changed +GNUtoo-irssi: (I don't remember where, probably in the datasheet that applies to the more recent GPUs (sic)) + +damo22:its the base address of the gma init call + +PaulePanter: damo22: Are you going to push a patch for testing? + +damo22:but in order for it to work you need vgarom with native init, it doesnt run the rom just uses it for VBT +PaulePanter: damo22: I still not see how that should fix the error, but we’ll see. +damo22:how do i squash my commits into one patch that can be applied to 5320? +PaulePanter: damo22: Is that patch really dependent on 5320? I thought it is also needed for the current native graphics init in the tree? + +PaulePanter: damo22: `git rebase -i +PaulePanter: ` +PaulePanter: damo22: git rebase -i commit-hash-of-5320 +damo22:thanks +PaulePanter: damo22: To squash you will need to change `pick` to `f` or `s` for `fixup` or `squash`. + +damo22:i have a patch that could be tested on X60: http://review.coreboot.org/#/c/5868/ +PaulePanter: damo22: On Nehalem: +PaulePanter: src/northbridge/intel/nehalem/gma.c: intel_gma_init(conf, gtt_res->base, physbase, pio_res->base, +PaulePanter: src/northbridge/intel/nehalem/gma.c- lfb_res->base); +damo22:PaulePanter: i fail to see relevance of nehalem in i945 +PaulePanter: damo22: Hopefully the code can be written in a way that common paths are written the same. +PaulePanter: damo22: Let’s first see if the patch fixes it. + +PaulePanter: damo22: By the way, which datasheet do you think is correct for the Intel 945 IGD in the Lenovo T60 and X60? + +damo22:whichever datasheet includes 945PM (Calistoga) Graphics +damo22:is it PM or GM? +PaulePanter: damo22: I thought GM. +damo22:PM has no integrated graphics so it must be GM +PaulePanter: damo22: Document Number: 309219-006 +damo22:PaulePanter: this must be the datasheet: http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/mobile-945-express-chipset-datasheet.pdf + +PaulePanter: Mobile Intel® 945 Express Chipset Family +PaulePanter: damo22: ;-) + +damo22:309219-006 is correct +PaulePanter: Graphics Stolen Memory and TSEG are within DRAM space defined under TOLUD. From +kmalkki:PaulePanter: did you go through the list of patches in your gerrit space that I suggested needed rebase? +PaulePanter: the top of low used DRAM, (G)MCH claims 1 to 64 MBs of DRAM for internal graphics if +PaulePanter: enabled. +PaulePanter: kmalkki: I thought I did go through most of them. +kmalkki:do you have the list +kmalkki:I did not keep copy :/ +kmalkki:5388 +kmalkki:that is AMR +PaulePanter: kmalkki: Don’t waste you time with it. I have a copy of your list somewhere and will go through it in the next days. +kmalkki:PaulePanter: +1 5388 +damo22:PaulePanter: its an integrated GMA 950 afaik +idwer: oh... 5388 has no priority whatsover to me +idwer: not anymore ;) + +damo22:does GM45 support in coreboot have ddr2 AND ddr3 support? + +damo22:well that means X200 could be ported with ME disabled +phcoder-screen:damo22: that's my next fun project after raminit for ivy. +* thomasg_ is now known as thomasg + +damo22:fchmmr: LTN150XG-L08 is my T60 EDID string (for his T60 15" -- this is already noted below in intelvbttool results) + +fchmmr: damo22: ok, i should test 5868? I understand it puts the vgarom inside but without running it (just for getting VBT tables) but latre we could replace it with something like what the X230 "Deploy VBT" does +damo22:yeah +fchmmr: Let me read backlog... +damo22:fchmmr: you dont need backlog, everything you need is in the 5868 commit +fchmmr: how did your X60t unbricking go, damo22? +damo22:havent bothered finding my screwdrivers yet +fchmmr: I need to.... tidy myself up. Back in an hour or so. +fchmmr: damo22: upload a ROM for me, with 5868 and grub payload +fchmmr: I'll test it for you +damo22:im not good with grub payloads +damo22:i can give you one with seabios +fchmmr: ok give me that, +fchmmr: also hm ok, give me your .config. I'll add grub myself +damo22:ok +damo22:fchmmr: http://paste.debian.net/plain/101692 +# +# Automatically generated make config: don't edit +# coreboot version: 4.0-5614-gdb77532 +# Mon May 26 00:11:44 2014 +# + +# +# General setup +# +CONFIG_EXPERT=y +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_SCANBUILD_ENABLE is not set +# CONFIG_CCACHE is not set +# CONFIG_SCONFIG_GENPARSER is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_DYNAMIC_CBMEM is not set +# CONFIG_COLLECT_TIMESTAMPS is not set +# CONFIG_USE_BLOBS is not set +# CONFIG_COVERAGE is not set + +# +# Mainboard +# +# CONFIG_VENDOR_AAEON is not set +# CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_ADVANTECH is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_ARIMA is not set +# CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_ASI is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_A_TREND is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_AXUS is not set +# CONFIG_VENDOR_AZZA is not set +# CONFIG_VENDOR_BACHMANN is not set +# CONFIG_VENDOR_BCOM is not set +# CONFIG_VENDOR_BIFFEROS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BROADCOM is not set +# CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_DIGITALLOGIC is not set +# CONFIG_VENDOR_DMP is not set +# CONFIG_VENDOR_EAGLELION is not set +# CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_IWAVE is not set +# CONFIG_VENDOR_IWILL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LANNER is not set +CONFIG_VENDOR_LENOVO=y +# CONFIG_VENDOR_LINUTOP is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MITAC is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_NEC is not set +# CONFIG_VENDOR_NEWISYS is not set +# CONFIG_VENDOR_NOKIA is not set +# CONFIG_VENDOR_NVIDIA is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_RCA is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SOYO is not set +# CONFIG_VENDOR_SUNW is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TECHNEXION is not set +# CONFIG_VENDOR_TECHNOLOGIC is not set +# CONFIG_VENDOR_TELEVIDEO is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_THOMSON is not set +# CONFIG_VENDOR_TRAVERSE is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +# CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WYSE is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="lenovo/x60" +CONFIG_MAINBOARD_PART_NUMBER="ThinkPad X60 / X60s" +CONFIG_IRQ_SLOT_COUNT=18 +CONFIG_MAINBOARD_VENDOR="Lenovo" +CONFIG_MAX_CPUS=2 +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_RAMBASE=0x100000 +CONFIG_VGA_BIOS_ID="8086,27a2" +CONFIG_DRIVERS_PS2_KEYBOARD=y +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_VGA_BIOS=y +# CONFIG_CONSOLE_POST is not set +# CONFIG_UDELAY_IO is not set +CONFIG_DCACHE_RAM_BASE=0xffdf8000 +CONFIG_DCACHE_RAM_SIZE=0x8000 +CONFIG_SERIAL_CPU_INIT=y +CONFIG_ACPI_SSDTX_NUM=0 +CONFIG_VGA_BIOS_FILE="vgabios.bin" +# CONFIG_PCI_64BIT_PREF_MEM is not set +CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_ID_SECTION_OFFSET=0x80 +# CONFIG_BOARD_EMULATION_QEMU_X86_I440FX is not set +# CONFIG_BOARD_EMULATION_QEMU_X86_Q35 is not set +# CONFIG_BOARD_EMULATION_QEMU_ARMV7 is not set +CONFIG_STACK_SIZE=0x1000 +CONFIG_XIP_ROM_SIZE=0x10000 +CONFIG_MMCONF_SUPPORT_DEFAULT=y +# CONFIG_VGA is not set +CONFIG_BOARD_LENOVO_X60=y +# CONFIG_BOARD_LENOVO_X201 is not set +# CONFIG_BOARD_LENOVO_X230 is not set +# CONFIG_BOARD_LENOVO_T60 is not set +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="LENOVO" +CONFIG_SEABIOS_PS2_TIMEOUT=3000 +CONFIG_MAINBOARD_VERSION="1.0" +CONFIG_CPU_ADDR_BITS=32 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +CONFIG_LOGICAL_CPUS=y +CONFIG_IOAPIC=y +CONFIG_SMP=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +# CONFIG_USBDEBUG is not set +CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_BOARD_ROMSIZE_KB_2048=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +CONFIG_COREBOOT_ROMSIZE_KB_2048=y +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +CONFIG_COREBOOT_ROMSIZE_KB=2048 +CONFIG_ROM_SIZE=0x200000 +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad X60 / X60s" +CONFIG_ARCH_X86=y +# CONFIG_ARCH_ARMV7 is not set + +# +# Architecture (x86) +# +CONFIG_X86_ARCH_OPTIONS=y +CONFIG_AP_IN_SIPI_WAIT=y +# CONFIG_SIPI_VECTOR_IN_ROM is not set +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_NUM_IPI_STARTS=2 +CONFIG_X86_BOOTBLOCK_SIMPLE=y +# CONFIG_X86_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_ROMCC is not set +CONFIG_PC80_SYSTEM=y +CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/i945/bootblock.c" +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801gx/bootblock.c" +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_HAVE_ARCH_MEMSET=y +CONFIG_HAVE_ARCH_MEMCPY=y +CONFIG_HAVE_ARCH_MEMMOVE=y +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set + +# +# Chipset +# + +# +# CPU +# +CONFIG_SOCKET_SPECIFIC_OPTIONS=y +# CONFIG_CPU_AMD_AGESA is not set +CONFIG_HAVE_INIT_TIMER=y +CONFIG_HIGH_SCRATCH_MEMORY_SIZE=0x0 +CONFIG_CPU_INTEL_MODEL_6EX=y +CONFIG_CPU_INTEL_MODEL_6FX=y +CONFIG_SMM_TSEG_SIZE=0 +CONFIG_CPU_INTEL_SOCKET_MFCPGA478=y +CONFIG_SSE2=y +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +CONFIG_UDELAY_LAPIC=y +CONFIG_LAPIC_MONOTONIC_TIMER=y +# CONFIG_UDELAY_TSC is not set +# CONFIG_UDELAY_TIMER2 is not set +# CONFIG_TSC_CALIBRATE_WITH_IO is not set +# CONFIG_TSC_SYNC_LFENCE is not set +CONFIG_TSC_SYNC_MFENCE=y +# CONFIG_SMM_TSEG is not set +# CONFIG_SMM_MODULES is not set +# CONFIG_X86_AMD_FIXED_MTRRS is not set +# CONFIG_PARALLEL_MP is not set +# CONFIG_BACKUP_DEFAULT_SMM_REGION is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_AP_SIPI_VECTOR=0xfffff000 +CONFIG_MMX=y +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +CONFIG_CPU_MICROCODE_ADDED_DURING_BUILD=y +CONFIG_CPU_MICROCODE_CBFS_GENERATE=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# +CONFIG_VIDEO_MB=0 +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_AMD_NB_CIMX is not set +# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set +CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y +CONFIG_NORTHBRIDGE_INTEL_I945=y +# CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC is not set +CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM=y +CONFIG_CHANNEL_XOR_RANDOMIZATION=y +# CONFIG_OVERRIDE_CLOCK_DISABLE is not set +# CONFIG_CHECK_SLFRCS_ON_RESUME is not set +CONFIG_CBFS_SIZE=0x200000 +CONFIG_HPET_MIN_TICKS=0x80 +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +CONFIG_EHCI_BAR=0xfef00000 +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +CONFIG_AMD_SB_SPI_TX_LEN=4 +# CONFIG_SPI_FLASH is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON=y +CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y +CONFIG_SOUTHBRIDGE_RICOH_RL5C476=y + +# +# Super I/O +# +CONFIG_SUPERIO_NSC_PC87382=y +CONFIG_SUPERIO_NSC_PC87392=y + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +CONFIG_EC_LENOVO_H8=y +CONFIG_H8_DOCK_EARLY_INIT=y +CONFIG_EC_LENOVO_PMH7=y + +# +# SoC +# + +# +# Devices +# +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y +# CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG is not set +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_ON_DEVICE_ROM_RUN is not set +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set +CONFIG_PCI=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_AGP_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_ASPM is not set +CONFIG_PCI_BUS_SEGN_BITS=0 + +# +# VGA BIOS +# + +# +# Display +# + +# +# PXE ROM +# +# CONFIG_PXE_ROM is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 + +# +# Generic Drivers +# +# CONFIG_DRIVERS_I2C_RTD2132 is not set +CONFIG_DRIVERS_ICS_954309=y +# CONFIG_INTEL_DP is not set +# CONFIG_INTEL_DDI is not set +CONFIG_INTEL_EDID=y +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVERS_OXFORD_OXPCIE is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_TPM is not set +# CONFIG_RTL8168_ROM_DISABLE is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +CONFIG_HAVE_UART_IO_MAPPED=y +# CONFIG_HAVE_UART_MEMORY_MAPPED is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +CONFIG_MMCONF_SUPPORT=y + +# +# Console +# +CONFIG_EARLY_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y +CONFIG_CONSOLE_SERIAL=y +CONFIG_CONSOLE_SERIAL8250=y +CONFIG_CONSOLE_SERIAL_COM1=y +# CONFIG_CONSOLE_SERIAL_COM2 is not set +# CONFIG_CONSOLE_SERIAL_COM3 is not set +# CONFIG_CONSOLE_SERIAL_COM4 is not set +CONFIG_TTYS0_BASE=0x3f8 +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_BAUD=115200 +CONFIG_TTYS0_LCS=3 +# CONFIG_SPKMODEM is not set +CONFIG_HAVE_USBDEBUG=y +# CONFIG_HAVE_USBDEBUG_OPTIONS is not set +# CONFIG_CONSOLE_NE2K is not set +# CONFIG_CONSOLE_CBMEM is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_NO_POST is not set +# CONFIG_CMOS_POST is not set +CONFIG_IO_POST=y +CONFIG_IO_POST_PORT=0x80 +CONFIG_HAVE_ACPI_RESUME=y +# CONFIG_HAVE_ACPI_SLIC is not set +CONFIG_HAVE_HARD_RESET=y +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_TIMER_QUEUE is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_USE_WATCHDOG_ON_BOOT=y +CONFIG_GFXUMA=y +# CONFIG_RELOCATABLE_MODULES is not set +# CONFIG_HAVE_REFCODE_BLOB is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_HAVE_MP_TABLE=y +CONFIG_HAVE_PIRQ_TABLE=y + +# +# System tables +# +CONFIG_GENERATE_ACPI_TABLES=y +CONFIG_GENERATE_MP_TABLE=y +CONFIG_GENERATE_PIRQ_TABLE=y +CONFIG_GENERATE_SMBIOS_TABLES=y + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +# CONFIG_PAYLOAD_ELF is not set +# CONFIG_PAYLOAD_LINUX is not set +CONFIG_PAYLOAD_SEABIOS=y +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +CONFIG_SEABIOS_STABLE=y +# CONFIG_SEABIOS_MASTER is not set +CONFIG_PAYLOAD_FILE="$(obj)/seabios/out/bios.bin.elf" +CONFIG_COMPRESSED_PAYLOAD_LZMA=y + +# +# Debugging +# +# CONFIG_GDB_STUB is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_CAR is not set +# CONFIG_DEBUG_PIRQ is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_SMM_RELOCATION is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_TRACE is not set +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set + +damo22:you need to still add the vgabios filename +damo22:CONFIG_VGA_BIOS_FILE="vgabios.bin" is the current setting +damo22:# CONFIG_CONSOLE_CBMEM is not set woops + +fchmmr: damo22 » register "gpu_lvds_is_dual_channel" = "1" +fchmmr: on x60/devicetree.cb +damo22:fchmmr: well check your VBT i think its correct though +fchmmr: so 0 was wrong? +damo22:it might depend on panel + +fchmmr: Oh +fchmmr: I get it now. +fchmmr: I didn't see any code in 5868 that executes anything from the vgarom but, +fchmmr: you set coreboot to load it into memory, but not execute it. +fchmmr: I thought "load" only meant put it in cbfs +fchmmr: is this a correct assessment? +fchmmr: To let kernel find vbt tables. +fchmmr: And then we "fake" it later (withotu vga rom loaded). +fchmmr: damo22: are you testing 5868 on your X60t? +damo22:fchmmr: its to make linux kernel detect lvds after native init, but if you can also test coreboot native framebuffer with grub too, that would be handy + +fchmmr: So, vgarom has nothing to do with that patch. +fchmmr: ? +fchmmr: All I see is a change of stolen memory address, and the backlight values added +damo22:fchmmr: its tricky because the final vgabios in memory changes depending on the panel, because vgarom is self modifying + +fchmmr: So should I include the vgarunning.bin instead of vgabios.bin ? +damo22:yes + +damo22:fchmmr: if you can load grub as payload and you see something, its a success +fchmmr: damo22: the problem is, without that patch I just use 5320 as-is, and I see grub as payload already. +fchmmr: Hence my question above. +damo22:fchmmr: also, if you can boot into linux after that and dont get any error messages from drm module, its a double success +fchmmr: Which error messages (besides "Invalid ROM contents") am I looking for? +damo22:fchmmr: stuff like, page fault +fchmmr: And should I enable any specific debugging options (such as drm.debug=0x06) +damo22:yes that would help +fchmmr: Ok: which logs do you want? +fchmmr: I'll upload it for your reference +damo22:fchmmr: kernel boot log and Xorg.0.log, coreboot log if possible +fchmmr: probably kern.log and Xorg.0.log +fchmmr: coreboot log is possible, i have dock. +fchmmr: anything else? +damo22:that is all, thanks +fchmmr: ok. will do. + +fchmmr: damo22: I could test this on T60 aswell by cherry picking 5345, right? +damo22:fchmmr: idk +fchmmr: (and addinf backlight value to deivcetree) +fchmmr: We should devise a way to test this on T60 aswell. +damo22:fchmmr: lets just see if the x60 fix works + +damo22:it still needs work if the test passes +fchmmr: Ok but, you just have that one line changed in gma.c, and backlight value changed it x60/devicetree.cb +damo22:yes +damo22:phcoder did most of the work +fchmmr: So, I could run this same test on T60 by cherry picking 5345 on top of 5868, changing t60/devicetree.cb's backlight value and including T60 runningvga.bin and having that load (but not execute) +damo22:its a small bug i think +fchmmr: I will do that above, after X60 is tested. +damo22:fchmmr: youre always talking about more and more combinations of tests, lets just get one right +fchmmr: Yes. Just a thought. We'll test X60 exclusively. T60 can easily be tested later. +fchmmr: Ok..... back soon. I'll get you the results you wanted. I'll be using 3.14.4 (the one samnob made). +damo22:thanks + +fchmmr: We should do this with the latest runningvga.bin (from extracting with dd on the latest vgabios.bin) +fchmmr: My one is older +damo22:fchmmr: version number of vgabios is irrelevant if it was taken from a lenovo bios that used to run on your machine, and since pulled from ram +damo22:ie, it should have the correct VBT values +damo22:for your machine + + + +
+ Or go back to main document index. +
+ ++ These logs are usually obtained when testing changes related to graphics on i945 (X60 and T60). +
++ TODO: T60: find (for rare buggy CPU's that are unstable without microcode updates) if there is a workaround (patched kernel, special parameter, etc) So far, only 1 processor has been found to have issues. See microcode errata sheets http://download.intel.com/design/mobile/SPECUPDT/31407918.pdf and http://download.intel.com/design/mobile/SPECUPDT/30922214.pdf and then look at the debugging results collected in t7200q directory (q means quirk). +
+ + + ++ Fix X60 Tablet issues (see incompatible panels listed at ../index.html#supported_x60t_list). +
+ ++ Fix T60 issues (see incompatible panels listed at ../index.html#supported_t60_list). +
+ ++ Run that tool (resources/utilities/i945gpu/intel-regs.py) as root on machines with the offending panels in: +
++ This shows values in devicetree.cb and src/northbridge/intel/i945/gma.c, the idea is that you run it on factory bios or vbios + and that it will (might) show different values: then you try those in the native graphics (in libreboot). +
+ ++ Other values/registers might also need to be added to the script for these tests. +
+ ++ Original getregs.py script can be found at http://hg.mtjm.eu/scripts/file/tip/intel-regs.py + written by Michał Masłowski. +
+ + + ++ Older kernels could init GPU on an X60 without a vbios or native graphics. + I have to do a git bisect to find out when that was broken. +
+ ++ Note: "memory_corruption_check=0 i915.lvds_channel_mode=2" kernel parameters were once used + successfully for linux-libre 3.10 on a ThinkPad T60 (distribution: Parabola) to get graphics working. +
+ + + ++ Also check #5320_kernel312fix (to fix 3D on kernel 3.12/higher) +
++ The fix below was done on 5320/6 but should work just fine on later versions of 5320. +
++ Native gpu init + backlight controls! (Fn keys). Also confirmed on X60 Tablet (1024x768) and X60 Tablet (1400x1050) +
++ Checkout http://review.coreboot.org/#/c/5320 on top of a coreboot git clone. +
++ Add backlight controls: in src/mainboard/lenovo/x60/devicetree.cb, change gpu_backlight to 0x879F879E +
+
+ That's all! This has also been backported into libreboot 5th release (line 1233 in src/mainboard/lenovo/x60/i915io.c). GNUtoo (Denis Carikli)
+ told me about the register BLC_PWM_CTL and that you could set it to control backlight. I read that address using devmem2 while running the VBIOS:
+ # devmem2 0xe4361254 w
+
+ When doing this, it gave back that value. The same trick was used to get backlight controls for T60 (see #t60_native_notes). +
+ ++ Reading 0xe4361254 (address) in Lenovo BIOS always yields FFFFFFFF, even when writing to it (and writing to it doesn't affect brightness controls). + 'mtjm' on IRC found that the buttons (Fn keys) control /sys/class/backlight/acpi_video0 which has no affect on 61254 (BLC_PWM_CTL). He says + intel_backlight has different values and uses the register. devmem2 works, needs checking lspci -vv for where the memory is mapped, + which is different than on coreboot; mtjm found that it was 0xec061254 on his machine (X60 Tablet), and the register value is different too. + This is relevant, because we still don't know how backlight controls are actually handled. We got it working by accident. We need to know more.. +
++ Intel-gpu-tools may prove useful for further debugging: http://cgit.freedesktop.org/xorg/app/intel-gpu-tools/ +
++ mtjm says 0xe4300000 is an MMIO region of the gpu (lspci -vv shows it), 0x61254 (BLC_PWM_CTL) is a documented register. Searching the kernel driver for backlight + shows that in intel_panel.c this register is used (there is an XXX comment about finding the right value, where recent kernels get it from. +
++ What we want to do is calculate a good value, instead of setting it in devicetree.cb. mtjm says about backlight physics: + it has a light source , uses pulse width modulation (PWM) to turn it on/off, dimming is done by spending less time on. + Note: this may not be correct; he says his understanding is based on how the Lenote yeeloong works. +
++ mtjm goes on to say, that the register specifies the frequency used for PWM in its depending on the GPU core frequency, so it + might be possible to calculate it without hardcoded laptop-specific values. Therefore, I am supposed to find out the 'display core frequency' + (mtjm says there might be a register for it; also, it might be in 5320 or the replay code) and the PWM modulation frequency. + https://en.wikipedia.org/wiki/Backlight#Flicker_due_to_backlight_dimming +
++ phcoder (Vladimir Serbinenko) who is author of 5320 (review.coreboot.org) talks about 'duty cycle limit' and 'flickering frequency'. +
+ + + ++ Also check #5320_kernel312fix (to fix 3D on kernel 3.12/higher) +
++ The fix below was done on an earlier version of 5345, but should work on the current version. +
++ Native gpu init + backlight controls! (Fn keys). Working on all panels except for 14" XGA (1024x768) and 15" XGA (1024x768)! +
+
+ Checkout http://review.coreboot.org/#/c/5320 + and then cherry-pick http://review.coreboot.org/#/c/5345 on top of a coreboot git clone. +
++ Add backlight controls: in src/mainboard/lenovo/t60/devicetree.cb, change gpu_backlight to 0x58BF58BE +
++ Hold on! Check ../index.html#get_edid_panelname to know what LCD panel you have. This is important for the next step! +
+ ++ ../index.html#supported_t60_list. +
+ ++ Note to self: Run oprom trace for phcoder (T60 w/ 5320+5345 + oprom + grub) for phcoder. This (among other things) + might help to get all panels supported, without modification. +
+ + + +This needs to be rewritten (or better organized, or deleted?). This is also now included in libreboot 6 (using the proper way, not the 7c0000 method which was a hack)
+ ++ This was done on 5320/6 so far. The fix below is for 5320/6 which is now obsolete. This needs to be re-done for the latest version + of 5320. The fix below is (in practise) only for reference, therefore. +
+ ++ See #x60_cb5927_testing for the original (and current) fix, for the replay code. Now we want + to implement that on top of http://review.coreboot.org/#/c/5320 + which is the current code for native graphics initialization on i945. +
+ ++ src/northbridge/intel/i945/gma.c (using the 7c0000 hack) on 5320: 5320_7c0000_gma.c (rename it to gma.c, + replacing the current one). +
+ ++ The above is a hack (as is the original). A better (more correct) method is implemented in later versions of 5927, so + that should also be adapted for 5320. For now, you can use the above fix. +
+ ++ The correct way to do it is to set gtt address to (end of stolen memory - gtt size), which is what later versions of 5927 do (successfully). +
+ ++ Here is some debugging output using intel_gpu_tools v1.2-1 (from trisquel repositories) using tool "intel_gtt": +
+ +The latest version as-is (5927/11) has not been tested by me yet. Always boot with 'drm.debug=0x06' kernel parameter when testing this.
+ ++ This is the fix for 3D on kernel 3.12 and higher on i945 (ThinkPad X60 in this case). This is for the replay code. + Libreboot 5th release has a version of this backported already (based on 5927/3 using the '7c0000' hack). +
+ ++ + The replay code is obsolete (see 5320 changeset on review.coreboot.org for better version + which supports more machines/screens, and then 5345 for T60). Information here for reference since that is where the fix was first applied. + +
+ ++ Read the information on http://review.coreboot.org/#/c/5927/. +
+ ++ For historical purposes, here is a collection of IRC logs that once existed on this page, related to the issue: + kernel312_irc. +
+ +
+ PGETBL_CTL differs between VBIOS (-) and native graphics init (+).
+
+ - PGETBL_CTL: 0x3ffc0001
+ + PGETBL_CTL: 0x3f800001
+
GTT (graphics translation table) size is PGETBL_save, max 256 KiB. BSM (Base of Stolen Memory) is given by the bios.
+ ++ Use 'drm.debug=0x06' kernel parameter when booting in grub! Make sure to use kernel 3.14.4 as before (or any recent kernel). +
++ Before each test run, boot a live USB and delete the old logs in /var/log (kernel log, xorg log, dmesg and so on). +
++ Use latest 5927/5320/5345 on X60/T60 (with GTT/3D/kernel3.12 fix) with native graphics initialization. + Load (from the ROM) the runningvga.bin for each LCD panel on each machine; do not execute it, only load it! + Rename the ROM appropriately, based on the machine name and the panel name. coreboot_nativegfx_5868_plusrunningvga_t60_14_LTD141ECMB.rom, + for instance. Keep a copy for later use. +
+ +It is (theoretically) supposed to:
+You are supposed to:
++ With each boot, make notes about what you see and get logs using the standard test. + You will need the files from #intelvbttool_results for each machine. +
+ + Results (# means untested): ++ The VBIOS on i945 (intel gpu) platforms is self-modifying; that is, + it's contents change when you run it. intelvbttool takes a dump of + the currently running vbios, and parses it. +
+ ++ The idea is that we can extract the VBT tables using this knowledge, on the X60, X60 Tablet and T60 (Intel GPU). +
+ ++ Here is an example of how VBT was implemented on the ThinkPad X230: + http://review.coreboot.org/#/c/5396. +
+ ++ Use this kernel: + http://samnoble.org/thinkpad/kernel/linux-image-3.14.4-gnuowen_2_i386.deb +
+ ++ You'll need to build a T60 ROM with SeaBIOS and the VGA ROM (for Intel GPU). An X60 ROM is also needed (same configuration, using the VGA ROM for X60). +
+ ++ T60 has DVI on it's dock, make sure that the dock is attached when getting this output. +
+ ++ Get intelvbttool here: http://review.coreboot.org/#/c/5842 (util/intelvbttool). +
+ +
+ Now dump a copy of the running VGA BIOS:
+ $ sudo dd if=/dev/mem bs=64k of=runningvga.bin skip=12 count=1
+ Then do (and record the output):
+ $ ./intelvbttool runningvga.bin > intelvbttool_out
+
+ Backup both files (runningvga.bin and intelvbttool_out), renaming them to match the machine and LCD panel used. + ../index.html#get_edid_panelname will show you how to get the name (model) of the LCD panel used. +
+ ++ When idle, the X60 and T60 make a high pitched whining sound. With a recorder, find out where it originates from. + 'processor.max_cstate=2' or 'idle=halt' kernel parameters can be used in GRUB to remove it. + Alternatively (and for better battery life), another method is to use 'powertop' (see docs/index.html in libreboot release + archives). +
+ ++ funfunctor in IRC says: "sounds like the gain is set to high, AGC of a ADC is not setup correctl probably". +
++ damo22 in IRC says: "damo22: it seems like the T60 (happens on X60 aswell) does not + support certain cpu C-states but is being forced to use them and this causes a noise. i believe it's because + it doesnt let the cpu go into low power state.". +
++ CareBear\ in IRC says: "it has to do with the CPU and chipset switching power states differently with coreboot than with the factory BIOS and as a result the power supply circuitry on the mainboard emits that noise. the whine is quite clearly directly related to the CPU switching between power states + " +
+ +
+ Another comment (mailing list):
+ If this noise doesn't occur with
+ the vendor firmware, has anybody checked if coreboot uses the same
+ power management timing settings? (e.g. C4-TIMING_CNT, see [1], there
+ might be more such settings not mentioned in the public datasheet)
+ [1] Intel I/O Controller Hub 7 (ICH7) Family Datasheet Document Number: 307013-003
+
+ +
+ + + ++ Look into this later. This isn't necessarily a bug, just a part of the code which someone noticed that seems odd. +
+
+ funfuctor: fchmmr: what is 'eventc' exactly in the devicetree of your board? Is that meant to be programed sequentially somehow?
+ fchmmr: looks like something with EC
+ fchmmr: src/ec/lenovo/h8/chip.h: u8 eventc_enable;
+ fchmmr: src/ec/lenovo/h8/h8.c: ec_write(0x1c, conf->eventc_enable);
+ funfuctor: fchmmr: yes, better ask phcoder-screen why eventc is defined twice
+ funfuctor: and which value is correct
+ fchmmr: looks like 0x3c is incorrect
+ fchmmr: just a guess
+ fchmmr: in devicetree.cb it goes event2 then 3 4 5 6 7 c 8 9 then a b c d
+ fchmmr: but i don't know what 'event c' is
+ funfuctor: fchmmr: interesting, well in that case you could prob figure it out yourself..
+ funfuctor: fchmmr: the order should not matter. basically devicetree is syntax for fill in a C struct
+ funfuctor: fchmmr: look closely at build/mainboard/lenovo/t60/static.c
+ fchmmr: funfunctor: it was sven schnelle who wrote that (I used 'git blame')
+ fchmmr: I think "eventc" has something to do with battery
+ fchmmr: commit 95ebe66f7f5fef64d363cb48e5a441ad505353d1
+ fchmmr: Author: Sven Schnelle <svens@stackframe.org>
+ fchmmr: Date: Thu Apr 28 09:29:06 2011 +0000
+ fchmmr: that's the commit that added those lines.
+ fchmmr: funfunctor:
+ fchmmr: "" // C: OEM information
+ fchmmr: src/ec/lenovo/h8/acpi/battery.asl
+ funfuctor: fchmmr: i'll leave you with the issue of fixing the devicetree duplicate value
+ funfuctor: fchmmr: you need to read the datasheet to figure out what register 0x3C is
+ funfuctor: sorry *0x1C rather
+ funfuctor: grep eventc src/ec/lenovo/h8/h8.c
+ funfuctor: ec_write(0x1c, conf->eventc_enable);
+ Also look in src/ec/lenovo/h8/h8.c and src/ec/lenovo/h8/chip.h and src/mainboard/lenovo/x60/devicetree.cb
+ Do a 'git blame' and a 'git log path/to/file' etc. ask sven, even.
+
+ funfunctor: shadow compiling means you run both compilers (context: GCC and Clang/LLVM) at the same time. If one compiler misses a problem the other compiler hopefully finds it
+ funfunctor: fchmmr: blow your mind (compiler security and reprodicible builds) - http://scienceblogs.com/goodmath/2007/04/15/strange-loops-dennis-ritchie-a/
+
+ Copyright © 2014 Francis Rowe, All Rights Reserved.
+ See ../license.html for license conditions.
+
+ Most people think of security on the software side: the hardware is important aswell. + Hardware security is useful in particular to journalists (or activists in a given movement) who need absolute privacy in their work. + It is also generally useful to all those that believe security and privacy are inalienable rights. + Security starts with the hardware; crypto and network security come later. +
++ Paradoxically, going this far to increase your security also makes you a bigger target. + At the same time, it protects you in the case that someone does attack your machine. + This paradox only exists while few people take adequate steps to protect yourself: it is your duty + to protect yourself, not only for your benefit but to make strong security normal so + that those who do need protection (and claim it) are a smaller target against the masses. +
++ Even if there are levels of security beyond your ability (technically, financially and so on) + doing at least something (what you are able to do) is extremely important. + If you use the internet and your computer without protection, attacking you is cheap (some say it is + only a few US cents). If everyone (majority of people) use strong security by default, + it makes attacks more costly and time consuming; in effect, making them disappear. +
++ This tutorial deals with reducing the number of devices that have direct memory access that + could communicate with inputs/outputs that could be used to remotely + command the machine (or leak data). +
+
@@ -58,7 +87,7 @@
If your model was WWAN, remove the simcard (check anyway):
Uncover those 2 screws at the bottom:
- SIM card is in the marked location:
+ SIM card (not present in the picture) is in the marked location:
Replacement: USB dongle.
Remove the microphone (can desolder it, but you can also easily pull it off with you hands). Already removed here:
- We do not know what the built-in microcode (on the CPU) is doing. The theory is that it could be programmed to take commands that do something
- and then the CPU returns results. (meaning, remote security hole). So we remove it, just in case.
- Replacement: external microphone on USB or line-in jack.
+ Rationale:
+ Another reason to remove the microphone: If your computer gets[1] compromised, it can
+ record what you say, and use it to receive data from nearby devices if
+ they're compromised too. Also, we do not know what the built-in microcode (in the CPU) is doing; it could theoretically
+ be programmed to accept remote commands from some speaker somewhere (remote security hole). In other words,
+ the machine could already be compromised from the factory.
@@ -114,13 +146,25 @@
Remove the speaker:
Reason: combined with the microphone issue, this could be used to leak data.
+ If your computer gets[1] compromised, it can be used to
+ transmit data to nearby compromised devices. It's unknown if it can be
+ turned into a microphone[2].
Replacement: headphones/speakers (line-out) or external DAC (USB).
Remove the wlan (also remove wwan if you have it):
- Reason: has direct (and very fast) memory access, and could (theoretically) leak data over a side-channel.
+ Reason: has direct (and very fast) memory access, and could (theoretically) leak data over a side-channel.
+ Wifi: The ath5k/ath9k cards might not have firmware at all. They might safe but could have
+ access to the computer's RAM trough DMA. If people have an intel
+ card(most X60's come with Intel wifi by default, until you change it),then that card runs
+ a non-free firwamre and has access to the computer's RAM trough DMA! So
+ it's risk-level is very high.
+ Wwan (3d modem): They run proprietary software and have access to the
+ computer's RAM! So it's like AMT but over the GSM network which is
+ probably even worse.
+ Replacement: external USB wifi dongle. (or USB wwan/3g dongle; note, this has all the same privacy issues as mobile phones. wwan not recommended).
- A lot of this tutorial is based on that video. Look towards the second half of the video to see how to do the abev. + A lot of this tutorial is based on that video. Look towards the second half of the video to see how to do the above.
+ EC: Cannot be removed but can be mitigated: it contains non-free + non-loadable code, but it has no access to the computer's RAM. + It has access to the on-switch of the wifi, bluetooth, modem and some + other power management features. The issue is that it has access to the + keyboard, however if the software security howto (not yet written) is followed correctly, + it won't be able to leak data to a local attacker. It has no network + access but it may still be able to leak data remotely, but that + requires someone to be nearby to recover the data with the help of an + SDR and some directional antennas[3]. +
+ ++ Explain that black hats, TAO, and so on might use a 0day to get in, + and explain that in this case it mitigates what the attacker can do. + Also the TAO do some evaluation before launching an attack: they take + the probability of beeing caught into account, along with the kind of + target. A 0day costs a lot of money, I heard that it was from 100000$ + to 400000$, some other websites had prices 10 times lower but that + but it was probably a typo. So if people increase their security it + makes it more risky and more costly to attack people. +
++ It's possible to turn headphones into a microphone, you could try + yourself, however they don't record loud at all. Also intel cards have + the capability to change a connector's function, for instance the + microphone jack can now become a headphone plug, that's called + retasking. There is some support for it in GNU/Linux but it's not very + well known. +
++ 30c3-5356-en-Firmware_Fat_Camp_webm.webm from the 30th CCC. While + their demo is experimental(their hardware also got damaged during the + transport), the spies probably already have that since a long time. + http://berlin.ftp.media.ccc.de/congress/2013/webm/30c3-5356-en-Firmware_Fat_Camp_webm.webm +
+diff --git a/docs/index.html b/docs/index.html index 37fdd38..43d90d8 100644 --- a/docs/index.html +++ b/docs/index.html @@ -32,6 +32,15 @@ +
+ It is assumed that you are running GNU/Linux. No other operating system is known to be compatible (with libreboot) for this release. +
+ ++ The information here is user documentation mainly. For development notes and TODO's, see RELEASE.html and + future/index.html +
+- This is for Lenovo BIOS users on the ThinkPad X60 and T60. If you have coreboot or libreboot running already, ignore this. + This is for Lenovo BIOS users on the ThinkPad X60/X60S, X60 Tablet and T60. If you have coreboot or libreboot running already, ignore this.
- Bucts is needed when flashing the X60/T60 ROM while Lenovo BIOS is running. + Bucts is needed when flashing the X60/X60S/X60T/T60 ROM while Lenovo BIOS is running. Each ROM contains identical data inside the two final 64K region in the file. This corresponds to the final two 64K regions in the flash chip. Lenovo BIOS will prevent you from writing the final one, so running "bucts 1" will set the machine to boot from the other block instead (which @@ -488,9 +502,71 @@
+ Regarding native gpu initialization ('native graphics') which replaces the proprietary VGA Option ROM ('Video BIOS' or 'VBIOS'), + all known LCD panels are currently compatible: +
++ See #get_edid_panelname. +
+ + + ++ Regarding native gpu initialization ('native graphics') which replaces the proprietary VGA Option ROM ('Video BIOS' or 'VBIOS'). +
+ ++ The following LCD panels are known to work: +
++ The following LCD panels are incompatible at the moment. +
++ See #get_edid_panelname. +
+ ++ Regarding native gpu initialization ('native graphics') which replaces the proprietary VGA Option ROM ('Video BIOS' or 'VBIOS'). +
+ +T60 15.4" (1280x800 and 1680x1050) with Intel GPU is untested in this release. Not much yet is known about panel names. They will be tested at a later date.
@@ -535,30 +611,6 @@ -- A user with 2 T60's, each with a Core 2 Duo T7200 processor tried libreboot on each machine. - One worked, one did not. It should be explained that in addition to the microcode (on the CPU), - updates are usually supplied in coreboot (from Intel) which patch the onboard microcode to fix bugs. - Errata's can be found at http://download.intel.com/design/mobile/SPECUPDT/30922214.pdf - and http://download.intel.com/design/mobile/SPECUPDT/31407918.pdf. - These microcode updates are not included in libreboot because they are proprietary (blobs). Most CPU's work fine without them: hundreds - of Core Duo T2300/T2400/T2500/L2300/L2400/L2500 processors have been tested on the X60, and a few T5600 CPU's have been tested on the T60 (and X60 and all work). - In the case of the T7200, it was found that one of the two tested had instability issues (kernel panics) without the updates: work is being done to find out - exactly what version of the microcode that particular CPU had in this case. - If you find that your CPU gives you similar issues (after trying libreboot), the current workaround is to simply try another CPU - (fortunately, the CPU's in the T60 are installed in a socket so replacing them is easy). -
-- There might be a patched kernel that can be used, or a kernel parameter that can be used in GRUB to work around these (rare) buggy CPU's - (it is unknown at the moment whether this is possible). - The Core 2 Duo T7600 is untested, but will be tested soon (the lead developer of libreboot project has 3 of them to try out). -
-- If reading this for 2nd beta, note that any debugging obtained so far will be included in the 3rd beta. -
-To find what LCD panel you have, see: #get_edid_panelname.
@@ -577,7 +629,7 @@+ How to boot an ISO: burn it to a CD (like you would normally) and hold down the Alt/Control key while booting. + The bootloader will detect the GNU/Linux CD as 'Windows' (because Apple doesn't think GNU/Linux exists). Install it like you normally would. + When you boot up again, hold Alt/Control once more. The installation (on the HDD) will once again be seen as 'Windows'. (it's not actually Windows, + but Apple likes to think that Apple and Microsoft are all that exist.) + Now to install libreboot, follow #flashrom_macbook21. +
+ + The MacBook2,1 comes with a webcam, which does not work without proprietary software. Also, webcams are a security risk; cover it up! Or remove it. + +
++ Hover over the next paragraph to make it black. +
+
+ Following this guide means simply flashing a libreboot ROM. This guide will not (directly) teach you how to make a backup (dump) of the original Apple EFI firmware
+ because to do so would be to explicitly endorse proprietary software. However, for the purposes of reverse engineering it can be useful
+ to have a backup. Each copy of the original Apple EFI is (believed, but unproven to be) tied to the specific machine that it came from; it will not (as is believed) run
+ on any other machine, even if it's the same type of machine as yours. What this means is that, effectively, you can back it up now (so that you can
+ re-flash it later if you want to run the original Apple EFI firmware again) or lose it forever. The macbook21 installation
+ guide on the coreboot wiki will show you how to do this:
+ http://www.coreboot.org/Board:apple/macbook21.
+ Do not make this decision lightly! This is (very likely) your last and only chance.
+
+ (this theory is untested at the time of writing) +
+ +- These instructions work for both the ThinkPad X60 and T60. -
-- This assumes that you already have coreboot or libreboot running -
-- If you have Lenovo BIOS running, go to #flashrom_lenovobios instead. + + This is for the MacBook2,1 while running Apple EFI firmware. If you already have + coreboot or libreboot running, then go to #flashrom instead! +
+- If you are flashing a Lenovo ThinkPad T60, be sure to read #supported_t60_list + Be sure to read the information in #macbook21.
+
If you need to recompile flashrom:
See: #build_flashrom
@@ -1130,31 +1223,108 @@
$ sudo ./builddeb-flashrom
- Look at #rom to see which ROM is suitable for your machine. Alternative you may be using your own + Look at #rom to see which ROM is suitable for your machine. Alternatively you may be using your own custom ROM. Adapt.
+
- Flash the ROM:
- $ sudo ./flash bin/YOURBOARD/YOURROM
+ Flashing is actually easy (compared to X60/T60).
+ $ sudo flashrom -p internal:laptop=force_I_want_a_brick -w bin/YOURBOARD/YOURROM
- You should see "Verifying flash... VERIFIED." written at the end of the flashrom output. SHUT DOWN
- after you see this, and then boot up again after a few seconds.
+ Alternatively, a script is provided which does the same thing:
+ $ sudo ./macbook21_firstflash bin/YOURBOARD/YOURROM
+ You should also see within the output the following:
+ "Verifying flash... VERIFIED."
+
+ If you see that, great! Shut down now (power off). Wait a few seconds and then boot! +
+ +- If you boot and you see nothing, try turning up the backlight (Fn+Home). - If this is a ThinkPad X60 and backlight resets to zero when turning it up while at max, look at #tft_brightness. + These instructions work for the Lenovo ThinkPad X60/X60S/X60T/T60 and Apple MacBook2,1.
-- If this is a ThinkPad X60 then you can look at #x60_wifi for how to enable/disable wifi. - You can also look at #x60_trackpoint for how to enable/disable the trackpoint (red mouse on keyboard). + This assumes that you already have coreboot or libreboot running. + +
++ + If you have Lenovo BIOS running (X60/X60S/X60T/T60), go to #flashrom_lenovobios instead. + +
++ + If you have Apple EFI firmware running (macbook21), go to #flashrom_macbook21 instead. + +
++ + If you are flashing a Lenovo ThinkPad T60, be sure to read #supported_t60_list. + +
++ + If you are flashing an Apple MacBook2,1, be sure to read the information in #macbook21.
+
+ If you need to recompile flashrom:
+ See: #build_flashrom
+
+ You also need the run-time dependencies. This script works on apt-get distros:
+ $ sudo ./builddeb-flashrom
+
+ Look at #rom to see which ROM is suitable for your machine. Alternative you may be using your own + custom ROM. Adapt. +
+
+ Flash the ROM:
+ $ sudo ./flash bin/YOURBOARD/YOURROM
+
+ You should see "Verifying flash... VERIFIED." written at the end of the flashrom output. SHUT DOWN + after you see this, and then boot up again after a few seconds. +
+ ++ + If you boot and you see nothing, try turning up the backlight (Fn+Home). + If this is a ThinkPad X60 and backlight resets to zero when turning it up while at max, look at #tft_brightness. + +
+ ++ + If this is a ThinkPad X60 then you can look at #x60_wifi for how to enable/disable wifi. + You can also look at #x60_trackpoint for how to enable/disable the trackpoint (red mouse on keyboard). + +
+ +https://upload.wikimedia.org/wikipedia/commons/thumb/b/b9/KB_France.svg/800px-KB_France.svg.png
+$ cd libreboot_src/grub
- compile grub ('build' script has the info on how to do this)
- come back out into libreboot_src
- $ cd ../
Generate the layout file:
$ ckbcomp us > usqwerty
$ cat usqwerty | ./grub/grub-mklayout -o usqwerty.gkb
Note: these files are already included ('build' script also makes use of them). You don't need to do any of this.
-$ ckbcomp gb > ukqwerty
+
Generate the layout file:
+ $ ckbcomp gb > ukqwerty
$ cat ukqwerty | ./grub/grub-mklayout -o ukqwerty.gkb
Note: these files are already included ('build' script makes use of them). You don't need to do it.
-How the dvorak.gkb was made (for US Dvorak layout in GRUB).
- -$ cd libreboot_src/grub
- compile grub ('build' script has the info on how to do this)
- come back out into libreboot_src:
- $ cd ../
Generate the layout file:
$ ckbcomp dvorak > usdvorak
- $ cat usdvorak | ./grub/grub-mklayout -o dvorak.gkb
Note: these files are already included ('build' script makes use of them). You don't need to do it.
+ $ cat usdvorak | ./grub/grub-mklayout -o usdvorak.gkbThere isn't much difference to US Dvorak.
- $ cp usdvorak ukdvorak
Patch ukdvorak like so (diff usdvorak ukdvorak):
- diff the usdvorak file with ukdvorak to see how it was patched.
+ ukdvorak had to be created manually, based on usdvorak. diff them (under resources/grub/keymap/original) + to see how ukdvorak file was created +
-Now create ukdvorak.gkb
$ cat ukdvorak | ./grub/grub-mklayout -o ukdvorak.gkb
Note: these files are already included ('build' script makes use of them). You don't need to do any of this.
- -How the frazerty.gkb was made (for FR AZERTY layout in GRUB).
- -$ cd libreboot_src/grub
- compile grub ('build' script has the info on how to do this)
- come back out into libreboot_src:
- $ cd ../
Generate the layout file:
$ ckbcomp fr > frazerty
$ cat frazerty | ./grub/grub-mklayout -o frazerty.gkb
Note: these files are already included ('build' script makes use of them). You don't need to do it.
+Generate the layout file:
+ $ ckbcomp it > itqwerty
+ $ cat itqwerty | ./grub/grub-mklayout -o itqwerty.gkb
Unlisted note: http://inertiawar.com/microcode/ + Read that thread: http://www.coreboot.org/pipermail/coreboot/2014-July/078261.html (link published to coreboot mailing list on July 8, 2014) + Document everything listed in this discussion (and the link) + + SeaVGABIOS+SeaBIOS support for X60/T60: + Read that: http://www.coreboot.org/pipermail/coreboot/2014-July/078342.html This page talks about 'calibration' in powertop: https://docs.fedoraproject.org/en-US/Fedora/15/html/Power_Management_Guide/PowerTOP.html I should think about adapting information here based on that page. + + Look into 'git archive' instead of deleting .git + eg (coreboot directory): + git archive --format=tar --prefix=libreboot/ -o ../libreboot_release.tar HEAD