From 756ee1f9eb4583b127b2233666643d16ad7fd8d2 Mon Sep 17 00:00:00 2001 From: Francis Rowe Date: Sat, 27 Feb 2016 06:23:12 -0500 Subject: use only 1 crossgcc revision in libreboot --- diff --git a/.gitignore b/.gitignore index 03ff08d..d2c17b3 100644 --- a/.gitignore +++ b/.gitignore @@ -5,6 +5,7 @@ /docs/version /bucts/ /coreboot/ +/crossgcc/ /depthcharge/ /flashrom/ /grub/ diff --git a/resources/scripts/helpers/build/clean/coreboot b/resources/scripts/helpers/build/clean/coreboot index 2f7701e..baaabbd 100755 --- a/resources/scripts/helpers/build/clean/coreboot +++ b/resources/scripts/helpers/build/clean/coreboot @@ -31,7 +31,8 @@ printf "Cleaning the previous build of coreboot and its utilities\n" # clean coreboot and crossgcc (source archives preserved) for payload in coreboot/*; do for board in "${payload}/"*; do - # Clean coreboot, of course + + # Clean coreboot, of course make -C "${board}/" distclean # Clean its utilities as well @@ -40,16 +41,15 @@ for payload in coreboot/*; do done make -C "${board}/payloads/libpayload/" distclean - # Clean crossgcc - if [ "${payload##*/}" != "crossgcc" ]; then # is a symlink - # delete symlink to crossgcc - rm -f "${board}/util/crossgcc" - else # is the real crossgcc - # payload is crossgcc - # board is not a board, it's a coreboot revision - make -C "${board}/" crossgcc-clean - fi + rm -f "${board}/util/crossgcc" done done +# Also do the same for the crossgcc version of coreboot +make -C "crossgcc/" crossgcc-clean +for util in {cbfs,ifd,nvram}tool cbmem; do + make -C "crossgcc/util/${util}/" clean +done +make -C "crosgcc/" distclean + printf "\n\n" diff --git a/resources/scripts/helpers/build/module/coreboot b/resources/scripts/helpers/build/module/coreboot index 07659cd..d3e86cd 100755 --- a/resources/scripts/helpers/build/module/coreboot +++ b/resources/scripts/helpers/build/module/coreboot @@ -34,24 +34,24 @@ printf "Building the utilities in coreboot\n" for payload in coreboot/*; do for board in "${payload}/"*; do - if [ "${payload##*/}" = "crossgcc" ]; then # build crossgcc - - for architecture in i386 arm; do - make -j$(nproc) -BC "${board}/" crossgcc-${architecture} - done - else # build other utils - # cbfstool, cbmem, nvramtool - for util in {cbfs,nvram}tool cbmem; do - make -BC "${board}/util/${util}" - done - # create symlink to crossgcc - ( - boardconfig_path="resources/libreboot/config/${payload##*/}/${board##*/}" - cbrevision="$(cat "${boardconfig_path}/cbrevision")" - cd "${board}/util/" - ln -s "../../../crossgcc/${cbrevision}/util/crossgcc/" crossgcc - ) - fi + # cbfstool, cbmem, nvramtool + for util in {cbfs,nvram}tool cbmem; do + make -BC "${board}/util/${util}" + done + # create symlink to crossgcc + ( + boardconfig_path="resources/libreboot/config/${payload##*/}/${board##*/}" + cbrevision="$(cat "${boardconfig_path}/cbrevision")" + cd "${board}/util/" + ln -s "../../../../crossgcc/util/crossgcc/" crossgcc + ) done done + +# Now build crossgcc +( +cd "crossgcc/" +make crossgcc-i386 +make crossgcc-arm +) diff --git a/resources/scripts/helpers/download/coreboot b/resources/scripts/helpers/download/coreboot index c8b853d..16bd1a8 100755 --- a/resources/scripts/helpers/download/coreboot +++ b/resources/scripts/helpers/download/coreboot @@ -33,6 +33,9 @@ else version="libreboot-$(git describe --tags HEAD)" fi +# coreboot revisios used for crossgcc +crossgccrevision="4351ace145c4069f9c93ca7541d6dfaf8300b53b" + # sanity check (check for invalid paths in the reused.list patch lists before proceeding) for payloads in resources/libreboot/config/*; do @@ -137,11 +140,6 @@ git clone https://review.coreboot.org/coreboot # there are modifications required cd "coreboot/" -# Reset to a common revision# -# other revisions used will be on this one, or before it -# This common revision is used for the crossgcc compilation -git reset --hard 4351ace145c4069f9c93ca7541d6dfaf8300b53b - # Define a common version (based on the libreboot version) # Most likely redundant, because the build system needs to update # this every time when building a ROM image anyway @@ -204,38 +202,20 @@ for payloads in ../../resources/libreboot/config/*; do done done -# prepare directories for crossgcc -for payloads in ../../resources/libreboot/config/*; do - - if [ ! -d "${payloads}/" ]; then - continue - fi - - payload="${payloads##*/}" - - for boardconfig in ../../resources/libreboot/config/${payload}/*; do - - if [ ! -d "${boardconfig}/" ]; then - continue - fi - - boardname="${boardconfig##*/}" - cbrevision=$(cat "${boardconfig}/cbrevision") - vbootrevision=$(cat "${boardconfig}/vbootrevision") - - # Create coreboot directory for compiling crossgcc - if [ ! -d "../crossgcc/${cbrevision}" ]; then - make_coreboot_src_directory crossgcc ${cbrevision} .. - ( - cd "../crossgcc/${cbrevision}/" - # reset to known revision (coreboot) - reset_at_revision ${cbrevision} - # no way to know which vboot revision is used here, so delete 3rdparty - rm -Rf "3rdparty/" - ) - fi - done -done +# prepare directory for crossgcc +rm -Rf "../../crossgcc/" +make_coreboot_src_directory crossgcc ${crossgccrevision} .. +( + cd "../crossgcc/${crossgccrevision}" + reset_at_revision ${crossgccrevision} + rm -Rf "3rdparty/" + + # Put this in its own separate directory + rm -Rf "../../../crossgcc" + cd ../ + mv "${crossgccrevision}/" "crossgcc/" + mv "crossgcc/" ../../ +) # go back to _src/coreboot/ (containing all coreboot directories) cd "../" @@ -246,7 +226,7 @@ rm -Rf "coreboot/" # ------------------------------------------------------------------------------ printf "Deleting .git* in coreboot/ (history inside .git contains the blobs that were deleted)\n" -rm -Rf */*/.git* +rm -Rf */*/.git* ../crossgcc/*.git rm -Rf */*/3rdparty/*/.git* # Delete crossgcc from non-crossgcc coreboot archives diff --git a/resources/utilities/coreboot-libre/blobs/coreboot/crossgcc/blobs.list b/resources/utilities/coreboot-libre/blobs/coreboot/crossgcc/blobs.list new file mode 100644 index 0000000..a8a9a96 --- /dev/null +++ b/resources/utilities/coreboot-libre/blobs/coreboot/crossgcc/blobs.list @@ -0,0 +1,52 @@ +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c7.c +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c6.c +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c8.c +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000d9.c +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c5.c +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevE/F10MicrocodePatch010000bf.c +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMicrocodePatch06000624_Enc.c +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMicrocodePatch0600050D_Enc.c +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMicrocodePatch06000425.c +src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600110F_Enc.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c7.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c6.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c8.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c4.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c5.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/F10MicrocodePatch010000bf.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500000B.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500001A.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c6.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c8.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c4.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c5.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevE/F10MicrocodePatch010000bf.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12MicrocodePatch03000002.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12MicrocodePatch0300000f.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12MicrocodePatch0300000e.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c7.c +src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c +src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000b6.c +src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000098.c +src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000086.c +src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c4.c +src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c5.c +src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbId7001MicrocodePatch.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000029.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000119.c +src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbSmuFirmware.h +src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbSmuFirmware.h +src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSmuFirmwareKB.h +src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbSmuFirmwareTN.h +src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/excel925.h +src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSamuPatchKB.h +src/vendorcode/amd/cimx/rd890/HotplugFirmware.h +src/cpu/dmp/vortex86ex/dmp_kbd_fw_part1.inc +src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlibSsdt.h +src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlibSsdt.h +src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/AlibSsdtKB.h +src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFM2.h +src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFS1.h diff --git a/resources/utilities/coreboot-libre/blobs/coreboot/crossgcc/nonblobs.list b/resources/utilities/coreboot-libre/blobs/coreboot/crossgcc/nonblobs.list new file mode 100644 index 0000000..6f67215 --- /dev/null +++ b/resources/utilities/coreboot-libre/blobs/coreboot/crossgcc/nonblobs.list @@ -0,0 +1,335 @@ +payloads/libpayload/curses/PDCurses-3.4/demos/worm.c +payloads/libpayload/curses/PDCurses-3.4/sdl1/deffont.h +payloads/libpayload/curses/PDCurses-3.4/sdl1/deficon.h +payloads/libpayload/curses/PDCurses-3.4/win32/pdckbd.c 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+src/mainboard/google/cyan/spd/hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.hex +src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex +src/mainboard/google/cyan/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex +src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNBLTALAR.spd.hex +src/mainboard/google/glados/spd/empty.spd.hex +src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8JTBLAR.spd.hex +src/mainboard/intel/sklrvp/spd/empty.spd.hex +src/mainboard/intel/sklrvp/spd/rvp3.spd.hex +src/mainboard/intel/kunimitsu/spd/empty.spd.hex +src/mainboard/intel/kunimitsu/spd/samsung_dimm_K4E8E304EE-EGCE.spd.hex +src/mainboard/intel/strago/spd/hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.hex +src/mainboard/intel/strago/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex +src/mainboard/intel/strago/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex +src/mainboard/intel/kunimitsu/spd/hynix_dimm_H9CCNNNBLTALAR-NUD-2G-1866.spd.hex +src/mainboard/intel/kunimitsu/spd/samsung_dimm_K4E8E304EE-EGCF-1G-1866.spd.hex +src/mainboard/intel/kunimitsu/spd/samsung_dimm_K4E6E304EE-EGCF-2G-1866.spd.hex +src/mainboard/intel/kunimitsu/spd/hynix_dimm_H9CCNNN8JTALAR-NUD-1G-1866.spd.hex +src/mainboard/bap/ode_e20XX/BAP_Q7.spd.hex +src/northbridge/intel/nehalem/raminit_tables.c +src/northbridge/intel/sandybridge/raminit_patterns.h +src/southbridge/nvidia/mcp55/early_setup_ss.h +src/southbridge/nvidia/ck804/early_setup_ss.h +src/southbridge/sis/sis966/early_setup_ss.h +util/crossgcc/patches/binutils-2.25_riscv.patch +src/southbridge/amd/pi/hudson/Kconfig +src/drivers/xgi/common/vb_setmode.c +src/drivers/xgi/common/vb_table.h +src/drivers/xgi/common/XGI_main.h +src/mainboard/siemens/mc_tcu3/romstage.c +src/mainboard/siemens/mc_tcu3/lcd_panel.c +src/mainboard/siemens/mc_tcu3/modhwinfo.c +src/mainboard/pcengines/apu1/Kconfig +src/mainboard/asus/kfsn4-dre/get_bus_conf.c +src/mainboard/google/samus/spd/spd.c +src/mainboard/hp/abm/mptable.c +src/northbridge/amd/pi/00630F01/Kconfig +src/cpu/amd/microcode/microcode.c +src/lib/tlcl_structures.h +util/rockchip/make_idb.py +util/autoport/readme.md +util/bimgtool/bimgtool.c +util/cbfstool/fmd_parser.c_shipped +util/cbfstool/fmd_scanner.c_shipped +Documentation/CorebootBuildingGuide.tex +Documentation/hypertransport.svg +Documentation/codeflow.svg +src/soc/broadcom/cygnus/ddr_init.c +src/soc/broadcom/cygnus/ddr_init_table.c +src/soc/qualcomm/ipq806x/lcc.c +src/soc/intel/braswell/acpi.c +src/soc/intel/braswell/Kconfig +src/vendorcode/amd/pi/Kconfig +src/drivers/intel/fsp1_1/Kconfig +src/drivers/intel/fsp1_1/fsp_gop.c +src/drivers/i2c/ww_ring/ww_ring_programs.c +src/mainboard/google/auron/spd/spd.c +src/mainboard/google/jecht/lan.c +src/mainboard/gigabyte/ga-b75m-d3v/romstage.c +src/mainboard/amd/lamar/Kconfig +payloads/external/GRUB2/Kconfig +payloads/external/FILO/Kconfig +payloads/external/SeaBIOS/Kconfig +src/soc/intel/common/fsp_ramstage.c +src/soc/intel/skylake/Kconfig +src/soc/intel/braswell/gpio.c +src/soc/nvidia/tegra210/Kconfig +src/soc/nvidia/tegra210/mtc.c +src/southbridge/intel/common/firmware/Kconfig +src/mainboard/google/cyan/spd/spd.c +src/mainboard/google/cyan/Kconfig +src/mainboard/google/glados/spd/spd.c +src/mainboard/intel/sklrvp/spd/spd.c +src/mainboard/intel/kunimitsu/spd/spd.c +src/mainboard/intel/strago/spd/spd.c +src/mainboard/intel/strago/Kconfig +src/mainboard/amd/bettong/mptable.c +src/northbridge/amd/pi/00660F01/Kconfig +util/crossgcc/patches/gcc-5.2.0_riscv.patch +util/xcompile/xcompile +src/northbridge/intel/sandybridge/raminit_mrc.c +src/northbridge/intel/fsp_rangeley/fsp/Kconfig +src/drivers/intel/fsp1_1/car.c +src/mainboard/intel/mohonpeak/Kconfig +src/mainboard/apple/macbookair4_2/early_southbridge.c +src/cpu/intel/fsp_model_406dx/acpi.c +src/northbridge/intel/fsp_sandybridge/fsp/Kconfig +src/drivers/aspeed/common/ast_dram_tables.h +src/drivers/aspeed/common/ast_tables.h +src/mainboard/intel/cougar_canyon2/Kconfig +src/cpu/amd/family_10h-family_15h/processor_name.c +src/cpu/amd/family_10h-family_15h/init_cpus.c +src/cpu/intel/fsp_model_206ax/acpi.c diff --git a/resources/utilities/coreboot-libre/blobs/coreboot/crossgcc/nonblobs_notes b/resources/utilities/coreboot-libre/blobs/coreboot/crossgcc/nonblobs_notes new file mode 100644 index 0000000..551da4a --- /dev/null +++ b/resources/utilities/coreboot-libre/blobs/coreboot/crossgcc/nonblobs_notes @@ -0,0 +1,15 @@ +.spd.hex files - serial presence detect. These are not blobs +see JEDEC standard or https://en.wikipedia.org/wiki/Serial_presence_detect +These are added to the nonblobs file + +src/northbridge/intel/nehalem/raminit_tables.c" +src/northbridge/intel/sandybridge/raminit_patterns.h +These are used by native raminit for the relevant platforms, and are not blobs + +"src/southbridge/nvidia/mcp55/early_setup_ss.h" \ +"src/southbridge/nvidia/ck804/early_setup_ss.h" \ +"src/southbridge/sis/sis966/early_setup_ss.h" +not blobs + +The text in this file is CC-BY-SA 4.0 or higher. All contributions to it must +be made under the same license. diff --git a/resources/utilities/coreboot-libre/deblob b/resources/utilities/coreboot-libre/deblob index 61b3e4b..cd9b463 100755 --- a/resources/utilities/coreboot-libre/deblob +++ b/resources/utilities/coreboot-libre/deblob @@ -70,5 +70,10 @@ for payloads in "coreboot/"*; do done done +# Now also do the same for crossgcc coreboot +for blob in $(cat "resources/utilities/coreboot-libre/blobs/coreboot/crossgcc/blobs.list"); do + rm -f "crossgcc/${blob}" +done + printf "\n\n" -- cgit v0.9.1