From 60453ff2cbd1befe24959fba1d24f734406444e3 Mon Sep 17 00:00:00 2001 From: Francis Rowe Date: Fri, 06 Nov 2015 02:45:49 -0500 Subject: Update coreboot to new version (use latest stable kgpe-d16 tree) --- diff --git a/resources/libreboot/patch/kgpe-d16/0002-southbridge-amd-sb700-Allow-use-of-auxiliary-SMBUS-c.patch b/resources/libreboot/patch/kgpe-d16/0002-southbridge-amd-sb700-Allow-use-of-auxiliary-SMBUS-c.patch index 651c973..b5f03eb 100644 --- a/resources/libreboot/patch/kgpe-d16/0002-southbridge-amd-sb700-Allow-use-of-auxiliary-SMBUS-c.patch +++ b/resources/libreboot/patch/kgpe-d16/0002-southbridge-amd-sb700-Allow-use-of-auxiliary-SMBUS-c.patch @@ -1,28 +1,29 @@ -From 6ae8695f880a4a15672eda801226b4b1c83aa1a8 Mon Sep 17 00:00:00 2001 +From c3691fe7c155d63baedbb1836e6ccf9c1fcb5846 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sat, 17 Oct 2015 04:36:47 -0500 -Subject: [PATCH 002/139] southbridge/amd/sb700: Allow use of auxiliary SMBUS +Subject: [PATCH 002/143] southbridge/amd/sb700: Allow use of auxiliary SMBUS controller Change-Id: I29ece10eeefc2c75a3829c169f1e1aede7194ec2 Signed-off-by: Timothy Pearson --- - src/device/Kconfig | 4 ++++ - src/include/device/smbus.h | 5 +++++ - src/southbridge/amd/sb700/Kconfig | 1 + - src/southbridge/amd/sb700/sm.c | 36 +++++++++++++++++++++++++++++++----- - src/southbridge/amd/sb700/smbus.c | 15 +++++++++++++++ - 5 files changed, 56 insertions(+), 5 deletions(-) + src/device/Kconfig | 4 ++++ + src/include/device/smbus.h | 5 ++++ + src/southbridge/amd/sb700/Kconfig | 1 + + src/southbridge/amd/sb700/sm.c | 47 ++++++++++++++++++++++++++++++------- + src/southbridge/amd/sb700/smbus.c | 15 ++++++++++++ + src/southbridge/amd/sb700/smbus.h | 5 ++-- + 6 files changed, 66 insertions(+), 11 deletions(-) diff --git a/src/device/Kconfig b/src/device/Kconfig -index 613461b..3dd2b61 100644 +index 613461b..bcf7dad 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -192,6 +192,10 @@ config MULTIPLE_VGA_ADAPTERS bool default n -+config SMBUS_HAS_AUX ++config SMBUS_HAS_AUX_CHANNELS + bool + default n + @@ -30,129 +31,133 @@ index 613461b..3dd2b61 100644 bool default n diff --git a/src/include/device/smbus.h b/src/include/device/smbus.h -index 073d7e2..53e90fb 100644 +index 073d7e2..a838f55 100644 --- a/src/include/device/smbus.h +++ b/src/include/device/smbus.h @@ -47,4 +47,9 @@ int smbus_process_call(device_t dev, u8 cmd, u16 data); int smbus_block_read(device_t dev, u8 cmd, u8 bytes, u8 *buffer); int smbus_block_write(device_t dev, u8 cmd, u8 bytes, const u8 *buffer); -+#if IS_ENABLED(CONFIG_SMBUS_HAS_AUX) -+void smbus_switch_to_aux(uint8_t enable_aux); -+uint8_t smbus_switched_to_aux(void); ++#if IS_ENABLED(CONFIG_SMBUS_HAS_AUX_CHANNELS) ++void smbus_switch_to_aux_channel(uint8_t aux_channel_number); ++uint8_t smbus_current_aux_channel(void); +#endif + #endif /* DEVICE_SMBUS_H */ diff --git a/src/southbridge/amd/sb700/Kconfig b/src/southbridge/amd/sb700/Kconfig -index 42ca2bb..a5dfe07 100644 +index 42ca2bb..0761934 100644 --- a/src/southbridge/amd/sb700/Kconfig +++ b/src/southbridge/amd/sb700/Kconfig @@ -27,6 +27,7 @@ config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy select IOAPIC select HAVE_USBDEBUG_OPTIONS select HAVE_HARD_RESET -+ select SMBUS_HAS_AUX ++ select SMBUS_HAS_AUX_CHANNELS # Set for southbridge SP5100 which also uses SB700 driver config SOUTHBRIDGE_AMD_SUBTYPE_SP5100 diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c -index f544c88..c216e1f 100644 +index f544c88..598ebec 100644 --- a/src/southbridge/amd/sb700/sm.c +++ b/src/southbridge/amd/sb700/sm.c -@@ -40,6 +40,8 @@ +@@ -40,6 +40,11 @@ #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif ++#define PRIMARY_SMBUS_RESOURCE_NUMBER 0x90 ++#define AUXILIARY_SMBUS_RESOURCE_NUMBER 0x58 ++ +uint8_t smbus_use_aux = 0; + /* * SB700 enables all USB controllers by default in SMBUS Control. * SB700 enables SATA by default in SMBUS Control. -@@ -312,7 +314,10 @@ static int lsmbus_recv_byte(device_t dev) +@@ -312,7 +317,10 @@ static int lsmbus_recv_byte(device_t dev) device = dev->path.i2c.device; pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, 0x90); + if (!smbus_use_aux) -+ res = find_resource(pbus->dev, 0x90); ++ res = find_resource(pbus->dev, PRIMARY_SMBUS_RESOURCE_NUMBER); + else -+ res = find_resource(pbus->dev, 0x58); ++ res = find_resource(pbus->dev, AUXILIARY_SMBUS_RESOURCE_NUMBER); return do_smbus_recv_byte(res->base, device); } -@@ -326,7 +331,10 @@ static int lsmbus_send_byte(device_t dev, u8 val) +@@ -326,7 +334,10 @@ static int lsmbus_send_byte(device_t dev, u8 val) device = dev->path.i2c.device; pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, 0x90); + if (!smbus_use_aux) -+ res = find_resource(pbus->dev, 0x90); ++ res = find_resource(pbus->dev, PRIMARY_SMBUS_RESOURCE_NUMBER); + else -+ res = find_resource(pbus->dev, 0x58); ++ res = find_resource(pbus->dev, AUXILIARY_SMBUS_RESOURCE_NUMBER); return do_smbus_send_byte(res->base, device, val); } -@@ -340,7 +348,10 @@ static int lsmbus_read_byte(device_t dev, u8 address) +@@ -340,7 +351,10 @@ static int lsmbus_read_byte(device_t dev, u8 address) device = dev->path.i2c.device; pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, 0x90); + if (!smbus_use_aux) -+ res = find_resource(pbus->dev, 0x90); ++ res = find_resource(pbus->dev, PRIMARY_SMBUS_RESOURCE_NUMBER); + else -+ res = find_resource(pbus->dev, 0x58); ++ res = find_resource(pbus->dev, AUXILIARY_SMBUS_RESOURCE_NUMBER); return do_smbus_read_byte(res->base, device, address); } -@@ -354,7 +365,10 @@ static int lsmbus_write_byte(device_t dev, u8 address, u8 val) +@@ -354,7 +368,10 @@ static int lsmbus_write_byte(device_t dev, u8 address, u8 val) device = dev->path.i2c.device; pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, 0x90); + if (!smbus_use_aux) -+ res = find_resource(pbus->dev, 0x90); ++ res = find_resource(pbus->dev, PRIMARY_SMBUS_RESOURCE_NUMBER); + else -+ res = find_resource(pbus->dev, 0x58); ++ res = find_resource(pbus->dev, AUXILIARY_SMBUS_RESOURCE_NUMBER); return do_smbus_write_byte(res->base, device, address, val); } -@@ -393,7 +407,7 @@ static void sb700_sm_read_resources(device_t dev) +@@ -393,9 +410,18 @@ static void sb700_sm_read_resources(device_t dev) /* dev->command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; */ - /* smbus */ +- res = new_resource(dev, 0x90); +- res->base = 0xB00; + /* primary smbus */ - res = new_resource(dev, 0x90); - res->base = 0xB00; - res->size = 0x10; -@@ -402,6 +416,15 @@ static void sb700_sm_read_resources(device_t dev) - res->gran = 8; - res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | IORESOURCE_ASSIGNED; - -+ /* auxiliary smbus */ -+ res = new_resource(dev, 0x58); -+ res->base = 0xB20; ++ res = new_resource(dev, PRIMARY_SMBUS_RESOURCE_NUMBER); ++ res->base = SMBUS_IO_BASE; + res->size = 0x10; + res->limit = 0xFFFFUL; /* res->base + res->size -1; */ + res->align = 8; + res->gran = 8; + res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | IORESOURCE_ASSIGNED; + - compact_resources(dev); - } - -@@ -441,6 +464,9 @@ static void sb700_sm_set_resources(struct device *dev) - - res = find_resource(dev, 0x90); - pci_write_config32(dev, 0x90, res->base | 1); ++ /* auxiliary smbus */ ++ res = new_resource(dev, AUXILIARY_SMBUS_RESOURCE_NUMBER); ++ res->base = SMBUS_AUX_IO_BASE; + res->size = 0x10; + res->limit = 0xFFFFUL; /* res->base + res->size -1; */ + res->align = 8; +@@ -439,8 +465,11 @@ static void sb700_sm_set_resources(struct device *dev) + pci_write_config8(dev, 0x65, byte); + /* TODO: End of test hpet */ + +- res = find_resource(dev, 0x90); +- pci_write_config32(dev, 0x90, res->base | 1); ++ res = find_resource(dev, PRIMARY_SMBUS_RESOURCE_NUMBER); ++ pci_write_config32(dev, PRIMARY_SMBUS_RESOURCE_NUMBER, res->base | 1); + -+ res = find_resource(dev, 0x58); -+ pci_write_config32(dev, 0x58, res->base | 1); ++ res = find_resource(dev, AUXILIARY_SMBUS_RESOURCE_NUMBER); ++ pci_write_config32(dev, AUXILIARY_SMBUS_RESOURCE_NUMBER, res->base | 1); } static struct pci_operations lops_pci = { diff --git a/src/southbridge/amd/sb700/smbus.c b/src/southbridge/amd/sb700/smbus.c -index 94f5e24..a89e830 100644 +index 94f5e24..e1cfe6b 100644 --- a/src/southbridge/amd/sb700/smbus.c +++ b/src/southbridge/amd/sb700/smbus.c @@ -22,6 +22,11 @@ @@ -161,8 +166,8 @@ index 94f5e24..a89e830 100644 +extern uint8_t smbus_use_aux; + -+void smbus_switch_to_aux(uint8_t enable_aux); -+uint8_t smbus_switched_to_aux(void); ++void smbus_switch_to_aux_channel(uint8_t aux_channel_number); ++uint8_t smbus_current_aux_channel(void); + void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val) { @@ -171,17 +176,40 @@ index 94f5e24..a89e830 100644 return 0; } -+void smbus_switch_to_aux(uint8_t enable_aux) ++void smbus_switch_to_aux_channel(uint8_t aux_channel_number) +{ -+ smbus_use_aux = enable_aux; ++ smbus_use_aux = (aux_channel_number != 0); +} + -+uint8_t smbus_switched_to_aux(void) ++uint8_t smbus_current_aux_channel(void) +{ + return smbus_use_aux; +} + #endif +diff --git a/src/southbridge/amd/sb700/smbus.h b/src/southbridge/amd/sb700/smbus.h +index d223fe7..34b4098 100644 +--- a/src/southbridge/amd/sb700/smbus.h ++++ b/src/southbridge/amd/sb700/smbus.h +@@ -2,6 +2,7 @@ + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. ++ * Copyright (C) 2015 Timothy Pearson , Raptor Engineering + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by +@@ -24,8 +25,8 @@ + #include "stddef.h" + #include + +-#define SMBUS_IO_BASE 0x6000 /* Is it a temporary SMBus I/O base address? */ +- /*SIZE 0x40 */ ++#define SMBUS_IO_BASE 0xb00 ++#define SMBUS_AUX_IO_BASE 0xb20 + + #define SMBHSTSTAT 0x0 + #define SMBSLVSTAT 0x1 -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0001-drivers-i2c-w83795-Add-full-support-for-fan-control-.patch b/resources/libreboot/patch/kgpe-d16/0003-drivers-i2c-w83795-Add-full-support-for-core-functio.patch index 0dc1606..0cbdaf6 100644 --- a/resources/libreboot/patch/kgpe-d16/0001-drivers-i2c-w83795-Add-full-support-for-fan-control-.patch +++ b/resources/libreboot/patch/kgpe-d16/0003-drivers-i2c-w83795-Add-full-support-for-core-functio.patch @@ -1,28 +1,37 @@ -From f7b8be27ea159845a982c310799a5896865016cd Mon Sep 17 00:00:00 2001 +From 72d183bad6db0f2f91b991710d1c0a8113a071f3 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sat, 5 Sep 2015 17:53:20 -0500 -Subject: [PATCH 001/139] drivers/i2c/w83795: Add full support for fan control, - fan monitoring, and voltage monitoring +Subject: [PATCH 003/143] drivers/i2c/w83795: Add full support for core + functions + +Add full support for fan control, fan monitoring, and voltage +monitoring. Fan speeds and functions are configurable via +each mainboard's devicetree.cb file. + +NOTE: This patch effectively rewrites large portions of +the original driver. You may need to re-verify correct +operation on your hardware if you were using the old +driver code. Change-Id: I3e246af0e398d65ee43ea708060885c67fd7d202 Signed-off-by: Timothy Pearson --- - src/drivers/i2c/w83795/chip.h | 142 +++++++++++++++++ - src/drivers/i2c/w83795/w83795.c | 334 ++++++++++++++++++++++++++-------------- - src/drivers/i2c/w83795/w83795.h | 52 +++++-- - 3 files changed, 399 insertions(+), 129 deletions(-) + src/drivers/i2c/w83795/chip.h | 142 ++++++++++++++++ + src/drivers/i2c/w83795/w83795.c | 339 ++++++++++++++++++++++++++------------- + src/drivers/i2c/w83795/w83795.h | 52 ++++-- + 3 files changed, 405 insertions(+), 128 deletions(-) create mode 100644 src/drivers/i2c/w83795/chip.h diff --git a/src/drivers/i2c/w83795/chip.h b/src/drivers/i2c/w83795/chip.h new file mode 100644 -index 0000000..effe119 +index 0000000..c8a42ea --- /dev/null +++ b/src/drivers/i2c/w83795/chip.h @@ -0,0 +1,142 @@ +/* + * This file is part of the coreboot project. + * -+ * Copyright (C) 2015 Timothy Pearson , Raptor Engineering ++ * Copyright (C) 2015 Raptor Engineering + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by @@ -162,14 +171,14 @@ index 0000000..effe119 + uint8_t fan8_duty; /* % of full speed (0-100) */ +}; diff --git a/src/drivers/i2c/w83795/w83795.c b/src/drivers/i2c/w83795/w83795.c -index 2bbe0be..cf0cf2f 100644 +index 2bbe0be..0af272f 100644 --- a/src/drivers/i2c/w83795/w83795.c +++ b/src/drivers/i2c/w83795/w83795.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2012 Advanced Micro Devices, Inc. -+ * Copyright (C) 2015 Timothy Pearson , Raptor Engineering ++ * Copyright (C) 2015 Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -306,7 +315,8 @@ index 2bbe0be..cf0cf2f 100644 } -static void w83795_set_tss(void) --{ ++static void w83795_set_fan(struct device *dev, w83795_fan_mode_t mode) + { - u8 val; - - val = 0x00; @@ -316,8 +326,7 @@ index 2bbe0be..cf0cf2f 100644 -} - -static void w83795_set_fan(w83795_fan_mode_t mode) -+static void w83795_set_fan(struct device *dev, w83795_fan_mode_t mode) - { +-{ - u8 i; - - /* select temperature sensor (TSS)*/ @@ -365,8 +374,7 @@ index 2bbe0be..cf0cf2f 100644 + /* Datasheet v1.41 page 44 (VSEN1 - VSEN13, VTT) */ + return ((millivolts / 2) >> 2); +} - -- if (do_smbus_read_byte(SMBUS_IO_BASE, W83795_DEV, 0x00) < 0) { ++ +static uint8_t millivolts_to_limit_value_type2(int millivolts) +{ + /* Datasheet v1.41 page 44 (3VSB, 3VDD, VBAT) */ @@ -385,7 +393,8 @@ index 2bbe0be..cf0cf2f 100644 + uint8_t i; + uint8_t val; + uint16_t limit_value; -+ + +- if (do_smbus_read_byte(SMBUS_IO_BASE, W83795_DEV, 0x00) < 0) { + if (smbus_read_byte(dev, 0x00) < 0) { printk(BIOS_ERR, "W83795G/ADG Nuvoton H/W Monitor not found\n"); return; @@ -395,11 +404,17 @@ index 2bbe0be..cf0cf2f 100644 if ((val & W83795_REG_CONFIG_CONFIG48) == 0) printk(BIOS_INFO, "Found 64 pin W83795G Nuvoton H/W Monitor\n"); else if ((val & W83795_REG_CONFIG_CONFIG48) == 1) -@@ -190,35 +153,178 @@ static void w83795_init(w83795_fan_mode_t mode, u8 dts_src) +@@ -190,35 +153,185 @@ static void w83795_init(w83795_fan_mode_t mode, u8 dts_src) /* Reset */ val |= W83795_REG_CONFIG_INIT; - w83795_write(W83795_REG_CONFIG, val); +- +- /* Fan monitoring setting */ +- val = 0xFF; /* FAN1-FAN8 */ +- w83795_write(W83795_REG_FANIN_CTRL1, val); +- val = 0x3F; /* FAN9-FAN14 */ +- w83795_write(W83795_REG_FANIN_CTRL2, val); + w83795_write(dev, W83795_REG_CONFIG, val); + + /* Fan monitor settings */ @@ -460,21 +475,11 @@ index 2bbe0be..cf0cf2f 100644 + w83795_write(dev, W83795_REG_T12TSS, ((config->temp2_source_select & 0xff) << 8) | (config->temp1_source_select & 0xff)); + w83795_write(dev, W83795_REG_T34TSS, ((config->temp4_source_select & 0xff) << 8) | (config->temp3_source_select & 0xff)); + w83795_write(dev, W83795_REG_T56TSS, ((config->temp6_source_select & 0xff) << 8) | (config->temp5_source_select & 0xff)); - -- /* Fan monitoring setting */ -- val = 0xFF; /* FAN1-FAN8 */ -- w83795_write(W83795_REG_FANIN_CTRL1, val); -- val = 0x3F; /* FAN9-FAN14 */ -- w83795_write(W83795_REG_FANIN_CTRL2, val); -- -- /* enable monitoring operations */ -- val = w83795_read(W83795_REG_CONFIG); -- val |= W83795_REG_CONFIG_START; -- w83795_write(W83795_REG_CONFIG, val); -- -- w83795_dts_enable(dts_src); -- w83795_set_fan(mode); -+ /* Set Critical Temperature to Full Speed all fan (CTFS) */ ++ ++ /* Set critical temperatures ++ * If any sensor exceeds the associated critical temperature, ++ * all fans will be forced to full speed. ++ */ + w83795_write(dev, W83795_REG_CTFS(0), config->temp1_critical_temperature); + w83795_write(dev, W83795_REG_CTFS(1), config->temp2_critical_temperature); + w83795_write(dev, W83795_REG_CTFS(2), config->temp3_critical_temperature); @@ -550,21 +555,31 @@ index 2bbe0be..cf0cf2f 100644 + w83795_write(dev, W83795_REG_VOLT_LIM_LOW(14), millivolts_to_limit_value_type2(config->vbat_low_limit_mv)); + + /* VSEN12 limits */ -+ limit_value = millivolts_to_limit_value_type3(config->vsen12_high_limit_mv); -+ w83795_write(dev, W83795_REG_VOLT_LIM_HIGH_2_M(4), limit_value >> 2); -+ w83795_write(dev, W83795_REG_VOLT_LIM_HIGH_2_L(4), limit_value & 0x3); -+ limit_value = millivolts_to_limit_value_type3(config->vsen12_low_limit_mv); -+ w83795_write(dev, W83795_REG_VOLT_LIM_LOW_2_M(4), limit_value >> 2); -+ w83795_write(dev, W83795_REG_VOLT_LIM_LOW_2_L(4), limit_value & 0x3); -+ ++ if (config->temp_ctl1 & 0x2) { ++ limit_value = millivolts_to_limit_value_type3(config->vsen12_high_limit_mv); ++ w83795_write(dev, W83795_REG_VOLT_LIM_HIGH_2_M(4), limit_value >> 2); ++ w83795_write(dev, W83795_REG_VOLT_LIM_HIGH_2_L(4), limit_value & 0x3); ++ limit_value = millivolts_to_limit_value_type3(config->vsen12_low_limit_mv); ++ w83795_write(dev, W83795_REG_VOLT_LIM_LOW_2_M(4), limit_value >> 2); ++ w83795_write(dev, W83795_REG_VOLT_LIM_LOW_2_L(4), limit_value & 0x3); ++ } + +- /* enable monitoring operations */ +- val = w83795_read(W83795_REG_CONFIG); +- val |= W83795_REG_CONFIG_START; +- w83795_write(W83795_REG_CONFIG, val); + /* VSEN13 limits */ -+ limit_value = millivolts_to_limit_value_type3(config->vsen13_high_limit_mv); -+ w83795_write(dev, W83795_REG_VOLT_LIM_HIGH_2_M(5), limit_value >> 2); -+ w83795_write(dev, W83795_REG_VOLT_LIM_HIGH_2_L(5), limit_value & 0x3); -+ limit_value = millivolts_to_limit_value_type3(config->vsen13_low_limit_mv); -+ w83795_write(dev, W83795_REG_VOLT_LIM_LOW_2_M(5), limit_value >> 2); -+ w83795_write(dev, W83795_REG_VOLT_LIM_LOW_2_L(5), limit_value & 0x3); -+ ++ if (config->temp_ctl1 & 0x8) { ++ limit_value = millivolts_to_limit_value_type3(config->vsen13_high_limit_mv); ++ w83795_write(dev, W83795_REG_VOLT_LIM_HIGH_2_M(5), limit_value >> 2); ++ w83795_write(dev, W83795_REG_VOLT_LIM_HIGH_2_L(5), limit_value & 0x3); ++ limit_value = millivolts_to_limit_value_type3(config->vsen13_low_limit_mv); ++ w83795_write(dev, W83795_REG_VOLT_LIM_LOW_2_M(5), limit_value >> 2); ++ w83795_write(dev, W83795_REG_VOLT_LIM_LOW_2_L(5), limit_value & 0x3); ++ } + +- w83795_dts_enable(dts_src); +- w83795_set_fan(mode); + w83795_set_fan(dev, mode); printk(BIOS_INFO, "Fan CTFS(celsius) TTTI(celsius)\n"); @@ -591,7 +606,7 @@ index 2bbe0be..cf0cf2f 100644 } static void w83795_hwm_init(struct device *dev) -@@ -232,9 +338,9 @@ static void w83795_hwm_init(struct device *dev) +@@ -232,9 +345,9 @@ static void w83795_hwm_init(struct device *dev) die("CPU: missing cpu device structure"); if (cpu->vendor == X86_VENDOR_AMD) @@ -604,14 +619,14 @@ index 2bbe0be..cf0cf2f 100644 printk(BIOS_ERR, "Neither AMD nor INTEL CPU detected\n"); } diff --git a/src/drivers/i2c/w83795/w83795.h b/src/drivers/i2c/w83795/w83795.h -index cac4d5f..0727dc5 100644 +index cac4d5f..ef603f5 100644 --- a/src/drivers/i2c/w83795/w83795.h +++ b/src/drivers/i2c/w83795/w83795.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2012 Advanced Micro Devices, Inc. -+ * Copyright (C) 2015 Timothy Pearson , Raptor Engineering ++ * Copyright (C) 2015 Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -706,5 +721,5 @@ index cac4d5f..0727dc5 100644 #endif -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0003-drivers-i2c-w83795-Add-option-to-use-auxiliary-SMBUS.patch b/resources/libreboot/patch/kgpe-d16/0003-drivers-i2c-w83795-Add-option-to-use-auxiliary-SMBUS.patch deleted file mode 100644 index b984f28..0000000 --- a/resources/libreboot/patch/kgpe-d16/0003-drivers-i2c-w83795-Add-option-to-use-auxiliary-SMBUS.patch +++ /dev/null @@ -1,62 +0,0 @@ -From 3e2be2d88101331eedb59c1459630b553c7cb660 Mon Sep 17 00:00:00 2001 -From: Timothy Pearson -Date: Sat, 17 Oct 2015 04:37:10 -0500 -Subject: [PATCH 003/139] drivers/i2c/w83795: Add option to use auxiliary SMBUS - controller - -Change-Id: I5a9b5eba992853b84b0cb6c3a1764edf42ac49b2 -Signed-off-by: Timothy Pearson ---- - src/drivers/i2c/w83795/chip.h | 4 ++++ - src/drivers/i2c/w83795/w83795.c | 14 ++++++++++++++ - 2 files changed, 18 insertions(+) - -diff --git a/src/drivers/i2c/w83795/chip.h b/src/drivers/i2c/w83795/chip.h -index effe119..413ea87 100644 ---- a/src/drivers/i2c/w83795/chip.h -+++ b/src/drivers/i2c/w83795/chip.h -@@ -139,4 +139,8 @@ struct drivers_i2c_w83795_config { - uint8_t fan6_duty; /* % of full speed (0-100) */ - uint8_t fan7_duty; /* % of full speed (0-100) */ - uint8_t fan8_duty; /* % of full speed (0-100) */ -+ -+ uint8_t smbus_aux; /* 0 == device located on first SMBUS, -+ * 1 == device located on auxiliary SMBUS -+ */ - }; -diff --git a/src/drivers/i2c/w83795/w83795.c b/src/drivers/i2c/w83795/w83795.c -index cf0cf2f..453e0af 100644 ---- a/src/drivers/i2c/w83795/w83795.c -+++ b/src/drivers/i2c/w83795/w83795.c -@@ -141,7 +141,16 @@ static void w83795_init(struct device *dev, w83795_fan_mode_t mode, u8 dts_src) - uint8_t val; - uint16_t limit_value; - -+#if IS_ENABLED(CONFIG_SMBUS_HAS_AUX) -+ uint8_t smbus_aux_prev = smbus_switched_to_aux(); -+ smbus_switch_to_aux(config->smbus_aux); -+#endif -+ - if (smbus_read_byte(dev, 0x00) < 0) { -+#if IS_ENABLED(CONFIG_SMBUS_HAS_AUX) -+ /* Restore SMBUS channel setting */ -+ smbus_switch_to_aux(smbus_aux_prev); -+#endif - printk(BIOS_ERR, "W83795G/ADG Nuvoton H/W Monitor not found\n"); - return; - } -@@ -325,6 +334,11 @@ static void w83795_init(struct device *dev, w83795_fan_mode_t mode, u8 dts_src) - val = w83795_read(dev, W83795_REG_CONFIG); - val |= W83795_REG_CONFIG_START; - w83795_write(dev, W83795_REG_CONFIG, val); -+ -+#if IS_ENABLED(CONFIG_SMBUS_HAS_AUX) -+ /* Restore SMBUS channel setting */ -+ smbus_switch_to_aux(smbus_aux_prev); -+#endif - } - - static void w83795_hwm_init(struct device *dev) --- -1.9.1 - diff --git a/resources/libreboot/patch/kgpe-d16/0004-drivers-i2c-w83795-Add-option-to-use-auxiliary-SMBUS.patch b/resources/libreboot/patch/kgpe-d16/0004-drivers-i2c-w83795-Add-option-to-use-auxiliary-SMBUS.patch new file mode 100644 index 0000000..ccb52ae --- /dev/null +++ b/resources/libreboot/patch/kgpe-d16/0004-drivers-i2c-w83795-Add-option-to-use-auxiliary-SMBUS.patch @@ -0,0 +1,68 @@ +From 8996dda2293b74ec84251cc2eefb7722acd6bd6b Mon Sep 17 00:00:00 2001 +From: Timothy Pearson +Date: Sat, 17 Oct 2015 04:37:10 -0500 +Subject: [PATCH 004/143] drivers/i2c/w83795: Add option to use auxiliary + SMBUS controller + +Change-Id: I5a9b5eba992853b84b0cb6c3a1764edf42ac49b2 +Signed-off-by: Timothy Pearson +--- + src/drivers/i2c/w83795/chip.h | 7 +++++++ + src/drivers/i2c/w83795/w83795.c | 17 +++++++++++++++++ + 2 files changed, 24 insertions(+) + +diff --git a/src/drivers/i2c/w83795/chip.h b/src/drivers/i2c/w83795/chip.h +index c8a42ea..9a3f847 100644 +--- a/src/drivers/i2c/w83795/chip.h ++++ b/src/drivers/i2c/w83795/chip.h +@@ -139,4 +139,11 @@ struct drivers_i2c_w83795_config { + uint8_t fan6_duty; /* % of full speed (0-100) */ + uint8_t fan7_duty; /* % of full speed (0-100) */ + uint8_t fan8_duty; /* % of full speed (0-100) */ ++ ++ uint8_t smbus_aux; /* 0 == device located on primary SMBUS, ++ * 1 == device located on first auxiliary ++ * SMBUS channel, ++ * == device located on auxiliary ++ * SMBUS channel ++ */ + }; +diff --git a/src/drivers/i2c/w83795/w83795.c b/src/drivers/i2c/w83795/w83795.c +index 0af272f..0f82e1c 100644 +--- a/src/drivers/i2c/w83795/w83795.c ++++ b/src/drivers/i2c/w83795/w83795.c +@@ -141,7 +141,18 @@ static void w83795_init(struct device *dev, w83795_fan_mode_t mode, u8 dts_src) + uint8_t val; + uint16_t limit_value; + ++#if IS_ENABLED(CONFIG_SMBUS_HAS_AUX_CHANNELS) ++ uint8_t smbus_aux_channel_prev = smbus_current_aux_channel(); ++ smbus_switch_to_aux_channel(config->smbus_aux); ++ printk(BIOS_DEBUG, "Set SMBUS controller to channel %d\n", config->smbus_aux); ++#endif ++ + if (smbus_read_byte(dev, 0x00) < 0) { ++#if IS_ENABLED(CONFIG_SMBUS_HAS_AUX_CHANNELS) ++ /* Restore SMBUS channel setting */ ++ smbus_switch_to_aux_channel(smbus_aux_channel_prev); ++ printk(BIOS_DEBUG, "Set SMBUS controller to channel %d\n", smbus_aux_channel_prev); ++#endif + printk(BIOS_ERR, "W83795G/ADG Nuvoton H/W Monitor not found\n"); + return; + } +@@ -332,6 +343,12 @@ static void w83795_init(struct device *dev, w83795_fan_mode_t mode, u8 dts_src) + val = w83795_read(dev, W83795_REG_CONFIG); + val |= W83795_REG_CONFIG_START; + w83795_write(dev, W83795_REG_CONFIG, val); ++ ++#if IS_ENABLED(CONFIG_SMBUS_HAS_AUX_CHANNELS) ++ /* Restore SMBUS channel setting */ ++ smbus_switch_to_aux_channel(smbus_aux_channel_prev); ++ printk(BIOS_DEBUG, "Set SMBUS controller to channel %d\n", smbus_aux_channel_prev); ++#endif + } + + static void w83795_hwm_init(struct device *dev) +-- +1.7.9.5 + diff --git a/resources/libreboot/patch/kgpe-d16/0005-mainboard-Update-mainboards-using-the-w83795-sensor-.patch b/resources/libreboot/patch/kgpe-d16/0005-mainboard-Update-mainboards-using-the-w83795-sensor-.patch new file mode 100644 index 0000000..e848f49 --- /dev/null +++ b/resources/libreboot/patch/kgpe-d16/0005-mainboard-Update-mainboards-using-the-w83795-sensor-.patch @@ -0,0 +1,323 @@ +From 2b9d5ca0b29cbe6e1600879b5cc731c2c4cb106d Mon Sep 17 00:00:00 2001 +From: Timothy Pearson +Date: Thu, 22 Oct 2015 02:53:39 -0500 +Subject: [PATCH 005/143] mainboard: Update mainboards using the w83795 sensor + device + +Update mainboards using the w83795 sensor device with sane default +values. Note that in some cases the defaults may vary from the +defaults provided by the old driver, for example the default fan +speeds and control modes have changed as I do not have any information +on the correct sensor to fan mappings for these boards. + +Change-Id: Id2ad6222d7a0f29483b022fa097d7d098c6b4122 +Signed-off-by: Timothy Pearson +--- + src/mainboard/supermicro/h8qgi/devicetree.cb | 89 ++++++++++++++++++++++++++ + src/mainboard/supermicro/h8scm/devicetree.cb | 89 ++++++++++++++++++++++++++ + src/mainboard/tyan/s8226/devicetree.cb | 89 ++++++++++++++++++++++++++ + 3 files changed, 267 insertions(+) + +diff --git a/src/mainboard/supermicro/h8qgi/devicetree.cb b/src/mainboard/supermicro/h8qgi/devicetree.cb +index 59740c9..6c3ee90 100644 +--- a/src/mainboard/supermicro/h8qgi/devicetree.cb ++++ b/src/mainboard/supermicro/h8qgi/devicetree.cb +@@ -107,6 +107,95 @@ chip northbridge/amd/agesa/family15/root_complex + end + end #superio/winbond/w83627dhg + chip drivers/i2c/w83795 ++ register "fanin_ctl1" = "0xff" # Enable monitoring of FANIN1 - FANIN8 ++ register "fanin_ctl2" = "0x00" # Connect FANIN11 - FANIN14 to alternate functions ++ register "temp_ctl1" = "0x2a" # Enable monitoring of DTS, VSEN12, and VSEN13 ++ register "temp_ctl2" = "0x01" # Enable monitoring of TD1/TR1 ++ register "temp_dtse" = "0x03" # Enable DTS1 and DTS2 ++ register "volt_ctl1" = "0xff" # Enable monitoring of VSEN1 - VSEN8 ++ register "volt_ctl2" = "0xf7" # Enable monitoring of VSEN9 - VSEN11, 3VDD, 3VSB, and VBAT ++ register "temp1_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp1) ++ register "temp2_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp2) ++ register "temp3_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp3) ++ register "temp4_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp4) ++ register "temp5_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp5) ++ register "temp6_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp6) ++ register "temp1_source_select" = "0x00" # Use TD1/TR1 as data source for Temp1 ++ register "temp2_source_select" = "0x00" # Use TD2/TR2 as data source for Temp2 ++ register "temp3_source_select" = "0x00" # Use TD3/TR3 as data source for Temp3 ++ register "temp4_source_select" = "0x00" # Use TD4/TR4 as data source for Temp4 ++ register "temp5_source_select" = "0x00" # Use TR5 as data source for Temp5 ++ register "temp6_source_select" = "0x00" # Use TR6 as data source for Temp6 ++ register "tr1_critical_temperature" = "85" # Set TD1/TR1 critical temperature to 85°C ++ register "tr1_critical_hysteresis" = "80" # Set TD1/TR1 critical hysteresis temperature to 80°C ++ register "tr1_warning_temperature" = "70" # Set TD1/TR1 warning temperature to 70°C ++ register "tr1_warning_hysteresis" = "65" # Set TD1/TR1 warning hysteresis temperature to 65°C ++ register "dts_critical_temperature" = "85" # Set DTS (CPU) critical temperature to 85°C ++ register "dts_critical_hysteresis" = "80" # Set DTS (CPU) critical hysteresis temperature to 80°C ++ register "dts_warning_temperature" = "70" # Set DTS (CPU) warning temperature to 70°C ++ register "dts_warning_hysteresis" = "65" # Set DTS (CPU) warning hysteresis temperature to 65°C ++ register "temp1_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C ++ register "temp2_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C ++ register "temp3_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C ++ register "temp4_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C ++ register "temp5_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C ++ register "temp6_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C ++ register "temp1_target_temperature" = "80" # Set Temp1 target temperature to 80°C ++ register "temp2_target_temperature" = "80" # Set Temp1 target temperature to 80°C ++ register "temp3_target_temperature" = "80" # Set Temp1 target temperature to 80°C ++ register "temp4_target_temperature" = "80" # Set Temp1 target temperature to 80°C ++ register "temp5_target_temperature" = "80" # Set Temp1 target temperature to 80°C ++ register "temp6_target_temperature" = "80" # Set Temp1 target temperature to 80°C ++ register "fan1_nonstop" = "7" # Set Fan 1 minimum speed ++ register "fan2_nonstop" = "7" # Set Fan 2 minimum speed ++ register "fan3_nonstop" = "7" # Set Fan 3 minimum speed ++ register "fan4_nonstop" = "7" # Set Fan 4 minimum speed ++ register "fan5_nonstop" = "7" # Set Fan 5 minimum speed ++ register "fan6_nonstop" = "7" # Set Fan 6 minimum speed ++ register "fan7_nonstop" = "7" # Set Fan 7 minimum speed ++ register "fan8_nonstop" = "7" # Set Fan 8 minimum speed ++ register "default_speed" = "100" # All fans to full speed on power up ++ register "fan1_duty" = "100" # Fan 1 to full speed ++ register "fan2_duty" = "100" # Fan 2 to full speed ++ register "fan3_duty" = "100" # Fan 3 to full speed ++ register "fan4_duty" = "100" # Fan 4 to full speed ++ register "fan5_duty" = "100" # Fan 5 to full speed ++ register "fan6_duty" = "100" # Fan 6 to full speed ++ register "fan7_duty" = "100" # Fan 7 to full speed ++ register "fan8_duty" = "100" # Fan 8 to full speed ++ register "vcore1_high_limit_mv" = "1500" # VCORE1 (Node 0) high limit to 1.5V ++ register "vcore1_low_limit_mv" = "900" # VCORE1 (Node 0) low limit to 0.9V ++ register "vcore2_high_limit_mv" = "1500" # VCORE2 (Node 1) high limit to 1.5V ++ register "vcore2_low_limit_mv" = "900" # VCORE2 (Node 1) low limit to 0.9V ++ register "vsen3_high_limit_mv" = "1600" # VSEN1 (Node 0 RAM voltage) high limit to 1.6V ++ register "vsen3_low_limit_mv" = "1100" # VSEN1 (Node 0 RAM voltage) low limit to 1.1V ++ register "vsen4_high_limit_mv" = "1600" # VSEN2 (Node 1 RAM voltage) high limit to 1.6V ++ register "vsen4_low_limit_mv" = "1100" # VSEN2 (Node 1 RAM voltage) low limit to 1.1V ++ register "vsen5_high_limit_mv" = "1250" # VSEN5 (Node 0 HT link voltage) high limit to 1.25V ++ register "vsen5_low_limit_mv" = "1150" # VSEN5 (Node 0 HT link voltage) low limit to 1.15V ++ register "vsen6_high_limit_mv" = "1250" # VSEN6 (Node 1 HT link voltage) high limit to 1.25V ++ register "vsen6_low_limit_mv" = "1150" # VSEN6 (Node 1 HT link voltage) low limit to 1.15V ++ register "vsen7_high_limit_mv" = "1150" # VSEN7 (Northbridge core voltage) high limit to 1.15V ++ register "vsen7_low_limit_mv" = "1050" # VSEN7 (Northbridge core voltage) low limit to 1.05V ++ register "vsen8_high_limit_mv" = "1900" # VSEN8 (+1.8V) high limit to 1.9V ++ register "vsen8_low_limit_mv" = "1700" # VSEN8 (+1.8V) low limit to 1.7V ++ register "vsen9_high_limit_mv" = "1250" # VSEN9 (+1.2V) high limit to 1.25V ++ register "vsen9_low_limit_mv" = "1150" # VSEN9 (+1.2V) low limit to 1.15V ++ register "vsen10_high_limit_mv" = "1150" # VSEN10 (+1.1V) high limit to 1.15V ++ register "vsen10_low_limit_mv" = "1050" # VSEN10 (+1.1V) low limit to 1.05V ++ register "vsen11_high_limit_mv" = "1625" # VSEN11 (5VSB, scaling factor ~3.2) high limit to 5.2V ++ register "vsen11_low_limit_mv" = "1500" # VSEN11 (5VSB, scaling factor ~3.2) low limit to 4.8V ++ register "vsen12_high_limit_mv" = "1083" # VSEN12 (+12V, scaling factor ~12) high limit to 13V ++ register "vsen12_low_limit_mv" = "917" # VSEN12 (+12V, scaling factor ~12) low limit to 11V ++ register "vsen13_high_limit_mv" = "1625" # VSEN13 (+5V, scaling factor ~3.2) high limit to 5.2V ++ register "vsen13_low_limit_mv" = "1500" # VSEN13 (+5V, scaling factor ~3.2) low limit to 4.8V ++ register "vdd_high_limit_mv" = "3500" # 3VDD high limit to 3.5V ++ register "vdd_low_limit_mv" = "3100" # 3VDD low limit to 3.1V ++ register "vsb_high_limit_mv" = "3500" # 3VSB high limit to 3.5V ++ register "vsb_low_limit_mv" = "3100" # 3VSB low limit to 3.1V ++ register "vbat_high_limit_mv" = "3500" # VBAT (+3V) high limit to 3.5V ++ register "vbat_low_limit_mv" = "2500" # VBAT (+3V) low limit to 2.5V ++ register "smbus_aux" = "0" # Device located on primary SMBUS + device pnp 5e on #hwm + end + end #drivers/i2c/w83795 +diff --git a/src/mainboard/supermicro/h8scm/devicetree.cb b/src/mainboard/supermicro/h8scm/devicetree.cb +index b8fb823..a280e62 100644 +--- a/src/mainboard/supermicro/h8scm/devicetree.cb ++++ b/src/mainboard/supermicro/h8scm/devicetree.cb +@@ -106,6 +106,95 @@ chip northbridge/amd/agesa/family15/root_complex + end + end #superio/winbond/w83627dhg + chip drivers/i2c/w83795 ++ register "fanin_ctl1" = "0xff" # Enable monitoring of FANIN1 - FANIN8 ++ register "fanin_ctl2" = "0x00" # Connect FANIN11 - FANIN14 to alternate functions ++ register "temp_ctl1" = "0x2a" # Enable monitoring of DTS, VSEN12, and VSEN13 ++ register "temp_ctl2" = "0x01" # Enable monitoring of TD1/TR1 ++ register "temp_dtse" = "0x03" # Enable DTS1 and DTS2 ++ register "volt_ctl1" = "0xff" # Enable monitoring of VSEN1 - VSEN8 ++ register "volt_ctl2" = "0xf7" # Enable monitoring of VSEN9 - VSEN11, 3VDD, 3VSB, and VBAT ++ register "temp1_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp1) ++ register "temp2_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp2) ++ register "temp3_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp3) ++ register "temp4_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp4) ++ register "temp5_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp5) ++ register "temp6_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp6) ++ register "temp1_source_select" = "0x00" # Use TD1/TR1 as data source for Temp1 ++ register "temp2_source_select" = "0x00" # Use TD2/TR2 as data source for Temp2 ++ register "temp3_source_select" = "0x00" # Use TD3/TR3 as data source for Temp3 ++ register "temp4_source_select" = "0x00" # Use TD4/TR4 as data source for Temp4 ++ register "temp5_source_select" = "0x00" # Use TR5 as data source for Temp5 ++ register "temp6_source_select" = "0x00" # Use TR6 as data source for Temp6 ++ register "tr1_critical_temperature" = "85" # Set TD1/TR1 critical temperature to 85°C ++ register "tr1_critical_hysteresis" = "80" # Set TD1/TR1 critical hysteresis temperature to 80°C ++ register "tr1_warning_temperature" = "70" # Set TD1/TR1 warning temperature to 70°C ++ register "tr1_warning_hysteresis" = "65" # Set TD1/TR1 warning hysteresis temperature to 65°C ++ register "dts_critical_temperature" = "85" # Set DTS (CPU) critical temperature to 85°C ++ register "dts_critical_hysteresis" = "80" # Set DTS (CPU) critical hysteresis temperature to 80°C ++ register "dts_warning_temperature" = "70" # Set DTS (CPU) warning temperature to 70°C ++ register "dts_warning_hysteresis" = "65" # Set DTS (CPU) warning hysteresis temperature to 65°C ++ register "temp1_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C ++ register "temp2_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C ++ register "temp3_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C ++ register "temp4_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C ++ register "temp5_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C ++ register "temp6_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C ++ register "temp1_target_temperature" = "80" # Set Temp1 target temperature to 80°C ++ register "temp2_target_temperature" = "80" # Set Temp1 target temperature to 80°C ++ register "temp3_target_temperature" = "80" # Set Temp1 target temperature to 80°C ++ register "temp4_target_temperature" = "80" # Set Temp1 target temperature to 80°C ++ register "temp5_target_temperature" = "80" # Set Temp1 target temperature to 80°C ++ register "temp6_target_temperature" = "80" # Set Temp1 target temperature to 80°C ++ register "fan1_nonstop" = "7" # Set Fan 1 minimum speed ++ register "fan2_nonstop" = "7" # Set Fan 2 minimum speed ++ register "fan3_nonstop" = "7" # Set Fan 3 minimum speed ++ register "fan4_nonstop" = "7" # Set Fan 4 minimum speed ++ register "fan5_nonstop" = "7" # Set Fan 5 minimum speed ++ register "fan6_nonstop" = "7" # Set Fan 6 minimum speed ++ register "fan7_nonstop" = "7" # Set Fan 7 minimum speed ++ register "fan8_nonstop" = "7" # Set Fan 8 minimum speed ++ register "default_speed" = "100" # All fans to full speed on power up ++ register "fan1_duty" = "100" # Fan 1 to full speed ++ register "fan2_duty" = "100" # Fan 2 to full speed ++ register "fan3_duty" = "100" # Fan 3 to full speed ++ register "fan4_duty" = "100" # Fan 4 to full speed ++ register "fan5_duty" = "100" # Fan 5 to full speed ++ register "fan6_duty" = "100" # Fan 6 to full speed ++ register "fan7_duty" = "100" # Fan 7 to full speed ++ register "fan8_duty" = "100" # Fan 8 to full speed ++ register "vcore1_high_limit_mv" = "1500" # VCORE1 (Node 0) high limit to 1.5V ++ register "vcore1_low_limit_mv" = "900" # VCORE1 (Node 0) low limit to 0.9V ++ register "vcore2_high_limit_mv" = "1500" # VCORE2 (Node 1) high limit to 1.5V ++ register "vcore2_low_limit_mv" = "900" # VCORE2 (Node 1) low limit to 0.9V ++ register "vsen3_high_limit_mv" = "1600" # VSEN1 (Node 0 RAM voltage) high limit to 1.6V ++ register "vsen3_low_limit_mv" = "1100" # VSEN1 (Node 0 RAM voltage) low limit to 1.1V ++ register "vsen4_high_limit_mv" = "1600" # VSEN2 (Node 1 RAM voltage) high limit to 1.6V ++ register "vsen4_low_limit_mv" = "1100" # VSEN2 (Node 1 RAM voltage) low limit to 1.1V ++ register "vsen5_high_limit_mv" = "1250" # VSEN5 (Node 0 HT link voltage) high limit to 1.25V ++ register "vsen5_low_limit_mv" = "1150" # VSEN5 (Node 0 HT link voltage) low limit to 1.15V ++ register "vsen6_high_limit_mv" = "1250" # VSEN6 (Node 1 HT link voltage) high limit to 1.25V ++ register "vsen6_low_limit_mv" = "1150" # VSEN6 (Node 1 HT link voltage) low limit to 1.15V ++ register "vsen7_high_limit_mv" = "1150" # VSEN7 (Northbridge core voltage) high limit to 1.15V ++ register "vsen7_low_limit_mv" = "1050" # VSEN7 (Northbridge core voltage) low limit to 1.05V ++ register "vsen8_high_limit_mv" = "1900" # VSEN8 (+1.8V) high limit to 1.9V ++ register "vsen8_low_limit_mv" = "1700" # VSEN8 (+1.8V) low limit to 1.7V ++ register "vsen9_high_limit_mv" = "1250" # VSEN9 (+1.2V) high limit to 1.25V ++ register "vsen9_low_limit_mv" = "1150" # VSEN9 (+1.2V) low limit to 1.15V ++ register "vsen10_high_limit_mv" = "1150" # VSEN10 (+1.1V) high limit to 1.15V ++ register "vsen10_low_limit_mv" = "1050" # VSEN10 (+1.1V) low limit to 1.05V ++ register "vsen11_high_limit_mv" = "1625" # VSEN11 (5VSB, scaling factor ~3.2) high limit to 5.2V ++ register "vsen11_low_limit_mv" = "1500" # VSEN11 (5VSB, scaling factor ~3.2) low limit to 4.8V ++ register "vsen12_high_limit_mv" = "1083" # VSEN12 (+12V, scaling factor ~12) high limit to 13V ++ register "vsen12_low_limit_mv" = "917" # VSEN12 (+12V, scaling factor ~12) low limit to 11V ++ register "vsen13_high_limit_mv" = "1625" # VSEN13 (+5V, scaling factor ~3.2) high limit to 5.2V ++ register "vsen13_low_limit_mv" = "1500" # VSEN13 (+5V, scaling factor ~3.2) low limit to 4.8V ++ register "vdd_high_limit_mv" = "3500" # 3VDD high limit to 3.5V ++ register "vdd_low_limit_mv" = "3100" # 3VDD low limit to 3.1V ++ register "vsb_high_limit_mv" = "3500" # 3VSB high limit to 3.5V ++ register "vsb_low_limit_mv" = "3100" # 3VSB low limit to 3.1V ++ register "vbat_high_limit_mv" = "3500" # VBAT (+3V) high limit to 3.5V ++ register "vbat_low_limit_mv" = "2500" # VBAT (+3V) low limit to 2.5V ++ register "smbus_aux" = "0" # Device located on primary SMBUS + device pnp 5e on #hwm + end + end #drivers/i2c/w83795 +diff --git a/src/mainboard/tyan/s8226/devicetree.cb b/src/mainboard/tyan/s8226/devicetree.cb +index 64701a5..9f5e584 100644 +--- a/src/mainboard/tyan/s8226/devicetree.cb ++++ b/src/mainboard/tyan/s8226/devicetree.cb +@@ -106,6 +106,95 @@ chip northbridge/amd/agesa/family15/root_complex + end + end #superio/winbond/w83627dhg + chip drivers/i2c/w83795 ++ register "fanin_ctl1" = "0xff" # Enable monitoring of FANIN1 - FANIN8 ++ register "fanin_ctl2" = "0x00" # Connect FANIN11 - FANIN14 to alternate functions ++ register "temp_ctl1" = "0x2a" # Enable monitoring of DTS, VSEN12, and VSEN13 ++ register "temp_ctl2" = "0x01" # Enable monitoring of TD1/TR1 ++ register "temp_dtse" = "0x03" # Enable DTS1 and DTS2 ++ register "volt_ctl1" = "0xff" # Enable monitoring of VSEN1 - VSEN8 ++ register "volt_ctl2" = "0xf7" # Enable monitoring of VSEN9 - VSEN11, 3VDD, 3VSB, and VBAT ++ register "temp1_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp1) ++ register "temp2_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp2) ++ register "temp3_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp3) ++ register "temp4_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp4) ++ register "temp5_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp5) ++ register "temp6_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp6) ++ register "temp1_source_select" = "0x00" # Use TD1/TR1 as data source for Temp1 ++ register "temp2_source_select" = "0x00" # Use TD2/TR2 as data source for Temp2 ++ register "temp3_source_select" = "0x00" # Use TD3/TR3 as data source for Temp3 ++ register "temp4_source_select" = "0x00" # Use TD4/TR4 as data source for Temp4 ++ register "temp5_source_select" = "0x00" # Use TR5 as data source for Temp5 ++ register "temp6_source_select" = "0x00" # Use TR6 as data source for Temp6 ++ register "tr1_critical_temperature" = "85" # Set TD1/TR1 critical temperature to 85°C ++ register "tr1_critical_hysteresis" = "80" # Set TD1/TR1 critical hysteresis temperature to 80°C ++ register "tr1_warning_temperature" = "70" # Set TD1/TR1 warning temperature to 70°C ++ register "tr1_warning_hysteresis" = "65" # Set TD1/TR1 warning hysteresis temperature to 65°C ++ register "dts_critical_temperature" = "85" # Set DTS (CPU) critical temperature to 85°C ++ register "dts_critical_hysteresis" = "80" # Set DTS (CPU) critical hysteresis temperature to 80°C ++ register "dts_warning_temperature" = "70" # Set DTS (CPU) warning temperature to 70°C ++ register "dts_warning_hysteresis" = "65" # Set DTS (CPU) warning hysteresis temperature to 65°C ++ register "temp1_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C ++ register "temp2_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C ++ register "temp3_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C ++ register "temp4_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C ++ register "temp5_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C ++ register "temp6_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C ++ register "temp1_target_temperature" = "80" # Set Temp1 target temperature to 80°C ++ register "temp2_target_temperature" = "80" # Set Temp1 target temperature to 80°C ++ register "temp3_target_temperature" = "80" # Set Temp1 target temperature to 80°C ++ register "temp4_target_temperature" = "80" # Set Temp1 target temperature to 80°C ++ register "temp5_target_temperature" = "80" # Set Temp1 target temperature to 80°C ++ register "temp6_target_temperature" = "80" # Set Temp1 target temperature to 80°C ++ register "fan1_nonstop" = "7" # Set Fan 1 minimum speed ++ register "fan2_nonstop" = "7" # Set Fan 2 minimum speed ++ register "fan3_nonstop" = "7" # Set Fan 3 minimum speed ++ register "fan4_nonstop" = "7" # Set Fan 4 minimum speed ++ register "fan5_nonstop" = "7" # Set Fan 5 minimum speed ++ register "fan6_nonstop" = "7" # Set Fan 6 minimum speed ++ register "fan7_nonstop" = "7" # Set Fan 7 minimum speed ++ register "fan8_nonstop" = "7" # Set Fan 8 minimum speed ++ register "default_speed" = "100" # All fans to full speed on power up ++ register "fan1_duty" = "100" # Fan 1 to full speed ++ register "fan2_duty" = "100" # Fan 2 to full speed ++ register "fan3_duty" = "100" # Fan 3 to full speed ++ register "fan4_duty" = "100" # Fan 4 to full speed ++ register "fan5_duty" = "100" # Fan 5 to full speed ++ register "fan6_duty" = "100" # Fan 6 to full speed ++ register "fan7_duty" = "100" # Fan 7 to full speed ++ register "fan8_duty" = "100" # Fan 8 to full speed ++ register "vcore1_high_limit_mv" = "1500" # VCORE1 (Node 0) high limit to 1.5V ++ register "vcore1_low_limit_mv" = "900" # VCORE1 (Node 0) low limit to 0.9V ++ register "vcore2_high_limit_mv" = "1500" # VCORE2 (Node 1) high limit to 1.5V ++ register "vcore2_low_limit_mv" = "900" # VCORE2 (Node 1) low limit to 0.9V ++ register "vsen3_high_limit_mv" = "1600" # VSEN1 (Node 0 RAM voltage) high limit to 1.6V ++ register "vsen3_low_limit_mv" = "1100" # VSEN1 (Node 0 RAM voltage) low limit to 1.1V ++ register "vsen4_high_limit_mv" = "1600" # VSEN2 (Node 1 RAM voltage) high limit to 1.6V ++ register "vsen4_low_limit_mv" = "1100" # VSEN2 (Node 1 RAM voltage) low limit to 1.1V ++ register "vsen5_high_limit_mv" = "1250" # VSEN5 (Node 0 HT link voltage) high limit to 1.25V ++ register "vsen5_low_limit_mv" = "1150" # VSEN5 (Node 0 HT link voltage) low limit to 1.15V ++ register "vsen6_high_limit_mv" = "1250" # VSEN6 (Node 1 HT link voltage) high limit to 1.25V ++ register "vsen6_low_limit_mv" = "1150" # VSEN6 (Node 1 HT link voltage) low limit to 1.15V ++ register "vsen7_high_limit_mv" = "1150" # VSEN7 (Northbridge core voltage) high limit to 1.15V ++ register "vsen7_low_limit_mv" = "1050" # VSEN7 (Northbridge core voltage) low limit to 1.05V ++ register "vsen8_high_limit_mv" = "1900" # VSEN8 (+1.8V) high limit to 1.9V ++ register "vsen8_low_limit_mv" = "1700" # VSEN8 (+1.8V) low limit to 1.7V ++ register "vsen9_high_limit_mv" = "1250" # VSEN9 (+1.2V) high limit to 1.25V ++ register "vsen9_low_limit_mv" = "1150" # VSEN9 (+1.2V) low limit to 1.15V ++ register "vsen10_high_limit_mv" = "1150" # VSEN10 (+1.1V) high limit to 1.15V ++ register "vsen10_low_limit_mv" = "1050" # VSEN10 (+1.1V) low limit to 1.05V ++ register "vsen11_high_limit_mv" = "1625" # VSEN11 (5VSB, scaling factor ~3.2) high limit to 5.2V ++ register "vsen11_low_limit_mv" = "1500" # VSEN11 (5VSB, scaling factor ~3.2) low limit to 4.8V ++ register "vsen12_high_limit_mv" = "1083" # VSEN12 (+12V, scaling factor ~12) high limit to 13V ++ register "vsen12_low_limit_mv" = "917" # VSEN12 (+12V, scaling factor ~12) low limit to 11V ++ register "vsen13_high_limit_mv" = "1625" # VSEN13 (+5V, scaling factor ~3.2) high limit to 5.2V ++ register "vsen13_low_limit_mv" = "1500" # VSEN13 (+5V, scaling factor ~3.2) low limit to 4.8V ++ register "vdd_high_limit_mv" = "3500" # 3VDD high limit to 3.5V ++ register "vdd_low_limit_mv" = "3100" # 3VDD low limit to 3.1V ++ register "vsb_high_limit_mv" = "3500" # 3VSB high limit to 3.5V ++ register "vsb_low_limit_mv" = "3100" # 3VSB low limit to 3.1V ++ register "vbat_high_limit_mv" = "3500" # VBAT (+3V) high limit to 3.5V ++ register "vbat_low_limit_mv" = "2500" # VBAT (+3V) low limit to 2.5V ++ register "smbus_aux" = "0" # Device located on primary SMBUS + device pnp 5e on #hwm + end + end #drivers/i2c/w83795 +-- +1.7.9.5 + diff --git a/resources/libreboot/patch/kgpe-d16/0004-drivers-aspeed-Add-native-text-mode-VGA-support-for-.patch b/resources/libreboot/patch/kgpe-d16/0006-drivers-aspeed-Add-native-text-mode-VGA-support-for-.patch index 3d9c5c8..b243026 100644 --- a/resources/libreboot/patch/kgpe-d16/0004-drivers-aspeed-Add-native-text-mode-VGA-support-for-.patch +++ b/resources/libreboot/patch/kgpe-d16/0006-drivers-aspeed-Add-native-text-mode-VGA-support-for-.patch @@ -1,7 +1,7 @@ -From 7075bbddd264958b80ea4831b602b6fbfaf60b0d Mon Sep 17 00:00:00 2001 +From 913f5fe9e0107c27e0029fe76f62b37f88ccb221 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sat, 5 Sep 2015 17:38:09 -0500 -Subject: [PATCH 004/139] drivers/aspeed: Add native text mode VGA support for +Subject: [PATCH 006/143] drivers/aspeed: Add native text mode VGA support for the AST2050 Change-Id: I37763a59d2546cd0c0e57b31fdb7aa77c2c50bee @@ -3671,5 +3671,5 @@ index dcb8a42..fcaf4aa 100644 #define PCI_DEVICE_ID_SYMPHONY_101 0x0001 -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0005-southbridge-amd-sb700-Fix-boot-hang-on-ASUS-KGPE-D16.patch b/resources/libreboot/patch/kgpe-d16/0007-southbridge-amd-sb700-Fix-boot-hang-on-ASUS-KGPE-D16.patch index a895479..0cac522 100644 --- a/resources/libreboot/patch/kgpe-d16/0005-southbridge-amd-sb700-Fix-boot-hang-on-ASUS-KGPE-D16.patch +++ b/resources/libreboot/patch/kgpe-d16/0007-southbridge-amd-sb700-Fix-boot-hang-on-ASUS-KGPE-D16.patch @@ -1,25 +1,25 @@ -From e897086a84f3b7c1af321e2a8a303cc49367b390 Mon Sep 17 00:00:00 2001 +From c95c41fbedceda4de85a076f8fc600c82106727c Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sat, 5 Sep 2015 17:46:15 -0500 -Subject: [PATCH 005/139] southbridge/amd/sb700: Fix boot hang on ASUS KGPE-D16 +Subject: [PATCH 007/143] southbridge/amd/sb700: Fix boot hang on ASUS + KGPE-D16 Change-Id: I1d7d6715663a13ab94fd6d71808e35f0f7384d00 Signed-off-by: Timothy Pearson --- - src/southbridge/amd/sb700/Kconfig | 4 + - src/southbridge/amd/sb700/acpi/ide.asl | 234 ++++++++++++++++++++++++++++++++ - src/southbridge/amd/sb700/acpi/sata.asl | 133 ++++++++++++++++++ - src/southbridge/amd/sb700/bootblock.c | 46 ++++++- - src/southbridge/amd/sb700/early_setup.c | 18 +++ - src/southbridge/amd/sb700/lpc.c | 3 + - src/southbridge/amd/sb700/sm.c | 21 +-- - src/southbridge/amd/sb700/smbus.h | 5 +- - 8 files changed, 447 insertions(+), 17 deletions(-) + src/southbridge/amd/sb700/Kconfig | 4 + + src/southbridge/amd/sb700/acpi/ide.asl | 234 +++++++++++++++++++++++++++++++ + src/southbridge/amd/sb700/acpi/sata.asl | 133 ++++++++++++++++++ + src/southbridge/amd/sb700/bootblock.c | 46 +++++- + src/southbridge/amd/sb700/early_setup.c | 18 +++ + src/southbridge/amd/sb700/lpc.c | 3 + + src/southbridge/amd/sb700/sm.c | 21 +-- + 7 files changed, 444 insertions(+), 15 deletions(-) create mode 100644 src/southbridge/amd/sb700/acpi/ide.asl create mode 100644 src/southbridge/amd/sb700/acpi/sata.asl diff --git a/src/southbridge/amd/sb700/Kconfig b/src/southbridge/amd/sb700/Kconfig -index a5dfe07..f56f84a 100644 +index 0761934..bca74fb 100644 --- a/src/southbridge/amd/sb700/Kconfig +++ b/src/southbridge/amd/sb700/Kconfig @@ -42,6 +42,10 @@ config SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT @@ -555,7 +555,7 @@ index a39ec18..0cc1e8b 100644 sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); dword = pci_read_config32(sm_dev, 0x64); diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c -index c216e1f..a4b78d0 100644 +index 598ebec..71253b5 100644 --- a/src/southbridge/amd/sb700/sm.c +++ b/src/southbridge/amd/sb700/sm.c @@ -2,6 +2,7 @@ @@ -566,7 +566,7 @@ index c216e1f..a4b78d0 100644 * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by -@@ -59,11 +60,8 @@ static void sm_init(device_t dev) +@@ -62,11 +63,8 @@ static void sm_init(device_t dev) printk(BIOS_INFO, "sm_init().\n"); rev = get_sb700_revision(dev); @@ -580,7 +580,7 @@ index c216e1f..a4b78d0 100644 /* 2.10 Interrupt Routing/Filtering */ dword = pci_read_config8(dev, 0x62); -@@ -129,9 +127,10 @@ static void sm_init(device_t dev) +@@ -132,9 +130,10 @@ static void sm_init(device_t dev) get_option(&on, "power_on_after_fail"); byte = pm_ioread(0x74); byte &= ~0x03; @@ -594,7 +594,7 @@ index c216e1f..a4b78d0 100644 byte |= 1 << 2; pm_iowrite(0x74, byte); printk(BIOS_INFO, "set power %s after power fail\n", on ? "on" : "off"); -@@ -295,6 +294,10 @@ static void sm_init(device_t dev) +@@ -298,6 +297,10 @@ static void sm_init(device_t dev) byte &= ~(1 << 1); pm_iowrite(0x59, byte); @@ -605,7 +605,7 @@ index c216e1f..a4b78d0 100644 printk(BIOS_INFO, "sm_init() end\n"); /* Enable NbSb virtual channel */ -@@ -385,7 +388,7 @@ static void sb700_sm_read_resources(device_t dev) +@@ -388,7 +391,7 @@ static void sb700_sm_read_resources(device_t dev) struct resource *res; /* Get the normal pci resources of this device */ @@ -614,29 +614,6 @@ index c216e1f..a4b78d0 100644 /* apic */ res = new_resource(dev, 0x74); -diff --git a/src/southbridge/amd/sb700/smbus.h b/src/southbridge/amd/sb700/smbus.h -index d223fe7..34b4098 100644 ---- a/src/southbridge/amd/sb700/smbus.h -+++ b/src/southbridge/amd/sb700/smbus.h -@@ -2,6 +2,7 @@ - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. -+ * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by -@@ -24,8 +25,8 @@ - #include "stddef.h" - #include - --#define SMBUS_IO_BASE 0x6000 /* Is it a temporary SMBus I/O base address? */ -- /*SIZE 0x40 */ -+#define SMBUS_IO_BASE 0xb00 -+#define SMBUS_AUX_IO_BASE 0xb20 - - #define SMBHSTSTAT 0x0 - #define SMBSLVSTAT 0x1 -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0006-southbridge-amd-sr5650-Fix-boot-failure-on-ASUS-KGPE.patch b/resources/libreboot/patch/kgpe-d16/0008-southbridge-amd-sr5650-Fix-boot-failure-on-ASUS-KGPE.patch index a0273e2..3b3da91 100644 --- a/resources/libreboot/patch/kgpe-d16/0006-southbridge-amd-sr5650-Fix-boot-failure-on-ASUS-KGPE.patch +++ b/resources/libreboot/patch/kgpe-d16/0008-southbridge-amd-sr5650-Fix-boot-failure-on-ASUS-KGPE.patch @@ -1,17 +1,17 @@ -From 03ff36542c8f8260b2ff7db5f41a16e9299a1bd0 Mon Sep 17 00:00:00 2001 +From ccebca23a1e58cc82d9e2d48642ee604ebbcd3b9 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sat, 5 Sep 2015 17:46:38 -0500 -Subject: [PATCH 006/139] southbridge/amd/sr5650: Fix boot failure on ASUS +Subject: [PATCH 008/143] southbridge/amd/sr5650: Fix boot failure on ASUS KGPE-D16 Change-Id: Ia13ba58118a826e830a4dc6e2378b76110fcabad Signed-off-by: Timothy Pearson --- - src/southbridge/amd/sr5650/acpi/sr5650.asl | 388 +++++++++++++++++++++++++++++ - src/southbridge/amd/sr5650/early_setup.c | 7 +- - src/southbridge/amd/sr5650/ht.c | 3 +- - src/southbridge/amd/sr5650/pcie.c | 37 ++- - src/southbridge/amd/sr5650/sr5650.c | 51 ++-- + src/southbridge/amd/sr5650/acpi/sr5650.asl | 388 ++++++++++++++++++++++++++++ + src/southbridge/amd/sr5650/early_setup.c | 7 +- + src/southbridge/amd/sr5650/ht.c | 3 +- + src/southbridge/amd/sr5650/pcie.c | 37 ++- + src/southbridge/amd/sr5650/sr5650.c | 51 ++-- 5 files changed, 456 insertions(+), 30 deletions(-) create mode 100644 src/southbridge/amd/sr5650/acpi/sr5650.asl @@ -617,5 +617,5 @@ index 441be66..75383de 100644 } -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0007-cpu-amd-Add-initial-support-for-AMD-Socket-G34-proce.patch b/resources/libreboot/patch/kgpe-d16/0009-cpu-amd-Add-initial-support-for-AMD-Socket-G34-proce.patch index 017295e..b66fdf3 100644 --- a/resources/libreboot/patch/kgpe-d16/0007-cpu-amd-Add-initial-support-for-AMD-Socket-G34-proce.patch +++ b/resources/libreboot/patch/kgpe-d16/0009-cpu-amd-Add-initial-support-for-AMD-Socket-G34-proce.patch @@ -1,26 +1,26 @@ -From 1c4603c0b0003dc41519ed8e03782ff6e1f9222f Mon Sep 17 00:00:00 2001 +From 9c3c40d0b53a338e7ed153b933155db1bc0cae08 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sat, 5 Sep 2015 17:50:29 -0500 -Subject: [PATCH 007/139] cpu/amd: Add initial support for AMD Socket G34 +Subject: [PATCH 009/143] cpu/amd: Add initial support for AMD Socket G34 processors Change-Id: Iccd034f32c26513edd52ca3a11a30f61c362682d Signed-off-by: Timothy Pearson --- - src/cpu/amd/Kconfig | 1 + - src/cpu/amd/Makefile.inc | 1 + - src/cpu/amd/car/post_cache_as_ram.c | 19 ++++- - src/cpu/amd/model_10xxx/init_cpus.c | 34 ++++++++- - src/cpu/amd/model_10xxx/model_10xxx_init.c | 2 + - src/cpu/amd/model_10xxx/processor_name.c | 23 +++++++ - src/cpu/amd/model_10xxx/ram_calc.c | 2 + - src/cpu/amd/quadcore/quadcore_id.c | 77 ++++++++++++++++----- - src/cpu/amd/socket_G34/Kconfig | 29 ++++++++ - src/cpu/amd/socket_G34/Makefile.inc | 14 ++++ - src/cpu/amd/socket_G34/socket_G34.c | 25 +++++++ - src/northbridge/amd/amdfam10/northbridge.c | 102 ++++++++++++++++++++++----- - src/northbridge/amd/amdht/ht_wrapper.c | 107 ++++++++++++++++++++++++++++- - src/northbridge/amd/amdht/ht_wrapper.h | 25 +++++++ + src/cpu/amd/Kconfig | 1 + + src/cpu/amd/Makefile.inc | 1 + + src/cpu/amd/car/post_cache_as_ram.c | 19 ++++- + src/cpu/amd/model_10xxx/init_cpus.c | 34 ++++++++- + src/cpu/amd/model_10xxx/model_10xxx_init.c | 2 + + src/cpu/amd/model_10xxx/processor_name.c | 23 ++++++ + src/cpu/amd/model_10xxx/ram_calc.c | 2 + + src/cpu/amd/quadcore/quadcore_id.c | 77 +++++++++++++++----- + src/cpu/amd/socket_G34/Kconfig | 29 ++++++++ + src/cpu/amd/socket_G34/Makefile.inc | 14 ++++ + src/cpu/amd/socket_G34/socket_G34.c | 25 +++++++ + src/northbridge/amd/amdfam10/northbridge.c | 102 +++++++++++++++++++++----- + src/northbridge/amd/amdht/ht_wrapper.c | 107 +++++++++++++++++++++++++++- + src/northbridge/amd/amdht/ht_wrapper.h | 25 +++++++ 14 files changed, 417 insertions(+), 44 deletions(-) create mode 100644 src/cpu/amd/socket_G34/Kconfig create mode 100644 src/cpu/amd/socket_G34/Makefile.inc @@ -828,5 +828,5 @@ index 0000000..3e9d957 + +#endif -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0008-northbridge-amd-amdmct-Fix-broken-AMD-K10-DDR3-memor.patch b/resources/libreboot/patch/kgpe-d16/0010-northbridge-amd-amdmct-Fix-broken-AMD-K10-DDR3-memor.patch index 75367b6..c3abdee 100644 --- a/resources/libreboot/patch/kgpe-d16/0008-northbridge-amd-amdmct-Fix-broken-AMD-K10-DDR3-memor.patch +++ b/resources/libreboot/patch/kgpe-d16/0010-northbridge-amd-amdmct-Fix-broken-AMD-K10-DDR3-memor.patch @@ -1,32 +1,32 @@ -From 2f8bf745a7ffc2e031efa0f60f993b88baf5a714 Mon Sep 17 00:00:00 2001 +From b79a652d746bc186b0de559aa237462e7ba09109 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sat, 5 Sep 2015 17:55:58 -0500 -Subject: [PATCH 008/139] northbridge/amd/amdmct: Fix broken AMD K10 DDR3 +Subject: [PATCH 010/143] northbridge/amd/amdmct: Fix broken AMD K10 DDR3 memory initalization Change-Id: Iab690db769e820600693ad1170085623b177b94e Signed-off-by: Timothy Pearson --- - src/northbridge/amd/amdfam10/raminit_amdmct.c | 2 + - src/northbridge/amd/amdmct/mct/mct_d.c | 1 - - src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 177 +++++- - src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 8 +- - src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h | 87 +-- - src/northbridge/amd/amdmct/mct_ddr3/mctardk6.c | 6 +- - src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 806 +++++++++++++----------- - src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c | 6 +- - src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c | 14 +- - src/northbridge/amd/amdmct/mct_ddr3/mctndi_d.c | 3 +- - src/northbridge/amd/amdmct/mct_ddr3/mctproc.c | 19 +- - src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c | 5 +- - src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 800 ++++++++++++----------- - src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c | 18 +- - src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c | 13 +- - src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c | 7 +- - src/northbridge/amd/amdmct/mct_ddr3/mctwl.c | 42 +- - src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c | 267 ++++---- - src/northbridge/amd/amdmct/wrappers/mcti_d.c | 112 +--- - 19 files changed, 1253 insertions(+), 1140 deletions(-) + src/northbridge/amd/amdfam10/raminit_amdmct.c | 2 + + src/northbridge/amd/amdmct/mct/mct_d.c | 1 - + src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 177 ++++- + src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 8 +- + src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h | 87 +-- + src/northbridge/amd/amdmct/mct_ddr3/mctardk6.c | 6 +- + src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 806 ++++++++++++----------- + src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c | 6 +- + src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c | 14 +- + src/northbridge/amd/amdmct/mct_ddr3/mctndi_d.c | 3 +- + src/northbridge/amd/amdmct/mct_ddr3/mctproc.c | 19 +- + src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c | 5 +- + src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 800 +++++++++++----------- + src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c | 18 +- + src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c | 13 +- + src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c | 7 +- + src/northbridge/amd/amdmct/mct_ddr3/mctwl.c | 42 +- + src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c | 267 ++++---- + src/northbridge/amd/amdmct/wrappers/mcti_d.c | 110 +--- + 19 files changed, 1252 insertions(+), 1139 deletions(-) diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c index a0d47f4..a585fae 100644 @@ -2916,7 +2916,7 @@ index cdeae49..1c3e322 100644 FreqChgCtrlWrd(pMCTstat, pDCTstat); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c -index 212a348..c76476b 100644 +index 212a348..67d705c 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c @@ -2,6 +2,7 @@ @@ -3008,7 +3008,7 @@ index 212a348..c76476b 100644 + if (wl) { + if (rank == 0) { + /* Get Rtt_WR for the current DIMM and rank */ -+ uint16_t dynamic_term = unbuffered_dimm_dynamic_termination_emrs(pDCTData->MaxDimmsInstalled, MemClkFreq, pDCTData->DimmRanks[currDimm], rank); ++ uint16_t dynamic_term = unbuffered_dimm_dynamic_termination_emrs(pDCTData->MaxDimmsInstalled, MemClkFreq, pDCTData->DimmRanks[dimm], rank); + + /* Convert dynamic termination code to corresponding nominal termination code */ + if (dynamic_term == 0x200) @@ -3050,10 +3050,10 @@ index 212a348..c76476b 100644 - } + tempW1 = 0x0; + } else { -+ tempW1 = unbuffered_dimm_nominal_termination_emrs(pDCTData->MaxDimmsInstalled, MemClkFreq, pDCTData->DimmRanks[currDimm], rank); ++ tempW1 = unbuffered_dimm_nominal_termination_emrs(pDCTData->MaxDimmsInstalled, MemClkFreq, pDCTData->DimmRanks[dimm], rank); } + } else { -+ tempW1 = unbuffered_dimm_nominal_termination_emrs(pDCTData->MaxDimmsInstalled, MemClkFreq, pDCTData->DimmRanks[currDimm], rank); ++ tempW1 = unbuffered_dimm_nominal_termination_emrs(pDCTData->MaxDimmsInstalled, MemClkFreq, pDCTData->DimmRanks[dimm], rank); } } tempW=tempW|tempW1; @@ -3301,18 +3301,9 @@ index 212a348..c76476b 100644 } diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c -index ea32893..6465e13 100644 +index ea32893..c00cf24 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c -@@ -49,7 +49,7 @@ static const uint16_t ddr3_limits[4] = {800, 666, 533, 400}; - static u16 mctGet_NVbits(u8 index) - { - u16 val = 0; -- int nvram; -+ int nvram = 0; - - switch (index) { - case NV_PACK_TYPE: @@ -59,6 +59,10 @@ static u16 mctGet_NVbits(u8 index) val = 1; #elif CONFIG_CPU_SOCKET_TYPE == 0x13 /* ASB2 */ @@ -3459,5 +3450,5 @@ index ea32893..6465e13 100644 vErratum414(pDCTstatA); } -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0011-northbridge-amd-amdfam10-Fix-typo-in-comment.patch b/resources/libreboot/patch/kgpe-d16/0011-northbridge-amd-amdfam10-Fix-typo-in-comment.patch deleted file mode 100644 index e28528b..0000000 --- a/resources/libreboot/patch/kgpe-d16/0011-northbridge-amd-amdfam10-Fix-typo-in-comment.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 72842e77d6207be18f86c8fbc3fc398808f4d69e Mon Sep 17 00:00:00 2001 -From: Timothy Pearson -Date: Sat, 5 Sep 2015 18:01:31 -0500 -Subject: [PATCH 011/139] northbridge/amd/amdfam10: Fix typo in comment - -Change-Id: I0a9b3a66231052622c862bae32b900f52f6efba9 -Signed-off-by: Timothy Pearson ---- - src/northbridge/amd/amdfam10/misc_control.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c -index e242e34..90a4db1 100644 ---- a/src/northbridge/amd/amdfam10/misc_control.c -+++ b/src/northbridge/amd/amdfam10/misc_control.c -@@ -47,7 +47,7 @@ - * The same trick can be used to augment legacy VGA resources which can - * be detect by generic pci reousrce allocator for VGA devices. - * BAD: it is more tricky than I think, the resource allocation code is -- * implemented in a way to NOT DOING legacy VGA resource allcation on -+ * implemented in a way to NOT DOING legacy VGA resource allocation on - * purpose :-(. - */ - static void mcf3_read_resources(device_t dev) --- -1.9.1 - diff --git a/resources/libreboot/patch/kgpe-d16/0009-northbridge-amd-amdmct-mct_ddr3-Fix-curly-brace-styl.patch b/resources/libreboot/patch/kgpe-d16/0011-northbridge-amd-amdmct-mct_ddr3-Fix-curly-brace-styl.patch index 877d6b0..df89fbc 100644 --- a/resources/libreboot/patch/kgpe-d16/0009-northbridge-amd-amdmct-mct_ddr3-Fix-curly-brace-styl.patch +++ b/resources/libreboot/patch/kgpe-d16/0011-northbridge-amd-amdmct-mct_ddr3-Fix-curly-brace-styl.patch @@ -1,17 +1,17 @@ -From 008cfb1a5e464a79af252b34086b1eb28d8b3420 Mon Sep 17 00:00:00 2001 +From 55eeaf44d331c7f42a7b03f22364d6a5a6febb47 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Tue, 8 Sep 2015 16:08:45 -0500 -Subject: [PATCH 009/139] northbridge/amd/amdmct/mct_ddr3: Fix curly brace +Subject: [PATCH 011/143] northbridge/amd/amdmct/mct_ddr3: Fix curly brace style violations Change-Id: Ic27d404a7ed76b58043037e8b66097db6d664501 Signed-off-by: Timothy Pearson --- - src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c | 37 ++++++++------------------- + src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c | 37 +++++++------------------ 1 file changed, 10 insertions(+), 27 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c -index c76476b..9f42d54 100644 +index 67d705c..397fd77 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c @@ -818,28 +818,19 @@ void setWLByteDelay(sDCTStruct *pDCTData, u8 ByteLane, u8 dimm, u8 targetAddr) @@ -91,5 +91,5 @@ index c76476b..9f42d54 100644 * We will then round the negative number to 0. */ -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0010-northbridge-amd-amdfam10-Limit-maximum-RAM-clock-to-.patch b/resources/libreboot/patch/kgpe-d16/0012-northbridge-amd-amdfam10-Limit-maximum-RAM-clock-to-.patch index d5a8941..95d7433 100644 --- a/resources/libreboot/patch/kgpe-d16/0010-northbridge-amd-amdfam10-Limit-maximum-RAM-clock-to-.patch +++ b/resources/libreboot/patch/kgpe-d16/0012-northbridge-amd-amdfam10-Limit-maximum-RAM-clock-to-.patch @@ -1,14 +1,14 @@ -From 5e830015eefae9024835e76c81715821a55b0853 Mon Sep 17 00:00:00 2001 +From 2eaf40d0574de0c971af14915222d604998d3636 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sat, 5 Sep 2015 18:00:27 -0500 -Subject: [PATCH 010/139] northbridge/amd/amdfam10: Limit maximum RAM clock to +Subject: [PATCH 012/143] northbridge/amd/amdfam10: Limit maximum RAM clock to BKDG recommendations Change-Id: I45eb03a4b351e458e8448245896743bd6fa57637 Signed-off-by: Timothy Pearson --- - src/northbridge/amd/amdfam10/raminit_amdmct.c | 46 +++++++++++++++++++++++---- - src/northbridge/amd/amdmct/wrappers/mcti_d.c | 2 +- + src/northbridge/amd/amdfam10/raminit_amdmct.c | 46 +++++++++++++++++++++---- + src/northbridge/amd/amdmct/wrappers/mcti_d.c | 2 +- 2 files changed, 41 insertions(+), 7 deletions(-) diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c @@ -104,7 +104,7 @@ index a585fae..3f33eba 100644 } +#endif diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c -index 6465e13..47260f2 100644 +index c00cf24..444adc5 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -322,7 +322,7 @@ static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat) @@ -117,5 +117,5 @@ index 6465e13..47260f2 100644 #ifdef UNUSED_CODE -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0012-device-hypertransport-Add-additional-debug-output.patch b/resources/libreboot/patch/kgpe-d16/0013-device-hypertransport-Add-additional-debug-output.patch index 61a3c56..f769827 100644 --- a/resources/libreboot/patch/kgpe-d16/0012-device-hypertransport-Add-additional-debug-output.patch +++ b/resources/libreboot/patch/kgpe-d16/0013-device-hypertransport-Add-additional-debug-output.patch @@ -1,12 +1,12 @@ -From 8791b352073e2738c7adfee154ffcab65ae6cdd6 Mon Sep 17 00:00:00 2001 +From e74e5090163511c5e7820cee396f407f292c6b32 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sat, 5 Sep 2015 18:06:52 -0500 -Subject: [PATCH 012/139] device/hypertransport: Add additional debug output +Subject: [PATCH 013/143] device/hypertransport: Add additional debug output Change-Id: I94b870f47581a4a2591d02eeb37627666e0f4297 Signed-off-by: Timothy Pearson --- - src/device/hypertransport.c | 3 +++ + src/device/hypertransport.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/device/hypertransport.c b/src/device/hypertransport.c @@ -31,5 +31,5 @@ index 07a320d..c76cb21 100644 #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0013-mainboard-asus-kgpe-d16-Add-initial-support-for-the-.patch b/resources/libreboot/patch/kgpe-d16/0014-mainboard-asus-kgpe-d16-Add-initial-support-for-the-.patch index 7dc753a..cd43042 100644 --- a/resources/libreboot/patch/kgpe-d16/0013-mainboard-asus-kgpe-d16-Add-initial-support-for-the-.patch +++ b/resources/libreboot/patch/kgpe-d16/0014-mainboard-asus-kgpe-d16-Add-initial-support-for-the-.patch @@ -1,7 +1,7 @@ -From 2515607768d1699c148a9eee0e40ccaeb8bb0650 Mon Sep 17 00:00:00 2001 +From 5392e9699f98451cb74a104f023ae31a6e049f7e Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Thu, 30 Apr 2015 01:47:31 -0500 -Subject: [PATCH 013/139] mainboard/asus/kgpe-d16: Add initial support for the +Subject: [PATCH 014/143] mainboard/asus/kgpe-d16: Add initial support for the KGPE-D16 As of this commit S3 suspend does not work on any K10 boards, @@ -10,25 +10,25 @@ including this board. Change-Id: Idd3971422fb2473bff7c60fe8d8161d6e20808ed Signed-off-by: Timothy Pearson --- - src/mainboard/asus/kgpe-d16/Kconfig | 95 ++++ - src/mainboard/asus/kgpe-d16/Kconfig.name | 2 + - src/mainboard/asus/kgpe-d16/acpi/pm_ctrl.asl | 367 ++++++++++++++ - src/mainboard/asus/kgpe-d16/acpi_tables.c | 75 +++ - src/mainboard/asus/kgpe-d16/board_info.txt | 5 + - src/mainboard/asus/kgpe-d16/bootblock.c | 52 ++ - src/mainboard/asus/kgpe-d16/cmos.default | 16 + - src/mainboard/asus/kgpe-d16/cmos.layout | 134 +++++ - src/mainboard/asus/kgpe-d16/devicetree.cb | 248 +++++++++ - src/mainboard/asus/kgpe-d16/dsdt.asl | 730 +++++++++++++++++++++++++++ - src/mainboard/asus/kgpe-d16/get_bus_conf.c | 128 +++++ - src/mainboard/asus/kgpe-d16/irq_tables.c | 112 ++++ - src/mainboard/asus/kgpe-d16/mainboard.c | 81 +++ - src/mainboard/asus/kgpe-d16/mb_sysconf.h | 44 ++ - src/mainboard/asus/kgpe-d16/mptable.c | 231 +++++++++ - src/mainboard/asus/kgpe-d16/resourcemap.c | 284 +++++++++++ - src/mainboard/asus/kgpe-d16/romstage.c | 422 ++++++++++++++++ - src/mainboard/asus/kgpe-d16/spd_notes.txt | 30 ++ - 18 files changed, 3056 insertions(+) + src/mainboard/asus/kgpe-d16/Kconfig | 95 ++++ + src/mainboard/asus/kgpe-d16/Kconfig.name | 2 + + src/mainboard/asus/kgpe-d16/acpi/pm_ctrl.asl | 367 +++++++++++++ + src/mainboard/asus/kgpe-d16/acpi_tables.c | 75 +++ + src/mainboard/asus/kgpe-d16/board_info.txt | 5 + + src/mainboard/asus/kgpe-d16/bootblock.c | 52 ++ + src/mainboard/asus/kgpe-d16/cmos.default | 16 + + src/mainboard/asus/kgpe-d16/cmos.layout | 134 +++++ + src/mainboard/asus/kgpe-d16/devicetree.cb | 249 +++++++++ + src/mainboard/asus/kgpe-d16/dsdt.asl | 730 ++++++++++++++++++++++++++ + src/mainboard/asus/kgpe-d16/get_bus_conf.c | 128 +++++ + src/mainboard/asus/kgpe-d16/irq_tables.c | 112 ++++ + src/mainboard/asus/kgpe-d16/mainboard.c | 81 +++ + src/mainboard/asus/kgpe-d16/mb_sysconf.h | 44 ++ + src/mainboard/asus/kgpe-d16/mptable.c | 231 ++++++++ + src/mainboard/asus/kgpe-d16/resourcemap.c | 284 ++++++++++ + src/mainboard/asus/kgpe-d16/romstage.c | 422 +++++++++++++++ + src/mainboard/asus/kgpe-d16/spd_notes.txt | 30 ++ + 18 files changed, 3057 insertions(+) create mode 100644 src/mainboard/asus/kgpe-d16/Kconfig create mode 100644 src/mainboard/asus/kgpe-d16/Kconfig.name create mode 100644 src/mainboard/asus/kgpe-d16/acpi/pm_ctrl.asl @@ -847,10 +847,10 @@ index 0000000..bcf9cd3 +checksum 392 983 984 diff --git a/src/mainboard/asus/kgpe-d16/devicetree.cb b/src/mainboard/asus/kgpe-d16/devicetree.cb new file mode 100644 -index 0000000..a172d89 +index 0000000..f4769fd --- /dev/null +++ b/src/mainboard/asus/kgpe-d16/devicetree.cb -@@ -0,0 +1,248 @@ +@@ -0,0 +1,249 @@ +chip northbridge/amd/amdfam10/root_complex # Root complex + device cpu_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_F_1207 # CPU socket @@ -908,48 +908,7 @@ index 0000000..a172d89 + device pci 13.0 on end # USB + device pci 13.1 on end # USB + device pci 13.2 on end # USB -+ device pci 14.0 on end # SM -+ device pci 14.1 on end # IDE 0x439c -+ device pci 14.2 off end # HDA 0x4383 (KGPE-D16 omits audio option) -+ device pci 14.3 on # LPC 0x439d (SMBUS primary controller) -+ chip superio/nuvoton/nct5572d # Super I/O -+ device pnp 2e.0 off end # FDC; Not available on the KGPE-D16 -+ device pnp 2e.1 off end # LPT1; Not available on the KGPE-D16 -+ device pnp 2e.2 on # Com1 -+ io 0x60 = 0x3f8 -+ irq 0x70 = 4 -+ end -+ device pnp 2e.3 off # IR: Not available on the KGPE-D16 -+ io 0x60 = 0x2f8 -+ irq 0x70 = 3 -+ end -+ device pnp 2e.5 on # PS/2 keyboard & mouse -+ io 0x60 = 0x60 -+ io 0x62 = 0x64 -+ irq 0x70 = 1 -+ irq 0x72 = 12 -+ end -+ device pnp 2e.6 off # CIR: Not available on the KGPE-D16 -+ io 0x60 = 0x100 -+ irq 0x70 = 0 -+ end -+ device pnp 2e.7 off end # GIPO689 -+ device pnp 2e.8 off end # WDT -+ device pnp 2e.9 off end # GPIO235 -+ device pnp 2e.a on end # ACPI -+ device pnp 2e.b on # HW Monitor -+ io 0x60 = 0x290 -+ io 0x62 = 0x0000 # SB-TSI currently not implemented -+ irq 0x70 = 5 -+ end -+ device pnp 2e.c off end # PECI -+ device pnp 2e.d off end # SUSLED -+ device pnp 2e.e off # CIRWKUP -+ io 0x60 = 0x0000 -+ irq 0x70 = 0 -+ end -+ device pnp 2e.f off end # GPIO_PP_OD -+ end ++ device pci 14.0 on # SM + chip drivers/generic/generic # DIMM n-0-0-0 + device i2c 50 on end + end @@ -1067,6 +1026,48 @@ index 0000000..a172d89 + device i2c 0x2f on end + end + end ++ device pci 14.1 on end # IDE 0x439c ++ device pci 14.2 off end # HDA 0x4383 (KGPE-D16 omits audio option) ++ device pci 14.3 on # LPC 0x439d (SMBUS primary controller) ++ chip superio/nuvoton/nct5572d # Super I/O ++ device pnp 2e.0 off end # FDC; Not available on the KGPE-D16 ++ device pnp 2e.1 off end # LPT1; Not available on the KGPE-D16 ++ device pnp 2e.2 on # Com1 ++ io 0x60 = 0x3f8 ++ irq 0x70 = 4 ++ end ++ device pnp 2e.3 off # IR: Not available on the KGPE-D16 ++ io 0x60 = 0x2f8 ++ irq 0x70 = 3 ++ end ++ device pnp 2e.5 on # PS/2 keyboard & mouse ++ io 0x60 = 0x60 ++ io 0x62 = 0x64 ++ irq 0x70 = 1 ++ irq 0x72 = 12 ++ end ++ device pnp 2e.6 off # CIR: Not available on the KGPE-D16 ++ io 0x60 = 0x100 ++ irq 0x70 = 0 ++ end ++ device pnp 2e.7 off end # GIPO689 ++ device pnp 2e.8 off end # WDT ++ device pnp 2e.9 off end # GPIO235 ++ device pnp 2e.a on end # ACPI ++ device pnp 2e.b on # HW Monitor ++ io 0x60 = 0x290 ++ io 0x62 = 0x0000 # SB-TSI currently not implemented ++ irq 0x70 = 5 ++ end ++ device pnp 2e.c off end # PECI ++ device pnp 2e.d off end # SUSLED ++ device pnp 2e.e off # CIRWKUP ++ io 0x60 = 0x0000 ++ irq 0x70 = 0 ++ end ++ device pnp 2e.f off end # GPIO_PP_OD ++ end ++ end + device pci 14.4 on # Bridge + device pci 1.0 on end # VGA + device pci 2.0 on end # FireWire @@ -3217,5 +3218,5 @@ index 0000000..623a88f +RECOVERY1 middle pin is connected to southbridge (AMD SP5100) GPIO 61 +Normal is HIGH, recovery is LOW. -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0014-mainboard-asus-kgpe-d16-Add-nvram-option-to-enable-d.patch b/resources/libreboot/patch/kgpe-d16/0015-mainboard-asus-kgpe-d16-Add-nvram-option-to-enable-d.patch index 073e2dc..7f431f5 100644 --- a/resources/libreboot/patch/kgpe-d16/0014-mainboard-asus-kgpe-d16-Add-nvram-option-to-enable-d.patch +++ b/resources/libreboot/patch/kgpe-d16/0015-mainboard-asus-kgpe-d16-Add-nvram-option-to-enable-d.patch @@ -1,15 +1,15 @@ -From 7137414550b7ef1d1f1d90e31c73eda392ab663d Mon Sep 17 00:00:00 2001 +From b6b068c466059602175a86a1fdbf3a0031c53387 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Tue, 11 Aug 2015 18:38:06 -0500 -Subject: [PATCH 014/139] mainboard/asus/kgpe-d16: Add nvram option to +Subject: [PATCH 015/143] mainboard/asus/kgpe-d16: Add nvram option to enable/disable the IEEE1394 controller Change-Id: I4f0f6c1cb1fad5b65f196dc6b443252a0ecc70a1 Signed-off-by: Timothy Pearson --- - src/mainboard/asus/kgpe-d16/cmos.default | 1 + - src/mainboard/asus/kgpe-d16/cmos.layout | 1 + - src/mainboard/asus/kgpe-d16/romstage.c | 21 +++++++++++++++++---- + src/mainboard/asus/kgpe-d16/cmos.default | 1 + + src/mainboard/asus/kgpe-d16/cmos.layout | 1 + + src/mainboard/asus/kgpe-d16/romstage.c | 21 +++++++++++++++++---- 3 files changed, 19 insertions(+), 4 deletions(-) diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default @@ -68,5 +68,5 @@ index 9964cfe..616fdfb 100644 /* Enable the RTC AltCentury register */ outb(0x41, 0xcd6); -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0015-cpu-amd-model_10xxx-Clean-up-debugging-statements.patch b/resources/libreboot/patch/kgpe-d16/0016-cpu-amd-model_10xxx-Clean-up-debugging-statements.patch index 1bf44c0..bd6a820 100644 --- a/resources/libreboot/patch/kgpe-d16/0015-cpu-amd-model_10xxx-Clean-up-debugging-statements.patch +++ b/resources/libreboot/patch/kgpe-d16/0016-cpu-amd-model_10xxx-Clean-up-debugging-statements.patch @@ -1,27 +1,19 @@ -From 158141bedc473c21a11918605dc7e76eee0c43e5 Mon Sep 17 00:00:00 2001 +From 51e23836f586c79d63ca402bad738bd7a4149572 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sat, 5 Sep 2015 18:46:54 -0500 -Subject: [PATCH 015/139] cpu/amd/model_10xxx: Clean up debugging statements +Subject: [PATCH 016/143] cpu/amd/model_10xxx: Clean up debugging statements Change-Id: I6dff74b3857e1fb384aefc87b44e7679bd4aab07 Signed-off-by: Timothy Pearson --- - src/cpu/amd/model_10xxx/fidvid.c | 43 ++++++++++++++++++++-------------------- - 1 file changed, 21 insertions(+), 22 deletions(-) + src/cpu/amd/model_10xxx/fidvid.c | 42 ++++++++++++++++++-------------------- + 1 file changed, 20 insertions(+), 22 deletions(-) diff --git a/src/cpu/amd/model_10xxx/fidvid.c b/src/cpu/amd/model_10xxx/fidvid.c -index 36bdf36..99ffcc8 100644 +index 36bdf36..5b1c581 100644 --- a/src/cpu/amd/model_10xxx/fidvid.c +++ b/src/cpu/amd/model_10xxx/fidvid.c -@@ -2,6 +2,7 @@ - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. -+ * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by -@@ -460,35 +461,35 @@ static void config_clk_power_ctrl_reg0(int node, u32 cpuRev, u8 procPkg) { +@@ -460,35 +460,35 @@ static void config_clk_power_ctrl_reg0(int node, u32 cpuRev, u8 procPkg) { static void config_power_ctrl_misc_reg(device_t dev,u32 cpuRev, u8 procPkg) { /* check PVI/SVI */ @@ -69,7 +61,7 @@ index 36bdf36..99ffcc8 100644 } static void config_nb_syn_ptr_adj(device_t dev, u32 cpuRev) { -@@ -581,7 +582,7 @@ static void prep_fid_change(void) +@@ -581,7 +581,7 @@ static void prep_fid_change(void) nodes = get_nodes(); for (i = 0; i < nodes; i++) { @@ -78,7 +70,7 @@ index 36bdf36..99ffcc8 100644 dev = NODE_PCI(i, 3); u32 cpuRev = mctGetLogicalCPUID(0xFF) ; u8 procPkg = mctGetProcessorPackageType(); -@@ -591,25 +592,23 @@ static void prep_fid_change(void) +@@ -591,25 +591,23 @@ static void prep_fid_change(void) /* Figure out the value for VsSlamTime and program it */ recalculateVsSlamTimeSettingOnCorePre(dev); @@ -112,5 +104,5 @@ index 36bdf36..99ffcc8 100644 } -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0016-southbridge-amd-sb700-Add-Suspend-to-RAM-S3-support.patch b/resources/libreboot/patch/kgpe-d16/0017-southbridge-amd-sb700-Add-Suspend-to-RAM-S3-support.patch index 446d1e8..1ebc523 100644 --- a/resources/libreboot/patch/kgpe-d16/0016-southbridge-amd-sb700-Add-Suspend-to-RAM-S3-support.patch +++ b/resources/libreboot/patch/kgpe-d16/0017-southbridge-amd-sb700-Add-Suspend-to-RAM-S3-support.patch @@ -1,19 +1,19 @@ -From 4e9327a08f16505bbcdeb49592ded51873a4d62f Mon Sep 17 00:00:00 2001 +From da02322d4086f1f391e2e4354b41c6b7056fc5d2 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sat, 5 Sep 2015 18:14:25 -0500 -Subject: [PATCH 016/139] southbridge/amd/sb700: Add Suspend to RAM (S3) +Subject: [PATCH 017/143] southbridge/amd/sb700: Add Suspend to RAM (S3) support Change-Id: Ic643e31b721f11a90d8fb5f8c8f8a3b7892c0d73 Signed-off-by: Timothy Pearson --- - src/southbridge/amd/sb700/Makefile.inc | 1 + - src/southbridge/amd/sb700/bootblock.c | 4 +- - src/southbridge/amd/sb700/early_setup.c | 39 +++++++-- - src/southbridge/amd/sb700/lpc.c | 12 ++- - src/southbridge/amd/sb700/sb700.h | 3 + - src/southbridge/amd/sb700/spi.c | 148 ++++++++++++++++++++++++++++++++ - src/southbridge/amd/sb700/spi.h | 21 +++++ + src/southbridge/amd/sb700/Makefile.inc | 1 + + src/southbridge/amd/sb700/bootblock.c | 4 +- + src/southbridge/amd/sb700/early_setup.c | 39 ++++++-- + src/southbridge/amd/sb700/lpc.c | 12 ++- + src/southbridge/amd/sb700/sb700.h | 3 + + src/southbridge/amd/sb700/spi.c | 148 +++++++++++++++++++++++++++++++ + src/southbridge/amd/sb700/spi.h | 21 +++++ 7 files changed, 216 insertions(+), 12 deletions(-) create mode 100644 src/southbridge/amd/sb700/spi.c create mode 100644 src/southbridge/amd/sb700/spi.h @@ -363,5 +363,5 @@ index 0000000..9b76b35 +void spi_release_bus(struct spi_slave *slave); \ No newline at end of file -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0017-superio-nuvoton-nct5572d-Enable-power-state-after-po.patch b/resources/libreboot/patch/kgpe-d16/0018-superio-nuvoton-nct5572d-Enable-power-state-after-po.patch index e7ce695..61abd52 100644 --- a/resources/libreboot/patch/kgpe-d16/0017-superio-nuvoton-nct5572d-Enable-power-state-after-po.patch +++ b/resources/libreboot/patch/kgpe-d16/0018-superio-nuvoton-nct5572d-Enable-power-state-after-po.patch @@ -1,17 +1,17 @@ -From d09d475241b1017919ac2048177ce5ab60f7328f Mon Sep 17 00:00:00 2001 +From e2c23ef578b911c1fe91b582c5c26a2b1e6fcaca Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sat, 5 Sep 2015 18:26:30 -0500 -Subject: [PATCH 017/139] superio/nuvoton/nct5572d: Enable power state after +Subject: [PATCH 018/143] superio/nuvoton/nct5572d: Enable power state after power failure support Change-Id: Ia0313b9ecd64c9e6f99a140772ebb35abe0175fd Signed-off-by: Timothy Pearson --- - src/superio/nuvoton/nct5572d/superio.c | 31 +++++++++++++++++++++++++++++++ - 1 file changed, 31 insertions(+) + src/superio/nuvoton/nct5572d/superio.c | 29 +++++++++++++++++++++++++++++ + 1 file changed, 29 insertions(+) diff --git a/src/superio/nuvoton/nct5572d/superio.c b/src/superio/nuvoton/nct5572d/superio.c -index c5278d6..ccf2416 100644 +index c5278d6..3b71c6b 100644 --- a/src/superio/nuvoton/nct5572d/superio.c +++ b/src/superio/nuvoton/nct5572d/superio.c @@ -3,6 +3,7 @@ @@ -47,12 +47,12 @@ index c5278d6..ccf2416 100644 static void nct5572d_init(struct device *dev) { + uint8_t byte; -+ uint32_t power_status; ++ uint8_t power_status; + if (!dev->enabled) return; -@@ -38,6 +51,24 @@ static void nct5572d_init(struct device *dev) +@@ -38,6 +51,22 @@ static void nct5572d_init(struct device *dev) case NCT5572D_KBC: pc_keyboard_init(); break; @@ -61,16 +61,14 @@ index c5278d6..ccf2416 100644 + power_status = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + get_option(&power_status, "power_on_after_fail"); + pnp_enter_conf_mode_8787(dev); -+ outb(0x07, dev->path.pnp.port); -+ outb(NCT5572D_ACPI, dev->path.pnp.port+1); /* ACPI function */ -+ outb(0xe4, dev->path.pnp.port); /* CRE4 */ -+ byte = inb(dev->path.pnp.port+1); ++ pnp_set_logical_device(dev); ++ byte = pnp_read_config(dev, 0xe4); + byte &= ~0x60; + if (power_status == 1) + byte |= (0x1 << 5); /* Force power on */ + else if (power_status == 2) + byte |= (0x2 << 5); /* Use last power state */ -+ outb(byte, dev->path.pnp.port+1); ++ pnp_write_config(dev, 0xe4, byte); + pnp_exit_conf_mode_aa(dev); + printk(BIOS_INFO, "set power %s after power fail\n", power_status ? "on" : "off"); + break; @@ -78,5 +76,5 @@ index c5278d6..ccf2416 100644 } -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0019-mainboard-asrock-e350m1-Update-CMOS-layout-to-match-.patch b/resources/libreboot/patch/kgpe-d16/0019-mainboard-asrock-e350m1-Update-CMOS-layout-to-match-.patch new file mode 100644 index 0000000..d4b20fe --- /dev/null +++ b/resources/libreboot/patch/kgpe-d16/0019-mainboard-asrock-e350m1-Update-CMOS-layout-to-match-.patch @@ -0,0 +1,38 @@ +From 8249f770fd166cc1ce8d6c033c01103d36763977 Mon Sep 17 00:00:00 2001 +From: Timothy Pearson +Date: Wed, 21 Oct 2015 15:27:02 -0500 +Subject: [PATCH 019/143] mainboard/asrock/e350m1: Update CMOS layout to match + SIO changes + +Change-Id: I3f1f33b50f788b6d57f1a7986c4bdb912426e4f0 +Signed-off-by: Timothy Pearson +--- + src/mainboard/asrock/e350m1/cmos.layout | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +diff --git a/src/mainboard/asrock/e350m1/cmos.layout b/src/mainboard/asrock/e350m1/cmos.layout +index 996160e..bc8de75 100644 +--- a/src/mainboard/asrock/e350m1/cmos.layout ++++ b/src/mainboard/asrock/e350m1/cmos.layout +@@ -29,7 +29,7 @@ entries + 396 1 e 1 interleave_chip_selects + 397 2 e 8 max_mem_clock + 399 1 e 2 multi_core +-400 1 e 1 power_on_after_fail ++400 2 e 3 power_on_after_fail + 412 4 e 6 debug_level + 440 4 e 9 slow_cpu + 444 1 e 1 nmi +@@ -49,6 +49,9 @@ enumerations + 1 1 Enable + 2 0 Enable + 2 1 Disable ++3 0 Off ++3 1 On ++3 2 Last + 4 0 Fallback + 4 1 Normal + 5 0 115200 +-- +1.7.9.5 + diff --git a/resources/libreboot/patch/kgpe-d16/0018-northbridge-amd-amdfam10-Add-Suspend-to-RAM-S3-Flash.patch b/resources/libreboot/patch/kgpe-d16/0020-northbridge-amd-amdfam10-Add-Suspend-to-RAM-S3-Flash.patch index 0fac423..31f37ec 100644 --- a/resources/libreboot/patch/kgpe-d16/0018-northbridge-amd-amdfam10-Add-Suspend-to-RAM-S3-Flash.patch +++ b/resources/libreboot/patch/kgpe-d16/0020-northbridge-amd-amdfam10-Add-Suspend-to-RAM-S3-Flash.patch @@ -1,15 +1,15 @@ -From 38e3b0862f6e914b010c004ff03cb9063452e26c Mon Sep 17 00:00:00 2001 +From 41778c7eef84c582216fd517274b55637bb3bbc3 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sat, 5 Sep 2015 18:39:34 -0500 -Subject: [PATCH 018/139] northbridge/amd/amdfam10: Add Suspend to RAM (S3) +Subject: [PATCH 020/143] northbridge/amd/amdfam10: Add Suspend to RAM (S3) Flash data storage area Change-Id: I169fafc3a61e11c3e4781190053e57bf34502d7b Signed-off-by: Timothy Pearson --- - src/northbridge/amd/amdfam10/Kconfig | 6 ++++ - src/northbridge/amd/amdfam10/Makefile.inc | 19 ++++++++++ - src/northbridge/amd/amdfam10/raminit_amdmct.c | 50 +++++++++++++++------------ + src/northbridge/amd/amdfam10/Kconfig | 6 +++ + src/northbridge/amd/amdfam10/Makefile.inc | 19 ++++++++++ + src/northbridge/amd/amdfam10/raminit_amdmct.c | 50 ++++++++++++++----------- 3 files changed, 53 insertions(+), 22 deletions(-) diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig @@ -131,5 +131,5 @@ index 3f33eba..5068e7a 100644 } #endif -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0019-northbridge-amd-amdmct-mct_ddr3-Add-initial-Suspend-.patch b/resources/libreboot/patch/kgpe-d16/0021-northbridge-amd-amdmct-mct_ddr3-Add-initial-Suspend-.patch index 482bedb..65315b4 100644 --- a/resources/libreboot/patch/kgpe-d16/0019-northbridge-amd-amdmct-mct_ddr3-Add-initial-Suspend-.patch +++ b/resources/libreboot/patch/kgpe-d16/0021-northbridge-amd-amdmct-mct_ddr3-Add-initial-Suspend-.patch @@ -1,23 +1,23 @@ -From b1e36a17d254e15459729ebfc3a83df4a2b28468 Mon Sep 17 00:00:00 2001 +From e0f5bb37ad0aacb69044c70bb61483cb1df72d08 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sat, 5 Sep 2015 18:40:31 -0500 -Subject: [PATCH 019/139] northbridge/amd/amdmct/mct_ddr3: Add initial Suspend +Subject: [PATCH 021/143] northbridge/amd/amdmct/mct_ddr3: Add initial Suspend to RAM (S3) support Change-Id: Ic97567851fa40295bc21cefd7537407b99d71709 Signed-off-by: Timothy Pearson --- - src/northbridge/amd/amdfam10/northbridge.c | 8 + - src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 154 ++++--- - src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 112 +++++ - src/northbridge/amd/amdmct/mct_ddr3/s3utils.c | 610 ++++++++++++++++++++++++++ - src/northbridge/amd/amdmct/mct_ddr3/s3utils.h | 28 ++ - 5 files changed, 840 insertions(+), 72 deletions(-) + src/northbridge/amd/amdfam10/northbridge.c | 8 + + src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 154 +++--- + src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 112 +++++ + src/northbridge/amd/amdmct/mct_ddr3/s3utils.c | 620 +++++++++++++++++++++++++ + src/northbridge/amd/amdmct/mct_ddr3/s3utils.h | 28 ++ + 5 files changed, 850 insertions(+), 72 deletions(-) create mode 100644 src/northbridge/amd/amdmct/mct_ddr3/s3utils.c create mode 100644 src/northbridge/amd/amdmct/mct_ddr3/s3utils.h diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c -index 74cecc8..9cc3d96 100644 +index 74cecc8..d4fe986 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -54,6 +54,10 @@ @@ -35,7 +35,7 @@ index 74cecc8..9cc3d96 100644 /* Do not delay UMA setup, as a device on the PCI bus may evaluate the global uma_memory variables already in its enable function. */ if (!done) { -+#if IS_ENABLED(CONFIG_DIMM_DDR3) ++#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && IS_ENABLED(CONFIG_DIMM_DDR3) + save_mct_information_to_nvram(); +#endif + @@ -352,10 +352,10 @@ index 219aa42..c790d7e 100644 ===============================================================================*/ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c new file mode 100644 -index 0000000..78523e8 +index 0000000..a49499f --- /dev/null +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c -@@ -0,0 +1,610 @@ +@@ -0,0 +1,620 @@ +/* + * This file is part of the coreboot project. + * @@ -950,7 +950,9 @@ index 0000000..78523e8 +int8_t restore_mct_information_from_nvram(void) +{ + ssize_t s3nv_offset; -+ struct amd_s3_persistent_data persistent_data; ++ ssize_t s3nv_file_offset; ++ void * s3nv_cbfs_file_ptr; ++ struct amd_s3_persistent_data *persistent_data; + + /* Obtain CBFS file offset */ + s3nv_offset = get_s3nv_file_offset(); @@ -958,11 +960,19 @@ index 0000000..78523e8 + return -1; + + /* Align flash pointer to nearest boundary */ ++ s3nv_file_offset = s3nv_offset; + s3nv_offset &= ~(CONFIG_S3_DATA_SIZE-1); + s3nv_offset += CONFIG_S3_DATA_SIZE; ++ s3nv_file_offset = s3nv_offset - s3nv_file_offset; + -+ cbfs_read(CBFS_DEFAULT_MEDIA, &persistent_data, s3nv_offset, sizeof(struct amd_s3_persistent_data)); -+ restore_mct_data_from_save_variable(&persistent_data); ++ /* Map data structure in CBFS and restore settings */ ++ s3nv_cbfs_file_ptr = cbfs_boot_map_with_leak(S3NV_FILE_NAME, CBFS_TYPE_RAW, NULL); ++ if (!s3nv_cbfs_file_ptr) { ++ printk(BIOS_DEBUG, "S3 state file could not be mapped: %s\n", S3NV_FILE_NAME); ++ return -1; ++ } ++ persistent_data = (s3nv_cbfs_file_ptr + s3nv_file_offset); ++ restore_mct_data_from_save_variable(persistent_data); + + return 0; +} @@ -1003,5 +1013,5 @@ index 0000000..dcddcad +void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persistent_data); \ No newline at end of file -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0020-cpu-amd-car-Add-initial-Suspend-to-RAM-S3-support.patch b/resources/libreboot/patch/kgpe-d16/0022-cpu-amd-car-Add-initial-Suspend-to-RAM-S3-support.patch index 672a21f..3afb5d5 100644 --- a/resources/libreboot/patch/kgpe-d16/0020-cpu-amd-car-Add-initial-Suspend-to-RAM-S3-support.patch +++ b/resources/libreboot/patch/kgpe-d16/0022-cpu-amd-car-Add-initial-Suspend-to-RAM-S3-support.patch @@ -1,12 +1,12 @@ -From 043f3abb58733fe14feb7cca5c2101f6a905aeb8 Mon Sep 17 00:00:00 2001 +From 9731b8e1e997c083bb2084085fb6d4c46d96910f Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sat, 5 Sep 2015 18:46:24 -0500 -Subject: [PATCH 020/139] cpu/amd/car: Add initial Suspend to RAM (S3) support +Subject: [PATCH 022/143] cpu/amd/car: Add initial Suspend to RAM (S3) support Change-Id: I1e1a67fa3c2c13cebcf8f0af318055b9d97d0a59 Signed-off-by: Timothy Pearson --- - src/cpu/amd/car/post_cache_as_ram.c | 12 ++++++++++++ + src/cpu/amd/car/post_cache_as_ram.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c @@ -52,5 +52,5 @@ index 230d1aa..e265de1 100644 prepare_ramstage_region(resume_backup_memory); -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0021-mainboard-asus-kgpe-d16-Add-initial-Suspend-to-RAM-S.patch b/resources/libreboot/patch/kgpe-d16/0023-mainboard-asus-kgpe-d16-Add-initial-Suspend-to-RAM-S.patch index 83ee459..7aaeceb 100644 --- a/resources/libreboot/patch/kgpe-d16/0021-mainboard-asus-kgpe-d16-Add-initial-Suspend-to-RAM-S.patch +++ b/resources/libreboot/patch/kgpe-d16/0023-mainboard-asus-kgpe-d16-Add-initial-Suspend-to-RAM-S.patch @@ -1,17 +1,17 @@ -From 65fa0d700672fcc4556f0d3300912e336a727d87 Mon Sep 17 00:00:00 2001 +From dbbc7efacaeec510163ef0f0f802ab75cca8d94e Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Thu, 7 May 2015 01:32:08 -0500 -Subject: [PATCH 021/139] mainboard/asus/kgpe-d16: Add initial Suspend to RAM +Subject: [PATCH 023/143] mainboard/asus/kgpe-d16: Add initial Suspend to RAM (S3) support Change-Id: I7da84b064287a445fd75a947e2f96ce1ae30d3de Signed-off-by: Timothy Pearson --- - src/mainboard/asus/kgpe-d16/Kconfig | 3 + - src/mainboard/asus/kgpe-d16/acpi/pm_ctrl.asl | 639 ++++++++++++++------------- - src/mainboard/asus/kgpe-d16/dsdt.asl | 5 +- - src/mainboard/asus/kgpe-d16/romstage.c | 34 +- - src/mainboard/asus/kgpe-d16/spd_notes.txt | 16 + + src/mainboard/asus/kgpe-d16/Kconfig | 3 + + src/mainboard/asus/kgpe-d16/acpi/pm_ctrl.asl | 639 +++++++++++++------------- + src/mainboard/asus/kgpe-d16/dsdt.asl | 5 +- + src/mainboard/asus/kgpe-d16/romstage.c | 34 +- + src/mainboard/asus/kgpe-d16/spd_notes.txt | 16 + 5 files changed, 369 insertions(+), 328 deletions(-) diff --git a/src/mainboard/asus/kgpe-d16/Kconfig b/src/mainboard/asus/kgpe-d16/Kconfig @@ -828,5 +828,5 @@ index 623a88f..ddd5cc8 100644 +Setting SuperIO LDN 9 CRF4 bits 1 or 0 (or both) to 0 disables NICB. \ No newline at end of file -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0022-include-smbios-Update-SMBIOS-memory-structures-to-ve.patch b/resources/libreboot/patch/kgpe-d16/0024-include-smbios-Update-SMBIOS-memory-structures-to-ve.patch index debb88e..bdb2752 100644 --- a/resources/libreboot/patch/kgpe-d16/0022-include-smbios-Update-SMBIOS-memory-structures-to-ve.patch +++ b/resources/libreboot/patch/kgpe-d16/0024-include-smbios-Update-SMBIOS-memory-structures-to-ve.patch @@ -1,13 +1,13 @@ -From ec5844dce6ad1a2c1528ea7cb6f41f408fd48a4f Mon Sep 17 00:00:00 2001 +From aef05f58a4a6f2760a93cb645dbf7bc85225837a Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sat, 5 Sep 2015 19:00:34 -0500 -Subject: [PATCH 022/139] include/smbios: Update SMBIOS memory structures to +Subject: [PATCH 024/143] include/smbios: Update SMBIOS memory structures to version 2.8 Change-Id: Icda915933c4ebf3a735d9e1d4e4dbb1138a06b39 Signed-off-by: Timothy Pearson --- - src/include/smbios.h | 6 ++++-- + src/include/smbios.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/include/smbios.h b/src/include/smbios.h @@ -29,5 +29,5 @@ index b654c23..fdb7bbd 100644 } __attribute__((packed)); -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0023-northbridge-amd-amdfam10-Set-DIMM-voltage-based-on-S.patch b/resources/libreboot/patch/kgpe-d16/0025-northbridge-amd-amdfam10-Set-DIMM-voltage-based-on-S.patch index 0867c83..917a36d 100644 --- a/resources/libreboot/patch/kgpe-d16/0023-northbridge-amd-amdfam10-Set-DIMM-voltage-based-on-S.patch +++ b/resources/libreboot/patch/kgpe-d16/0025-northbridge-amd-amdfam10-Set-DIMM-voltage-based-on-S.patch @@ -1,17 +1,17 @@ -From 4cc0cdf4b04ba705d302a60a7f5905c17fe9bffe Mon Sep 17 00:00:00 2001 +From e6a4307e156538ca120f68d281f5237cb50f8456 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sat, 5 Sep 2015 18:56:05 -0500 -Subject: [PATCH 023/139] northbridge/amd/amdfam10: Set DIMM voltage based on +Subject: [PATCH 025/143] northbridge/amd/amdfam10: Set DIMM voltage based on SPD data Change-Id: I67a76cf0e4ebc33fbd7dd151bb68dce1fc6ba680 Signed-off-by: Timothy Pearson --- - src/northbridge/amd/amdfam10/Kconfig | 4 ++ - src/northbridge/amd/amdfam10/acpi.c | 3 +- - src/northbridge/amd/amdfam10/northbridge.c | 75 ++++++++++++++++++++++++----- - src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 8 +++ - src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 6 +++ + src/northbridge/amd/amdfam10/Kconfig | 4 ++ + src/northbridge/amd/amdfam10/acpi.c | 3 +- + src/northbridge/amd/amdfam10/northbridge.c | 75 ++++++++++++++++++++++----- + src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 8 +++ + src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 6 +++ 5 files changed, 81 insertions(+), 15 deletions(-) diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig @@ -44,7 +44,7 @@ index 4b86e96..92433bb 100644 } } diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c -index 9cc3d96..3b302e8 100644 +index d4fe986..ff324cd 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -950,19 +950,38 @@ static int amdfam10_get_smbios_data16(int* count, int handle, unsigned long *cur @@ -194,5 +194,5 @@ index c790d7e..a947c2d 100644 void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); void InterleaveChannels_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0025-src-console-Add-x86-romstage-spinlock-option.patch b/resources/libreboot/patch/kgpe-d16/0025-src-console-Add-x86-romstage-spinlock-option.patch deleted file mode 100644 index 2f8ef7f..0000000 --- a/resources/libreboot/patch/kgpe-d16/0025-src-console-Add-x86-romstage-spinlock-option.patch +++ /dev/null @@ -1,100 +0,0 @@ -From 2eced49516682afa1c56ac1e83a8f4260d4dec2a Mon Sep 17 00:00:00 2001 -From: Timothy Pearson -Date: Mon, 18 May 2015 16:04:10 -0500 -Subject: [PATCH 025/139] src/console: Add x86 romstage spinlock option - -Change-Id: Ice42a0d3177736bf6e1bc601092e413601866f20 -Signed-off-by: Timothy Pearson ---- - src/arch/x86/include/arch/smp/spinlock.h | 10 +++++++++- - src/console/printk.c | 19 +++++++++++++++++++ - 2 files changed, 28 insertions(+), 1 deletion(-) - -diff --git a/src/arch/x86/include/arch/smp/spinlock.h b/src/arch/x86/include/arch/smp/spinlock.h -index 32be2f2..a5904c7 100644 ---- a/src/arch/x86/include/arch/smp/spinlock.h -+++ b/src/arch/x86/include/arch/smp/spinlock.h -@@ -1,7 +1,7 @@ - #ifndef ARCH_SMP_SPINLOCK_H - #define ARCH_SMP_SPINLOCK_H - --#ifndef __PRE_RAM__ -+#if !defined(__PRE_RAM__) || defined(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) - - /* - * Your basic SMP spinlocks, allowing only a single CPU anywhere -@@ -11,9 +11,17 @@ typedef struct { - volatile unsigned int lock; - } spinlock_t; - -+#ifdef __PRE_RAM__ -+spinlock_t* romstage_console_lock(void); -+#endif - - #define SPIN_LOCK_UNLOCKED (spinlock_t) { 1 } -+ -+#ifndef __PRE_RAM__ - #define DECLARE_SPIN_LOCK(x) static spinlock_t x = SPIN_LOCK_UNLOCKED; -+#else -+#define DECLARE_SPIN_LOCK(x) -+#endif - - /* - * Simple spin lock operations. There are two variants, one clears IRQ's -diff --git a/src/console/printk.c b/src/console/printk.c -index aab7ff5..2aae980 100644 ---- a/src/console/printk.c -+++ b/src/console/printk.c -@@ -2,6 +2,7 @@ - * blatantly copied from linux/kernel/printk.c - * - * Copyright (C) 1991, 1992 Linus Torvalds -+ * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - */ - -@@ -13,7 +14,13 @@ - #include - #include - -+#if defined(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) -+#ifndef __PRE_RAM__ - DECLARE_SPIN_LOCK(console_lock) -+#endif -+#else -+DECLARE_SPIN_LOCK(console_lock) -+#endif - - void do_putchar(unsigned char byte) - { -@@ -39,7 +46,13 @@ int do_printk(int msg_level, const char *fmt, ...) - #endif - - DISABLE_TRACE; -+#ifdef __PRE_RAM__ -+#ifdef CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK -+ spin_lock(romstage_console_lock()); -+#endif -+#else - spin_lock(&console_lock); -+#endif - - va_start(args, fmt); - i = vtxprintf(wrap_putchar, fmt, args, NULL); -@@ -47,7 +60,13 @@ int do_printk(int msg_level, const char *fmt, ...) - - console_tx_flush(); - -+#ifdef __PRE_RAM__ -+#ifdef CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK -+ spin_unlock(romstage_console_lock()); -+#endif -+#else - spin_unlock(&console_lock); -+#endif - ENABLE_TRACE; - - return i; --- -1.9.1 - diff --git a/resources/libreboot/patch/kgpe-d16/0024-mainboard-asus-kgpe-d16-Set-DDR3-memory-voltage-base.patch b/resources/libreboot/patch/kgpe-d16/0026-mainboard-asus-kgpe-d16-Set-DDR3-memory-voltage-base.patch index 059aefc..9d6ebc8 100644 --- a/resources/libreboot/patch/kgpe-d16/0024-mainboard-asus-kgpe-d16-Set-DDR3-memory-voltage-base.patch +++ b/resources/libreboot/patch/kgpe-d16/0026-mainboard-asus-kgpe-d16-Set-DDR3-memory-voltage-base.patch @@ -1,16 +1,16 @@ -From 7cc2167cf68f778b06a3defcb42b6b9ebdbce2e5 Mon Sep 17 00:00:00 2001 +From 7b1479a41c0fd5741f03fff5ce6ed3676f41b4dc Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sun, 10 May 2015 04:37:56 -0500 -Subject: [PATCH 024/139] mainboard/asus/kgpe-d16: Set DDR3 memory voltage +Subject: [PATCH 026/143] mainboard/asus/kgpe-d16: Set DDR3 memory voltage based on SPD data Change-Id: I21777283ce0fd3c607951204a63ff67dc656c8cc Signed-off-by: Timothy Pearson --- - src/mainboard/asus/kgpe-d16/Kconfig | 1 + - src/mainboard/asus/kgpe-d16/cmos.default | 1 + - src/mainboard/asus/kgpe-d16/cmos.layout | 5 +++ - src/mainboard/asus/kgpe-d16/romstage.c | 76 +++++++++++++++++++++++++++++--- + src/mainboard/asus/kgpe-d16/Kconfig | 1 + + src/mainboard/asus/kgpe-d16/cmos.default | 1 + + src/mainboard/asus/kgpe-d16/cmos.layout | 5 ++ + src/mainboard/asus/kgpe-d16/romstage.c | 76 ++++++++++++++++++++++++++++-- 4 files changed, 78 insertions(+), 5 deletions(-) diff --git a/src/mainboard/asus/kgpe-d16/Kconfig b/src/mainboard/asus/kgpe-d16/Kconfig @@ -162,5 +162,5 @@ index 3431bab..18e7c16 100644 set_lpc_sticky_ctl(1); /* Retain LPC/IMC GPIO configuration during S3 sleep */ if (!s3resume) { /* Avoid supply voltage glitches while the DIMMs are retaining data */ -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0027-northbridge-amd-amdmct-mct_ddr3-Fix-failing-S3-resum.patch b/resources/libreboot/patch/kgpe-d16/0027-northbridge-amd-amdmct-mct_ddr3-Fix-failing-S3-resum.patch deleted file mode 100644 index 852fc39..0000000 --- a/resources/libreboot/patch/kgpe-d16/0027-northbridge-amd-amdmct-mct_ddr3-Fix-failing-S3-resum.patch +++ /dev/null @@ -1,53 +0,0 @@ -From ade973158610c177dcdaa98cef1b44ebd6ad9255 Mon Sep 17 00:00:00 2001 -From: Timothy Pearson -Date: Mon, 1 Jun 2015 02:40:24 -0500 -Subject: [PATCH 027/139] northbridge/amd/amdmct/mct_ddr3: Fix failing S3 - resume - -Change-Id: I852a8132ff2f39f9297447455ad03d728ce9c5f6 -Signed-off-by: Timothy Pearson ---- - src/northbridge/amd/amdmct/mct_ddr3/s3utils.c | 16 +++++++++++++--- - 1 file changed, 13 insertions(+), 3 deletions(-) - -diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c -index 1dcbea0..c9bcac1 100644 ---- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c -+++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c -@@ -602,7 +602,9 @@ int8_t save_mct_information_to_nvram(void) - int8_t restore_mct_information_from_nvram(void) - { - ssize_t s3nv_offset; -- struct amd_s3_persistent_data persistent_data; -+ ssize_t s3nv_file_offset; -+ void * s3nv_cbfs_file_ptr; -+ struct amd_s3_persistent_data *persistent_data; - - /* Obtain CBFS file offset */ - s3nv_offset = get_s3nv_file_offset(); -@@ -610,11 +612,19 @@ int8_t restore_mct_information_from_nvram(void) - return -1; - - /* Align flash pointer to nearest boundary */ -+ s3nv_file_offset = s3nv_offset; - s3nv_offset &= ~(CONFIG_S3_DATA_SIZE-1); - s3nv_offset += CONFIG_S3_DATA_SIZE; -+ s3nv_file_offset = s3nv_offset - s3nv_file_offset; - -- cbfs_read(CBFS_DEFAULT_MEDIA, &persistent_data, s3nv_offset, sizeof(struct amd_s3_persistent_data)); -- restore_mct_data_from_save_variable(&persistent_data); -+ /* Map data structure in CBFS and restore settings */ -+ s3nv_cbfs_file_ptr = cbfs_boot_map_with_leak(S3NV_FILE_NAME, CBFS_TYPE_RAW, NULL); -+ if (!s3nv_cbfs_file_ptr) { -+ printk(BIOS_DEBUG, "S3 state file could not be mapped: %s\n", S3NV_FILE_NAME); -+ return -1; -+ } -+ persistent_data = (s3nv_cbfs_file_ptr + s3nv_file_offset); -+ restore_mct_data_from_save_variable(persistent_data); - - return 0; - } -\ No newline at end of file --- -1.9.1 - diff --git a/resources/libreboot/patch/kgpe-d16/0028-src-console-Add-x86-printk-spinlock-support.patch b/resources/libreboot/patch/kgpe-d16/0027-src-console-Add-x86-romstage-spinlock-option-and-pri.patch index 2baeb9c..a2aa438 100644 --- a/resources/libreboot/patch/kgpe-d16/0028-src-console-Add-x86-printk-spinlock-support.patch +++ b/resources/libreboot/patch/kgpe-d16/0027-src-console-Add-x86-romstage-spinlock-option-and-pri.patch @@ -1,23 +1,24 @@ -From 5748ef1b46c9625a81b63c9141dfe2bf55dccc20 Mon Sep 17 00:00:00 2001 +From 27f6bb783ba638e6aa2539a6c51ec96386dbf28f Mon Sep 17 00:00:00 2001 From: Timothy Pearson -Date: Sat, 5 Sep 2015 19:23:49 -0500 -Subject: [PATCH 028/139] src/console: Add x86 printk spinlock support +Date: Mon, 18 May 2015 16:04:10 -0500 +Subject: [PATCH 027/143] src/console: Add x86 romstage spinlock option and + prink spinlock support -Change-Id: Ib189ab842ede603b8d5080012ceb92e6964d4fe0 +Change-Id: Ice42a0d3177736bf6e1bc601092e413601866f20 Signed-off-by: Timothy Pearson --- - src/Kconfig | 4 ++++ - src/arch/x86/include/arch/smp/spinlock.h | 1 + - src/console/printk.c | 6 +++--- - src/cpu/amd/car/disable_cache_as_ram.c | 10 ++++++++++ - src/cpu/amd/car/post_cache_as_ram.c | 20 ++++++++++++++------ - 5 files changed, 32 insertions(+), 9 deletions(-) + src/Kconfig | 4 ++++ + src/arch/x86/include/arch/smp/spinlock.h | 11 ++++++++++- + src/console/printk.c | 19 +++++++++++++++++++ + src/cpu/amd/car/disable_cache_as_ram.c | 10 ++++++++++ + src/cpu/amd/car/post_cache_as_ram.c | 20 ++++++++++++++------ + 5 files changed, 57 insertions(+), 7 deletions(-) diff --git a/src/Kconfig b/src/Kconfig -index 2822bfe..4e46364 100644 +index 368384d..5aa33d00 100644 --- a/src/Kconfig +++ b/src/Kconfig -@@ -447,6 +447,10 @@ config HAVE_HARD_RESET +@@ -446,6 +446,10 @@ config HAVE_HARD_RESET This variable specifies whether a given board has a hard_reset function, no matter if it's provided by board code or chipset code. @@ -29,48 +30,91 @@ index 2822bfe..4e46364 100644 def_bool n help diff --git a/src/arch/x86/include/arch/smp/spinlock.h b/src/arch/x86/include/arch/smp/spinlock.h -index a5904c7..5000779 100644 +index 32be2f2..3283540 100644 --- a/src/arch/x86/include/arch/smp/spinlock.h +++ b/src/arch/x86/include/arch/smp/spinlock.h -@@ -13,6 +13,7 @@ typedef struct { +@@ -1,7 +1,7 @@ + #ifndef ARCH_SMP_SPINLOCK_H + #define ARCH_SMP_SPINLOCK_H - #ifdef __PRE_RAM__ - spinlock_t* romstage_console_lock(void); +-#ifndef __PRE_RAM__ ++#if !defined(__PRE_RAM__) || defined(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) + + /* + * Your basic SMP spinlocks, allowing only a single CPU anywhere +@@ -11,9 +11,18 @@ typedef struct { + volatile unsigned int lock; + } spinlock_t; + ++#ifdef __PRE_RAM__ ++spinlock_t *romstage_console_lock(void); +void initialize_romstage_console_lock(void); - #endif ++#endif #define SPIN_LOCK_UNLOCKED (spinlock_t) { 1 } ++ ++#ifndef __PRE_RAM__ + #define DECLARE_SPIN_LOCK(x) static spinlock_t x = SPIN_LOCK_UNLOCKED; ++#else ++#define DECLARE_SPIN_LOCK(x) ++#endif + + /* + * Simple spin lock operations. There are two variants, one clears IRQ's diff --git a/src/console/printk.c b/src/console/printk.c -index 2aae980..5a23db0 100644 +index aab7ff5..5a23db0 100644 --- a/src/console/printk.c +++ b/src/console/printk.c -@@ -14,7 +14,7 @@ +@@ -2,6 +2,7 @@ + * blatantly copied from linux/kernel/printk.c + * + * Copyright (C) 1991, 1992 Linus Torvalds ++ * Copyright (C) 2015 Timothy Pearson , Raptor Engineering + * + */ + +@@ -13,7 +14,13 @@ #include #include --#if defined(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) +#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) - #ifndef __PRE_RAM__ ++#ifndef __PRE_RAM__ DECLARE_SPIN_LOCK(console_lock) ++#endif ++#else ++DECLARE_SPIN_LOCK(console_lock) ++#endif + + void do_putchar(unsigned char byte) + { +@@ -39,7 +46,13 @@ int do_printk(int msg_level, const char *fmt, ...) #endif -@@ -47,7 +47,7 @@ int do_printk(int msg_level, const char *fmt, ...) DISABLE_TRACE; - #ifdef __PRE_RAM__ --#ifdef CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK ++#ifdef __PRE_RAM__ +#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) - spin_lock(romstage_console_lock()); - #endif - #else -@@ -61,7 +61,7 @@ int do_printk(int msg_level, const char *fmt, ...) ++ spin_lock(romstage_console_lock()); ++#endif ++#else + spin_lock(&console_lock); ++#endif + + va_start(args, fmt); + i = vtxprintf(wrap_putchar, fmt, args, NULL); +@@ -47,7 +60,13 @@ int do_printk(int msg_level, const char *fmt, ...) + console_tx_flush(); - #ifdef __PRE_RAM__ --#ifdef CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK ++#ifdef __PRE_RAM__ +#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) - spin_unlock(romstage_console_lock()); - #endif - #else ++ spin_unlock(romstage_console_lock()); ++#endif ++#else + spin_unlock(&console_lock); ++#endif + ENABLE_TRACE; + + return i; diff --git a/src/cpu/amd/car/disable_cache_as_ram.c b/src/cpu/amd/car/disable_cache_as_ram.c index 3b464b8..5eccf79 100644 --- a/src/cpu/amd/car/disable_cache_as_ram.c @@ -145,5 +189,5 @@ index e265de1..257b41a 100644 size_t car_size = car_data_size(); void *migrated_car = (void *)(CONFIG_RAMTOP - car_size); -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0026-northbridge-amd-amdmct-mct_ddr3-Fix-S3-suspend-overr.patch b/resources/libreboot/patch/kgpe-d16/0028-northbridge-amd-amdmct-mct_ddr3-Fix-S3-suspend-overr.patch index 638d21b..6616f45 100644 --- a/resources/libreboot/patch/kgpe-d16/0026-northbridge-amd-amdmct-mct_ddr3-Fix-S3-suspend-overr.patch +++ b/resources/libreboot/patch/kgpe-d16/0028-northbridge-amd-amdmct-mct_ddr3-Fix-S3-suspend-overr.patch @@ -1,17 +1,17 @@ -From ff54c12aa8d07a74ff4e84a5b020f64eb554ac4c Mon Sep 17 00:00:00 2001 +From 7023056e63402e693489a04925f854e4217f9b50 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sun, 31 May 2015 18:46:40 -0500 -Subject: [PATCH 026/139] northbridge/amd/amdmct/mct_ddr3: Fix S3 suspend +Subject: [PATCH 028/143] northbridge/amd/amdmct/mct_ddr3: Fix S3 suspend overrunning the stack size limit Change-Id: Id7441dacef2e46e283d1fc99d5e5fa3f20e0d097 Signed-off-by: Timothy Pearson --- - src/northbridge/amd/amdmct/mct_ddr3/s3utils.c | 16 +++++++++++++--- + src/northbridge/amd/amdmct/mct_ddr3/s3utils.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c -index 78523e8..1dcbea0 100644 +index a49499f..c9bcac1 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c @@ -543,10 +543,17 @@ int8_t save_mct_information_to_nvram(void) @@ -47,5 +47,5 @@ index 78523e8..1dcbea0 100644 /* Tear down SPI flash access */ flash->spi->rw = SPI_WRITE_FLAG; -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0029-lib-stack-Add-stack-overrun-detection.patch b/resources/libreboot/patch/kgpe-d16/0029-lib-stack-Add-stack-overrun-detection.patch index b0fc1e3..7a05905 100644 --- a/resources/libreboot/patch/kgpe-d16/0029-lib-stack-Add-stack-overrun-detection.patch +++ b/resources/libreboot/patch/kgpe-d16/0029-lib-stack-Add-stack-overrun-detection.patch @@ -1,12 +1,12 @@ -From aa92a6ff110c9fd77f6b157fa509988d597ad2e0 Mon Sep 17 00:00:00 2001 +From 1d4b434ed93ad03bd97152310fc24f60342e6b9b Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sat, 5 Sep 2015 19:31:03 -0500 -Subject: [PATCH 029/139] lib/stack: Add stack overrun detection +Subject: [PATCH 029/143] lib/stack: Add stack overrun detection Change-Id: I9a59fcb7cf221ae590a047c520e7aff99e23ecf1 Signed-off-by: Timothy Pearson --- - src/lib/stack.c | 5 +++-- + src/lib/stack.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/lib/stack.c b/src/lib/stack.c @@ -34,5 +34,5 @@ index 52dd723..bebeea2 100644 return -1; } -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0030-cpu-x86-lapic-Add-stack-overrun-detection.patch b/resources/libreboot/patch/kgpe-d16/0030-cpu-x86-lapic-Add-stack-overrun-detection.patch index 5defeab..10221c9 100644 --- a/resources/libreboot/patch/kgpe-d16/0030-cpu-x86-lapic-Add-stack-overrun-detection.patch +++ b/resources/libreboot/patch/kgpe-d16/0030-cpu-x86-lapic-Add-stack-overrun-detection.patch @@ -1,12 +1,12 @@ -From e30acf3fb35f09d788f29f9603124bcbc24723fb Mon Sep 17 00:00:00 2001 +From 626b7adfbc9c50a5e078075635efddf5707ef9a2 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sat, 5 Sep 2015 19:31:20 -0500 -Subject: [PATCH 030/139] cpu/x86/lapic: Add stack overrun detection +Subject: [PATCH 030/143] cpu/x86/lapic: Add stack overrun detection Change-Id: I03e43f38e0d2e51141208ebb169ad8deba77ab78 Signed-off-by: Timothy Pearson --- - src/cpu/x86/lapic/lapic_cpu_init.c | 2 ++ + src/cpu/x86/lapic/lapic_cpu_init.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -30,5 +30,5 @@ index 7fedd00..faa1f1f 100644 checkstack((void *)stacks[i] + CONFIG_STACK_SIZE, i); } -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0031-southbridge-amd-sr5650-Add-AMD-Family-15h-CPU-suppor.patch b/resources/libreboot/patch/kgpe-d16/0031-southbridge-amd-sr5650-Add-AMD-Family-15h-CPU-suppor.patch index d43fab6..d99746e 100644 --- a/resources/libreboot/patch/kgpe-d16/0031-southbridge-amd-sr5650-Add-AMD-Family-15h-CPU-suppor.patch +++ b/resources/libreboot/patch/kgpe-d16/0031-southbridge-amd-sr5650-Add-AMD-Family-15h-CPU-suppor.patch @@ -1,13 +1,13 @@ -From 7102e3001406f8eedbfbbeefafb2f27b62b47d03 Mon Sep 17 00:00:00 2001 +From 89f0d8276a64d05d7cf091ac41402bdf7f71f4ba Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sat, 5 Sep 2015 19:30:38 -0500 -Subject: [PATCH 031/139] southbridge/amd/sr5650: Add AMD Family 15h CPU +Subject: [PATCH 031/143] southbridge/amd/sr5650: Add AMD Family 15h CPU support Change-Id: I88203907270db1a268bd377151f15c24fca1efdc Signed-off-by: Timothy Pearson --- - src/southbridge/amd/sr5650/early_setup.c | 2 ++ + src/southbridge/amd/sr5650/early_setup.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c @@ -24,5 +24,5 @@ index 664f60a..62b0dab 100644 printk(BIOS_INFO, "CPU Rev is not recognized.\n"); } -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0032-cpu-amd-Move-model_10xxx-to-family_10h-family_15h.patch b/resources/libreboot/patch/kgpe-d16/0032-cpu-amd-Move-model_10xxx-to-family_10h-family_15h.patch index a255f78..c70b089 100644 --- a/resources/libreboot/patch/kgpe-d16/0032-cpu-amd-Move-model_10xxx-to-family_10h-family_15h.patch +++ b/resources/libreboot/patch/kgpe-d16/0032-cpu-amd-Move-model_10xxx-to-family_10h-family_15h.patch @@ -1,7 +1,7 @@ -From 54b88ab6e8f0b5a48bf8b0df168a6d12d44b09df Mon Sep 17 00:00:00 2001 +From a9c46688fdefebdf70848b4aba0021d747baee16 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Fri, 16 Oct 2015 14:24:06 -0500 -Subject: [PATCH 032/139] cpu/amd: Move model_10xxx to family_10h-family_15h +Subject: [PATCH 032/143] cpu/amd: Move model_10xxx to family_10h-family_15h Change-Id: I34501d3fc68b71db7781dad11d5b883868932a60 Signed-off-by: Timothy Pearson @@ -10,7 +10,7 @@ Signed-off-by: Timothy Pearson src/cpu/amd/family_10h-family_15h/Kconfig | 88 ++ src/cpu/amd/family_10h-family_15h/Makefile.inc | 14 + src/cpu/amd/family_10h-family_15h/defaults.h | 479 +++++++++ - src/cpu/amd/family_10h-family_15h/fidvid.c | 1049 ++++++++++++++++++++ + src/cpu/amd/family_10h-family_15h/fidvid.c | 1048 ++++++++++++++++++++ src/cpu/amd/family_10h-family_15h/init_cpus.c | 968 ++++++++++++++++++ .../amd/family_10h-family_15h/model_10xxx_init.c | 165 +++ .../amd/family_10h-family_15h/monotonic_timer.c | 98 ++ @@ -22,7 +22,7 @@ Signed-off-by: Timothy Pearson src/cpu/amd/model_10xxx/Kconfig | 88 -- src/cpu/amd/model_10xxx/Makefile.inc | 14 - src/cpu/amd/model_10xxx/defaults.h | 479 --------- - src/cpu/amd/model_10xxx/fidvid.c | 1049 -------------------- + src/cpu/amd/model_10xxx/fidvid.c | 1048 -------------------- src/cpu/amd/model_10xxx/init_cpus.c | 968 ------------------ src/cpu/amd/model_10xxx/model_10xxx_init.c | 165 --- src/cpu/amd/model_10xxx/monotonic_timer.c | 98 -- @@ -60,7 +60,7 @@ Signed-off-by: Timothy Pearson src/mainboard/supermicro/h8scm_fam10/romstage.c | 2 +- src/mainboard/tyan/s2912_fam10/romstage.c | 2 +- src/northbridge/amd/amdfam10/northbridge.c | 2 +- - 54 files changed, 3675 insertions(+), 3675 deletions(-) + 54 files changed, 3674 insertions(+), 3674 deletions(-) create mode 100644 src/cpu/amd/family_10h-family_15h/Kconfig create mode 100644 src/cpu/amd/family_10h-family_15h/Makefile.inc create mode 100644 src/cpu/amd/family_10h-family_15h/defaults.h @@ -700,15 +700,14 @@ index 0000000..6fd1a7e +}; diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c new file mode 100644 -index 0000000..99ffcc8 +index 0000000..5b1c581 --- /dev/null +++ b/src/cpu/amd/family_10h-family_15h/fidvid.c -@@ -0,0 +1,1049 @@ +@@ -0,0 +1,1048 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. -+ * Copyright (C) 2015 Timothy Pearson , Raptor Engineering + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by @@ -4417,15 +4416,14 @@ index 6fd1a7e..0000000 -}; diff --git a/src/cpu/amd/model_10xxx/fidvid.c b/src/cpu/amd/model_10xxx/fidvid.c deleted file mode 100644 -index 99ffcc8..0000000 +index 5b1c581..0000000 --- a/src/cpu/amd/model_10xxx/fidvid.c +++ /dev/null -@@ -1,1049 +0,0 @@ +@@ -1,1048 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. -- * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by @@ -7881,7 +7879,7 @@ index 1049014..0030619 100644 static void sio_setup(void) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c -index 3b302e8..adcfdf0 100644 +index ff324cd..fb3b2f7 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -34,7 +34,7 @@ @@ -7894,5 +7892,5 @@ index 3b302e8..adcfdf0 100644 #if CONFIG_LOGICAL_CPUS #include -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0033-cpu-amd-family_10h-family_15h-Use-correct-label-for-.patch b/resources/libreboot/patch/kgpe-d16/0033-cpu-amd-family_10h-family_15h-Use-correct-label-for-.patch new file mode 100644 index 0000000..91195af --- /dev/null +++ b/resources/libreboot/patch/kgpe-d16/0033-cpu-amd-family_10h-family_15h-Use-correct-label-for-.patch @@ -0,0 +1,28 @@ +From 24270e39badca612e98db97d736a6f8270f0e036 Mon Sep 17 00:00:00 2001 +From: Timothy Pearson +Date: Tue, 20 Oct 2015 01:17:34 -0500 +Subject: [PATCH 033/143] cpu/amd/family_10h-family_15h: Use correct label for + break state + +Change-Id: I07e517f239807cbe76037308f0beff80c9a6f2ba +Signed-off-by: Timothy Pearson +--- + src/cpu/amd/family_10h-family_15h/fidvid.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c +index 5b1c581..86e3179 100644 +--- a/src/cpu/amd/family_10h-family_15h/fidvid.c ++++ b/src/cpu/amd/family_10h-family_15h/fidvid.c +@@ -860,7 +860,7 @@ static void init_fidvid_bsp_stage1(u32 ap_apicid, void *gp) + while (--loop > 0) { + if (lapic_remote_read(ap_apicid, LAPIC_MSG_REG, &readback) != 0) + continue; +- if ((readback & 0x3f) == 1) { ++ if ((readback & 0x3f) == F10_APSTATE_RESET) { + timeout = 0; + break; /* target ap is in stage 1 */ + } +-- +1.7.9.5 + diff --git a/resources/libreboot/patch/kgpe-d16/0033-cpu-amd-Add-initial-AMD-Family-15h-support.patch b/resources/libreboot/patch/kgpe-d16/0034-cpu-amd-Add-initial-AMD-Family-15h-support.patch index 75aa195..fa979fe 100644 --- a/resources/libreboot/patch/kgpe-d16/0033-cpu-amd-Add-initial-AMD-Family-15h-support.patch +++ b/resources/libreboot/patch/kgpe-d16/0034-cpu-amd-Add-initial-AMD-Family-15h-support.patch @@ -1,7 +1,7 @@ -From db769f9a54ca4b8a1872c031f29aae31f412e2a2 Mon Sep 17 00:00:00 2001 +From 429c96728e6a22e1d53f801c8bd4075a91fe422b Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Fri, 16 Oct 2015 13:51:51 -0500 -Subject: [PATCH 033/139] cpu/amd: Add initial AMD Family 15h support +Subject: [PATCH 034/143] cpu/amd: Add initial AMD Family 15h support TEST: Booted ASUS KGPE-D16 with single Opteron 6380 * Unbuffered DDR3 DIMMs tested and working @@ -15,14 +15,15 @@ Change-Id: Idffd2ce36ce183fbfa087e5ba69a9148f084b45e Signed-off-by: Timothy Pearson --- src/cpu/amd/car/cache_as_ram.inc | 130 +- - src/cpu/amd/car/disable_cache_as_ram.c | 77 +- + src/cpu/amd/car/disable_cache_as_ram.c | 79 +- src/cpu/amd/family_10h-family_15h/defaults.h | 266 +- - src/cpu/amd/family_10h-family_15h/fidvid.c | 235 +- + src/cpu/amd/family_10h-family_15h/fidvid.c | 237 +- src/cpu/amd/family_10h-family_15h/init_cpus.c | 232 +- .../amd/family_10h-family_15h/model_10xxx_init.c | 92 +- src/cpu/amd/family_10h-family_15h/powernow_acpi.c | 50 +- src/cpu/amd/family_10h-family_15h/processor_name.c | 194 +- .../amd/family_10h-family_15h/update_microcode.c | 6 + + src/cpu/amd/model_fxx/init_cpus.c | 2 +- src/cpu/amd/quadcore/quadcore.c | 109 +- src/cpu/amd/quadcore/quadcore_id.c | 43 +- src/include/cpu/amd/model_10xxx_msr.h | 7 + @@ -32,6 +33,7 @@ Signed-off-by: Timothy Pearson .../amd/serengeti_cheetah_fam10/romstage.c | 2 +- src/mainboard/amd/tilapia_fam10/romstage.c | 2 +- src/mainboard/asus/kfsn4-dre/romstage.c | 2 +- + src/mainboard/asus/kgpe-d16/romstage.c | 4 +- src/mainboard/asus/m4a78-em/romstage.c | 2 +- src/mainboard/asus/m4a785-m/romstage.c | 2 +- src/mainboard/asus/m5a88-v/romstage.c | 2 +- @@ -83,8 +85,8 @@ Signed-off-by: Timothy Pearson src/northbridge/amd/amdmct/mct_ddr3/mwlc_d.h | 46 +- src/northbridge/amd/amdmct/mct_ddr3/s3utils.c | 652 +++- src/northbridge/amd/amdmct/wrappers/mcti.h | 14 +- - src/northbridge/amd/amdmct/wrappers/mcti_d.c | 42 +- - 70 files changed, 9184 insertions(+), 2064 deletions(-) + src/northbridge/amd/amdmct/wrappers/mcti_d.c | 43 +- + 72 files changed, 9192 insertions(+), 2067 deletions(-) create mode 100644 src/northbridge/amd/amdfam10/link_control.c create mode 100644 src/northbridge/amd/amdfam10/nb_control.c @@ -330,7 +332,7 @@ index 0b2bc60..6542906 100644 /* We will not go back. */ diff --git a/src/cpu/amd/car/disable_cache_as_ram.c b/src/cpu/amd/car/disable_cache_as_ram.c -index 5eccf79..5cab544 100644 +index 5eccf79..86180ee 100644 --- a/src/cpu/amd/car/disable_cache_as_ram.c +++ b/src/cpu/amd/car/disable_cache_as_ram.c @@ -19,7 +19,7 @@ @@ -342,7 +344,7 @@ index 5eccf79..5cab544 100644 */ #include -@@ -34,41 +34,78 @@ static inline __attribute__((always_inline)) uint32_t amd_fam1x_cpu_family(void) +@@ -34,41 +34,80 @@ static inline __attribute__((always_inline)) uint32_t amd_fam1x_cpu_family(void) return family; } @@ -390,42 +392,43 @@ index 5eccf79..5cab544 100644 + + enable_cache(); + } -+ + +- msr = rdmsr(SYSCFG_MSR); +- msr.lo &= ~(SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrFixDramModEn); +- wrmsr(SYSCFG_MSR, msr); + /* INVDWBINVD = 1 */ + msr = rdmsr(0xc0010015); + msr.lo |= (0x1 << 4); + wrmsr(0xc0010015, msr); -+ + +- /* Set the default memory type and disable fixed and enable variable MTRRs */ +- msr.hi = 0; +- msr.lo = (1 << 11); + family = amd_fam1x_cpu_family(); -+ + +- wrmsr(MTRR_DEF_TYPE_MSR, msr); ++#if IS_ENABLED(CPU_AMD_MODEL_10XXX) + if (family >= 0x6f) { + /* Family 15h or later */ -- msr = rdmsr(SYSCFG_MSR); -- msr.lo &= ~(SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrFixDramModEn); -- wrmsr(SYSCFG_MSR, msr); +- enable_cache(); + /* DisSS = 0 */ + msr = rdmsr(0xc0011020); + msr.lo &= ~(0x1 << 28); + wrmsr(0xc0011020, msr); - -- /* Set the default memory type and disable fixed and enable variable MTRRs */ -- msr.hi = 0; -- msr.lo = (1 << 11); ++ + if (!skip_sharedc_config) { + /* DisSpecTlbRld = 0 */ + msr = rdmsr(0xc0011021); + msr.lo &= ~(0x1 << 9); + wrmsr(0xc0011021, msr); - -- wrmsr(MTRR_DEF_TYPE_MSR, msr); ++ + /* Erratum 714: SpecNbReqDis = 0 */ + msr = rdmsr(BU_CFG2_MSR); + msr.lo &= ~(0x1 << 8); + wrmsr(BU_CFG2_MSR, msr); + } - -- enable_cache(); ++ + /* DisSpecTlbRld = 0 */ + /* DisHwPf = 0 */ + msr = rdmsr(0xc0011022); @@ -433,6 +436,7 @@ index 5eccf79..5cab544 100644 + msr.lo &= ~(0x1 << 13); + wrmsr(0xc0011022, msr); + } ++#endif } static void disable_cache_as_ram_bsp(void) @@ -957,10 +961,18 @@ index 6fd1a7e..24f87ba 100644 [20:16] RttIndex = 04h */ }; diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c -index 99ffcc8..2e26645 100644 +index 86e3179..e8e0818 100644 --- a/src/cpu/amd/family_10h-family_15h/fidvid.c +++ b/src/cpu/amd/family_10h-family_15h/fidvid.c -@@ -44,7 +44,7 @@ Fam10 Bios and Kernel Development Guide #31116, rev 3.48, April 22, 2010 +@@ -2,6 +2,7 @@ + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. ++ * Copyright (C) 2015 Timothy Pearson , Raptor Engineering + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by +@@ -43,7 +44,7 @@ Fam10 Bios and Kernel Development Guide #31116, rev 3.48, April 22, 2010 3.- 2.4.2.7 dualPlaneOnly(dev) @@ -969,7 +981,7 @@ index 99ffcc8..2e26645 100644 5.- enableNbPState1(dev) -@@ -143,25 +143,33 @@ static void enable_fid_change(u8 fid) +@@ -142,25 +143,33 @@ static void enable_fid_change(u8 fid) } } @@ -1019,7 +1031,7 @@ index 99ffcc8..2e26645 100644 if (cpuRev & AMD_FAM10_C3) { u32 nbPState = (pci_read_config32(dev, 0x1F0) & NB_PSTATE_MASK); if ( nbPState){ -@@ -203,7 +211,7 @@ static u8 setPStateMaxVal( device_t dev ) { +@@ -202,7 +211,7 @@ static u8 setPStateMaxVal( device_t dev ) { static void dualPlaneOnly( device_t dev ) { // BKDG 2.4.2.7 @@ -1028,7 +1040,7 @@ index 99ffcc8..2e26645 100644 if ((mctGetProcessorPackageType() == AMD_PKGTYPE_AM3_2r2) && (cpuRev & AMD_DR_Cx)) { // should be rev C or rev E but there's no constant for E if ( (pci_read_config32(dev, 0x1FC) & DUAL_PLANE_ONLY_MASK) -@@ -283,12 +291,16 @@ static void recalculateVsSlamTimeSettingOnCorePre(device_t dev) +@@ -282,12 +291,16 @@ static void recalculateVsSlamTimeSettingOnCorePre(device_t dev) */ /* Determine if this is a PVI or SVI system */ @@ -1050,7 +1062,7 @@ index 99ffcc8..2e26645 100644 /* Get P0's voltage */ /* MSRC001_00[68:64] are not programmed yet when called from -@@ -515,59 +527,67 @@ static void config_nb_syn_ptr_adj(device_t dev, u32 cpuRev) { +@@ -514,59 +527,67 @@ static void config_nb_syn_ptr_adj(device_t dev, u32 cpuRev) { } static void config_acpi_pwr_state_ctrl_regs(device_t dev, u32 cpuRev, u8 procPkg) { @@ -1171,7 +1183,7 @@ index 99ffcc8..2e26645 100644 } static void prep_fid_change(void) -@@ -584,7 +604,7 @@ static void prep_fid_change(void) +@@ -583,7 +604,7 @@ static void prep_fid_change(void) for (i = 0; i < nodes; i++) { printk(BIOS_DEBUG, "Prep FID/VID Node:%02x\n", i); dev = NODE_PCI(i, 3); @@ -1180,7 +1192,7 @@ index 99ffcc8..2e26645 100644 u8 procPkg = mctGetProcessorPackageType(); setVSRamp(dev); -@@ -612,7 +632,7 @@ static void prep_fid_change(void) +@@ -611,7 +632,7 @@ static void prep_fid_change(void) } } @@ -1189,7 +1201,7 @@ index 99ffcc8..2e26645 100644 msr_t initial_msr = rdmsr(TSC_MSR); msr_t pstate_msr = rdmsr(CUR_PSTATE_MSR); msr_t tsc_msr; -@@ -645,7 +665,7 @@ static void waitCurrentPstate(u32 target_pstate){ +@@ -644,7 +665,7 @@ static void waitCurrentPstate(u32 target_pstate){ if (pstate_msr.lo != target_pstate) { msr_t limit_msr = rdmsr(0xc0010061); @@ -1198,7 +1210,7 @@ index 99ffcc8..2e26645 100644 do { // should we just go on instead ? pstate_msr = rdmsr(CUR_PSTATE_MSR); -@@ -655,6 +675,7 @@ static void waitCurrentPstate(u32 target_pstate){ +@@ -654,6 +675,7 @@ static void waitCurrentPstate(u32 target_pstate){ static void set_pstate(u32 nonBoostedPState) { msr_t msr; @@ -1206,7 +1218,7 @@ index 99ffcc8..2e26645 100644 // Transition P0 for calling core. msr = rdmsr(0xC0010062); -@@ -662,12 +683,21 @@ static void set_pstate(u32 nonBoostedPState) { +@@ -661,12 +683,21 @@ static void set_pstate(u32 nonBoostedPState) { msr.lo = nonBoostedPState; wrmsr(0xC0010062, msr); @@ -1233,7 +1245,7 @@ index 99ffcc8..2e26645 100644 static void UpdateSinglePlaneNbVid(void) { -@@ -757,11 +787,14 @@ static u32 needs_NB_COF_VID_update(void) +@@ -756,11 +787,14 @@ static u32 needs_NB_COF_VID_update(void) u8 nodes; u8 i; @@ -1249,7 +1261,7 @@ index 99ffcc8..2e26645 100644 u32 nbCofVidUpdateDefined = (cpuRev & (AMD_FAM10_LT_D)); if (nbCofVidUpdateDefined && (pci_read_config32(NODE_PCI(i, 3), 0x1FC) -@@ -785,9 +818,11 @@ static u32 init_fidvid_core(u32 nodeid, u32 coreid) +@@ -784,9 +818,11 @@ static u32 init_fidvid_core(u32 nodeid, u32 coreid) /* Steps 1-6 of BIOS NB COF and VID Configuration * for SVI and Single-Plane PVI Systems. BKDG 2.4.2.9 #31116 rev 3.48 */ @@ -1263,7 +1275,7 @@ index 99ffcc8..2e26645 100644 reg1fc = pci_read_config32(dev, 0x1FC); if (nb_cof_vid_update) { -@@ -799,7 +834,7 @@ static u32 init_fidvid_core(u32 nodeid, u32 coreid) +@@ -798,7 +834,7 @@ static u32 init_fidvid_core(u32 nodeid, u32 coreid) fid_max = fid_max + ((reg1fc & DUAL_PLANE_NB_FID_OFF_MASK ) >> DUAL_PLANE_NB_FID_SHIFT ); } /* write newNbVid to P-state Reg's NbVid always if NbVidUpdatedAll=1 */ @@ -1272,7 +1284,7 @@ index 99ffcc8..2e26645 100644 /* fid setup is handled by the BSP at the end. */ -@@ -819,7 +854,7 @@ static void init_fidvid_ap(u32 apicid, u32 nodeid, u32 coreid) +@@ -818,7 +854,7 @@ static void init_fidvid_ap(u32 apicid, u32 nodeid, u32 coreid) printk(BIOS_DEBUG, "FIDVID on AP: %02x\n", apicid); @@ -1281,16 +1293,17 @@ index 99ffcc8..2e26645 100644 send |= (apicid << 24); // ap apicid // Send signal to BSP about this AP max fid -@@ -861,7 +896,7 @@ static void init_fidvid_bsp_stage1(u32 ap_apicid, void *gp) +@@ -860,7 +896,8 @@ static void init_fidvid_bsp_stage1(u32 ap_apicid, void *gp) while (--loop > 0) { if (lapic_remote_read(ap_apicid, LAPIC_MSG_REG, &readback) != 0) continue; -- if ((readback & 0x3f) == 1) { -+ if (((readback & 0x3f) == 1) || ((readback & 0x3f) == F10_APSTATE_ASLEEP)) { +- if ((readback & 0x3f) == F10_APSTATE_RESET) { ++ if (((readback & 0x3f) == F10_APSTATE_RESET) ++ || (is_fam15h() && ((readback & 0x3f) == F10_APSTATE_ASLEEP))) { timeout = 0; break; /* target ap is in stage 1 */ } -@@ -949,7 +984,10 @@ static void init_fidvid_stage2(u32 apicid, u32 nodeid) +@@ -948,7 +985,10 @@ static void init_fidvid_stage2(u32 apicid, u32 nodeid) /* If any node has nb_cof_vid_update set all nodes need an update. */ dev = NODE_PCI(nodeid, 3); @@ -1302,7 +1315,7 @@ index 99ffcc8..2e26645 100644 reg1fc = pci_read_config32(dev, 0x1FC); nbvid = (reg1fc >> 7) & 0x7F; NbVidUpdateAll = (reg1fc >> 1) & 1; -@@ -970,15 +1008,17 @@ static void init_fidvid_stage2(u32 apicid, u32 nodeid) +@@ -969,15 +1009,17 @@ static void init_fidvid_stage2(u32 apicid, u32 nodeid) pci_write_config32(dev, 0xA0, dtemp); dualPlaneOnly(dev); @@ -1325,7 +1338,7 @@ index 99ffcc8..2e26645 100644 } -@@ -1012,8 +1052,7 @@ static int init_fidvid_bsp(u32 bsp_apicid, u32 nodes) +@@ -1011,8 +1053,7 @@ static int init_fidvid_bsp(u32 bsp_apicid, u32 nodes) /* Steps 1-6 of BIOS NB COF and VID Configuration * for SVI and Single-Plane PVI Systems. */ @@ -2229,6 +2242,19 @@ index 51aca35..3b2f5dd 100644 /* Array terminator */ { 0xffffff, 0x0000 }, }; +diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c +index 12d3a95..3960c03 100644 +--- a/src/cpu/amd/model_fxx/init_cpus.c ++++ b/src/cpu/amd/model_fxx/init_cpus.c +@@ -190,7 +190,7 @@ void allow_all_aps_stop(u32 bsp_apicid) + + static void STOP_CAR_AND_CPU(void) + { +- disable_cache_as_ram(); // inline ++ disable_cache_as_ram(0); // inline + /* stop all cores except node0/core0 the bsp .... */ + stop_this_cpu(); + } diff --git a/src/cpu/amd/quadcore/quadcore.c b/src/cpu/amd/quadcore/quadcore.c index 9c21e94..8a9b5ed 100644 --- a/src/cpu/amd/quadcore/quadcore.c @@ -2566,6 +2592,26 @@ index 5d1f5a6..dd5c7dc 100644 post_code(0x34); amd_ht_init(sysinfo); +diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c +index a3f3310..a58fd0f 100644 +--- a/src/mainboard/asus/kgpe-d16/romstage.c ++++ b/src/mainboard/asus/kgpe-d16/romstage.c +@@ -354,7 +354,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) + + post_code(0x33); + +- cpuSetAMDMSR(); ++ cpuSetAMDMSR(0); + post_code(0x34); + + amd_ht_init(sysinfo); +@@ -512,4 +512,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) + BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) + { + return 0; +-} +\ No newline at end of file ++} diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index 82f30d9..82b96bf 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c @@ -2814,7 +2860,7 @@ index a1e08a0..b724394 100644 #ifdef __PRE_RAM__ diff --git a/src/northbridge/amd/amdfam10/amdfam10_util.c b/src/northbridge/amd/amdfam10/amdfam10_util.c -index 423bb73..a4045bd 100644 +index 423bb73..a4045bdf 100644 --- a/src/northbridge/amd/amdfam10/amdfam10_util.c +++ b/src/northbridge/amd/amdfam10/amdfam10_util.c @@ -34,14 +34,14 @@ u32 Get_NB32(u32 dev, u32 reg) @@ -3060,7 +3106,7 @@ index 0000000..f95b6f8 +}; \ No newline at end of file diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c -index adcfdf0..baf77d6 100644 +index fb3b2f7..fcf85a7 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -81,6 +81,21 @@ device_t get_node_pci(u32 nodeid, u32 fn) @@ -13628,7 +13674,7 @@ index 1c3e322..0ff4484 100644 } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c -index 9f42d54..7ea7901 100644 +index 397fd77..35378c8 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c @@ -30,13 +30,22 @@ @@ -14057,7 +14103,7 @@ index 9f42d54..7ea7901 100644 if (wl) { - if (rank == 0) { - /* Get Rtt_WR for the current DIMM and rank */ -- uint16_t dynamic_term = unbuffered_dimm_dynamic_termination_emrs(pDCTData->MaxDimmsInstalled, MemClkFreq, pDCTData->DimmRanks[currDimm], rank); +- uint16_t dynamic_term = unbuffered_dimm_dynamic_termination_emrs(pDCTData->MaxDimmsInstalled, MemClkFreq, pDCTData->DimmRanks[dimm], rank); - - /* Convert dynamic termination code to corresponding nominal termination code */ - if (dynamic_term == 0x200) @@ -14074,11 +14120,11 @@ index 9f42d54..7ea7901 100644 + tempW2 = fam15_rttnom(pDCTstat, dct, dimm, rank, package_type); + } } else { -- tempW1 = unbuffered_dimm_nominal_termination_emrs(pDCTData->MaxDimmsInstalled, MemClkFreq, pDCTData->DimmRanks[currDimm], rank); +- tempW1 = unbuffered_dimm_nominal_termination_emrs(pDCTData->MaxDimmsInstalled, MemClkFreq, pDCTData->DimmRanks[dimm], rank); + tempW2 = fam15_rttnom(pDCTstat, dct, dimm, rank, package_type); } } else { -- tempW1 = unbuffered_dimm_nominal_termination_emrs(pDCTData->MaxDimmsInstalled, MemClkFreq, pDCTData->DimmRanks[currDimm], rank); +- tempW1 = unbuffered_dimm_nominal_termination_emrs(pDCTData->MaxDimmsInstalled, MemClkFreq, pDCTData->DimmRanks[dimm], rank); + tempW2 = fam15_rttnom(pDCTstat, dct, dimm, rank, package_type); + } + tempW1 = 0; @@ -14093,7 +14139,7 @@ index 9f42d54..7ea7901 100644 + if (number_of_dimms > 1) { + if (rank == 0) { + /* Get Rtt_WR for the current DIMM and rank */ -+ uint16_t dynamic_term = unbuffered_dimm_dynamic_termination_emrs(pDCTData->MaxDimmsInstalled, MemClkFreq, pDCTData->DimmRanks[currDimm]); ++ uint16_t dynamic_term = unbuffered_dimm_dynamic_termination_emrs(pDCTData->MaxDimmsInstalled, MemClkFreq, pDCTData->DimmRanks[dimm]); + + /* Convert dynamic termination code to corresponding nominal termination code */ + if (dynamic_term == 0x200) @@ -14103,13 +14149,13 @@ index 9f42d54..7ea7901 100644 + else + tempW1 = 0x0; + } else { -+ tempW1 = unbuffered_dimm_nominal_termination_emrs(pDCTData->MaxDimmsInstalled, MemClkFreq, pDCTData->DimmRanks[currDimm], rank); ++ tempW1 = unbuffered_dimm_nominal_termination_emrs(pDCTData->MaxDimmsInstalled, MemClkFreq, pDCTData->DimmRanks[dimm], rank); + } + } else { -+ tempW1 = unbuffered_dimm_nominal_termination_emrs(pDCTData->MaxDimmsInstalled, MemClkFreq, pDCTData->DimmRanks[currDimm], rank); ++ tempW1 = unbuffered_dimm_nominal_termination_emrs(pDCTData->MaxDimmsInstalled, MemClkFreq, pDCTData->DimmRanks[dimm], rank); + } + } else { -+ tempW1 = unbuffered_dimm_nominal_termination_emrs(pDCTData->MaxDimmsInstalled, MemClkFreq, pDCTData->DimmRanks[currDimm], rank); ++ tempW1 = unbuffered_dimm_nominal_termination_emrs(pDCTData->MaxDimmsInstalled, MemClkFreq, pDCTData->DimmRanks[dimm], rank); + } } } @@ -16105,7 +16151,7 @@ index 38e66e1..2aba377 100644 #endif diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c -index 47260f2..1d4eade 100644 +index 444adc5..9969c4f 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -44,7 +44,7 @@ @@ -16149,12 +16195,7 @@ index 47260f2..1d4eade 100644 case NV_DCBKScrub: val = 0; /* Disabled - See DcacheScrub in BKDG */ break; -@@ -299,10 +309,14 @@ static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat) - pDCTstat->PresetmaxFreq = mctGet_NVbits(NV_MAX_MEMCLK); - - /* Determine the number of installed DIMMs */ -+ uint8_t dimm; - int ch1_count = 0; +@@ -303,6 +313,9 @@ static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat) int ch2_count = 0; uint8_t ch1_registered = 0; uint8_t ch2_registered = 0; @@ -16164,18 +16205,19 @@ index 47260f2..1d4eade 100644 int i; for (i = 0; i < 15; i = i + 2) { if (pDCTstat->DIMMValid & (1 << i)) -@@ -321,8 +335,26 @@ static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat) +@@ -321,8 +334,28 @@ static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat) printk(BIOS_DEBUG, "mctGet_MaxLoadFreq: Channel 2: %d DIMM(s) detected\n", ch2_count); } +#if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */ ++ uint8_t dimm; ++ + for (i = 0; i < 15; i = i + 2) { + if (pDCTstat->DIMMValid & (1 << i)) + ch1_voltage |= pDCTstat->DimmConfiguredVoltage[i]; + if (pDCTstat->DIMMValid & (1 << (i + 1))) + ch2_voltage |= pDCTstat->DimmConfiguredVoltage[i + 1]; + } -+#endif + + for (i = 0; i < 2; i++) { + sDCTStruct *pDCTData = pDCTstat->C_DCTPtr[i]; @@ -16185,6 +16227,7 @@ index 47260f2..1d4eade 100644 + highest_rank_count[i] = pDCTData->DimmRanks[dimm]; + } + } ++#endif + /* Set limits if needed */ - pDCTstat->PresetmaxFreq = mct_MaxLoadFreq(max(ch1_count, ch2_count), (ch1_registered || ch2_registered), pDCTstat->PresetmaxFreq); @@ -16192,7 +16235,7 @@ index 47260f2..1d4eade 100644 } #ifdef UNUSED_CODE -@@ -486,7 +518,7 @@ static void mctHookAfterAnyTraining(void) +@@ -486,7 +519,7 @@ static void mctHookAfterAnyTraining(void) { } @@ -16202,5 +16245,5 @@ index 47260f2..1d4eade 100644 return mctGetLogicalCPUID(node); } -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0034-mainboard-asus-kgpe-d16-Add-initial-Family-15h-CPU-s.patch b/resources/libreboot/patch/kgpe-d16/0035-mainboard-asus-kgpe-d16-Add-initial-Family-15h-CPU-s.patch index 9202333..b9d6f92 100644 --- a/resources/libreboot/patch/kgpe-d16/0034-mainboard-asus-kgpe-d16-Add-initial-Family-15h-CPU-s.patch +++ b/resources/libreboot/patch/kgpe-d16/0035-mainboard-asus-kgpe-d16-Add-initial-Family-15h-CPU-s.patch @@ -1,19 +1,19 @@ -From cf1d449f1ac17478863403eb4154433b4fb4a3e7 Mon Sep 17 00:00:00 2001 +From 2774e3488cb3fa2139cd40930a035f0fcfc13ec5 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sat, 5 Sep 2015 19:37:57 -0500 -Subject: [PATCH 034/139] mainboard/asus/kgpe-d16: Add initial Family 15h CPU +Subject: [PATCH 035/143] mainboard/asus/kgpe-d16: Add initial Family 15h CPU support Change-Id: I76f74ed4ae383f8b1f57eaaa2e025035002430f2 Signed-off-by: Timothy Pearson --- - src/mainboard/asus/kgpe-d16/Kconfig | 1 + - src/mainboard/asus/kgpe-d16/cmos.default | 3 +- - src/mainboard/asus/kgpe-d16/cmos.layout | 15 +- - src/mainboard/asus/kgpe-d16/devicetree.cb | 4 + - src/mainboard/asus/kgpe-d16/resourcemap.c | 276 +++++++++++++++++++++++++++++- - src/mainboard/asus/kgpe-d16/romstage.c | 58 ++++--- - 6 files changed, 326 insertions(+), 31 deletions(-) + src/mainboard/asus/kgpe-d16/Kconfig | 1 + + src/mainboard/asus/kgpe-d16/cmos.default | 3 +- + src/mainboard/asus/kgpe-d16/cmos.layout | 15 +- + src/mainboard/asus/kgpe-d16/devicetree.cb | 4 + + src/mainboard/asus/kgpe-d16/resourcemap.c | 276 ++++++++++++++++++++++++++++- + src/mainboard/asus/kgpe-d16/romstage.c | 56 +++--- + 6 files changed, 325 insertions(+), 30 deletions(-) diff --git a/src/mainboard/asus/kgpe-d16/Kconfig b/src/mainboard/asus/kgpe-d16/Kconfig index 9471692..8906dee 100644 @@ -88,10 +88,10 @@ index 110e0bb..e55edc4 100644 9 1 87.5% 9 2 75.0% diff --git a/src/mainboard/asus/kgpe-d16/devicetree.cb b/src/mainboard/asus/kgpe-d16/devicetree.cb -index a172d89..18e337e 100644 +index f4769fd..cd22893 100644 --- a/src/mainboard/asus/kgpe-d16/devicetree.cb +++ b/src/mainboard/asus/kgpe-d16/devicetree.cb -@@ -228,21 +228,25 @@ chip northbridge/amd/amdfam10/root_complex # Root complex +@@ -229,21 +229,25 @@ chip northbridge/amd/amdfam10/root_complex # Root complex device pci 18.2 on end device pci 18.3 on end device pci 18.4 on end @@ -410,7 +410,7 @@ index 3e240dc..3aab8b8 100644 + } } diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c -index a3f3310..9ea7cec 100644 +index a58fd0f..4b4e305 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -42,6 +42,7 @@ @@ -486,15 +486,6 @@ index a3f3310..9ea7cec 100644 /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ set_bsp_node_CHtExtNodeCfgEn(); -@@ -354,7 +373,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - - post_code(0x33); - -- cpuSetAMDMSR(); -+ cpuSetAMDMSR(0); - post_code(0x34); - - amd_ht_init(sysinfo); @@ -368,18 +387,21 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_mb_resource_map(); post_code(0x36); @@ -561,5 +552,5 @@ index a3f3310..9ea7cec 100644 printk(BIOS_INFO, "...WARM RESET...\n\n\n"); soft_reset(); -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0035-cpu-amd-family_10h-family_15h-Add-Family-15h-microco.patch b/resources/libreboot/patch/kgpe-d16/0036-cpu-amd-family_10h-family_15h-Add-Family-15h-microco.patch index e7068f9..ea9887b 100644 --- a/resources/libreboot/patch/kgpe-d16/0035-cpu-amd-family_10h-family_15h-Add-Family-15h-microco.patch +++ b/resources/libreboot/patch/kgpe-d16/0036-cpu-amd-family_10h-family_15h-Add-Family-15h-microco.patch @@ -1,13 +1,13 @@ -From fa4ef470b6b41bdab0063e754df2a8ec8a805238 Mon Sep 17 00:00:00 2001 +From 6cef66c3f775f0c1910d848b4fede77925126c5a Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Fri, 16 Oct 2015 14:08:32 -0500 -Subject: [PATCH 035/139] cpu/amd/family_10h-family_15h: Add Family 15h +Subject: [PATCH 036/143] cpu/amd/family_10h-family_15h: Add Family 15h microcode file Change-Id: I019f94b99d2fc33e19567acecaaad93813ab6b04 Signed-off-by: Timothy Pearson --- - src/cpu/amd/family_10h-family_15h/Makefile.inc | 5 +++++ + src/cpu/amd/family_10h-family_15h/Makefile.inc | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/cpu/amd/family_10h-family_15h/Makefile.inc b/src/cpu/amd/family_10h-family_15h/Makefile.inc @@ -24,5 +24,5 @@ index 5a81ab8..6cd2513 100644 +microcode_amd_fam15h.bin-file := 3rdparty/blobs/cpu/amd/family_15h/microcode_amd_fam15h.bin +microcode_amd_fam15h.bin-type := microcode -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0036-amdmct-mct_ddr3-Disable-Fam10h-specific-MTRR-setup-o.patch b/resources/libreboot/patch/kgpe-d16/0037-amdmct-mct_ddr3-Disable-Fam10h-specific-MTRR-setup-o.patch index cd1a613..96e544c 100644 --- a/resources/libreboot/patch/kgpe-d16/0036-amdmct-mct_ddr3-Disable-Fam10h-specific-MTRR-setup-o.patch +++ b/resources/libreboot/patch/kgpe-d16/0037-amdmct-mct_ddr3-Disable-Fam10h-specific-MTRR-setup-o.patch @@ -1,13 +1,13 @@ -From fd67f1513d362a0a02f999b632c62b7b5c074a50 Mon Sep 17 00:00:00 2001 +From c24f0d24c3957484dafd1d2b91fd1b1a43060c7d Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Mon, 1 Jun 2015 20:35:42 -0500 -Subject: [PATCH 036/139] amdmct/mct_ddr3: Disable Fam10h-specific MTRR setup +Subject: [PATCH 037/143] amdmct/mct_ddr3: Disable Fam10h-specific MTRR setup on Fam15h Change-Id: I5c12b5ef8564402601634e9f3528bbf9303e0b33 Signed-off-by: Timothy Pearson --- - src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 12 +++++++----- + src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -34,5 +34,5 @@ index 74066b1..4677c73 100644 if (is_fam15h()) { -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0037-cpu-amd-car-Add-romstage-BSP-stack-overrun-detection.patch b/resources/libreboot/patch/kgpe-d16/0038-cpu-amd-car-Add-romstage-BSP-stack-overrun-detection.patch index d8c5a24..5300db1 100644 --- a/resources/libreboot/patch/kgpe-d16/0037-cpu-amd-car-Add-romstage-BSP-stack-overrun-detection.patch +++ b/resources/libreboot/patch/kgpe-d16/0038-cpu-amd-car-Add-romstage-BSP-stack-overrun-detection.patch @@ -1,13 +1,14 @@ -From 5ae2feaab88902ab9d5bb95eab1ec396f9c01b9f Mon Sep 17 00:00:00 2001 +From ed27521eaee0dd334c658fb68d0c8ebaa6a126cc Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Mon, 1 Jun 2015 23:58:59 -0500 -Subject: [PATCH 037/139] cpu/amd/car: Add romstage BSP stack overrun detection +Subject: [PATCH 038/143] cpu/amd/car: Add romstage BSP stack overrun + detection Change-Id: Ia2e8f99be9df388e492a633c49df21ca1c57ba13 Signed-off-by: Timothy Pearson --- - src/cpu/amd/car/cache_as_ram.inc | 6 +++++- - src/cpu/amd/car/post_cache_as_ram.c | 8 ++++++++ + src/cpu/amd/car/cache_as_ram.inc | 6 +++++- + src/cpu/amd/car/post_cache_as_ram.c | 8 ++++++++ 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc @@ -54,5 +55,5 @@ index 257b41a..787bedd 100644 handoff = romstage_handoff_find_or_add(); if (handoff != NULL) -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0038-cpu-amd-car-Increase-Family-10h-CAR-size-limit-to-12.patch b/resources/libreboot/patch/kgpe-d16/0039-cpu-amd-car-Increase-Family-10h-CAR-size-limit-to-12.patch index b0ad3b3..17285a1 100644 --- a/resources/libreboot/patch/kgpe-d16/0038-cpu-amd-car-Increase-Family-10h-CAR-size-limit-to-12.patch +++ b/resources/libreboot/patch/kgpe-d16/0039-cpu-amd-car-Increase-Family-10h-CAR-size-limit-to-12.patch @@ -1,7 +1,7 @@ -From e3a15e1b280319fc3c95617b46630b31cf9b571e Mon Sep 17 00:00:00 2001 +From 3cc65b99ac7b00ba5960c5c40a984bebafcf379a Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Tue, 2 Jun 2015 13:25:23 -0500 -Subject: [PATCH 038/139] cpu/amd/car: Increase Family 10h CAR size limit to +Subject: [PATCH 039/143] cpu/amd/car: Increase Family 10h CAR size limit to 128k This resolves issues with 4-node (32-core) systems not having @@ -10,7 +10,7 @@ sufficient CAR memory to boot. Change-Id: I5378df7fe8c034ba30f7fdf454f81dd10a0c2ae4 Signed-off-by: Timothy Pearson --- - src/cpu/amd/car/post_cache_as_ram.c | 2 +- + src/cpu/amd/car/post_cache_as_ram.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c @@ -27,5 +27,5 @@ index 787bedd..2282cee 100644 printk(BIOS_WARNING, "BSP overran lower stack boundary. Undefined behaviour may result!\n"); -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0039-cpu-amd-car-Move-AP-stacks-below-the-BSP-stack-to-fr.patch b/resources/libreboot/patch/kgpe-d16/0040-cpu-amd-car-Move-AP-stacks-below-the-BSP-stack-to-fr.patch index 9364346..d7a949a 100644 --- a/resources/libreboot/patch/kgpe-d16/0039-cpu-amd-car-Move-AP-stacks-below-the-BSP-stack-to-fr.patch +++ b/resources/libreboot/patch/kgpe-d16/0040-cpu-amd-car-Move-AP-stacks-below-the-BSP-stack-to-fr.patch @@ -1,7 +1,7 @@ -From f14fb79d7a979b95ad94b35e5127dfa033b5734c Mon Sep 17 00:00:00 2001 +From 4dfbaf7e6fd49d46c58f8f5e58d0ce4e7e97fa04 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Tue, 2 Jun 2015 20:18:44 -0500 -Subject: [PATCH 039/139] cpu/amd/car: Move AP stacks below the BSP stack to +Subject: [PATCH 040/143] cpu/amd/car: Move AP stacks below the BSP stack to free up space Caching SPD data during startup requires additional CAR space. @@ -12,7 +12,7 @@ allows this space to be utilized. Change-Id: I51af31442f2b77cb64a4b788751ccc7186acb283 Signed-off-by: Timothy Pearson --- - src/cpu/amd/family_10h-family_15h/Kconfig | 2 +- + src/cpu/amd/family_10h-family_15h/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig @@ -29,5 +29,5 @@ index 7c47e27..81b1d1e 100644 config DCACHE_BSP_STACK_SLUSH hex -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0040-northbridge-amd-amdmct-Read-SPD-data-into-cache-to-d.patch b/resources/libreboot/patch/kgpe-d16/0041-northbridge-amd-amdmct-Read-SPD-data-into-cache-to-d.patch index d70b895..23c1b3d 100644 --- a/resources/libreboot/patch/kgpe-d16/0040-northbridge-amd-amdmct-Read-SPD-data-into-cache-to-d.patch +++ b/resources/libreboot/patch/kgpe-d16/0041-northbridge-amd-amdmct-Read-SPD-data-into-cache-to-d.patch @@ -1,14 +1,14 @@ -From f26e90bcbbd7b5966ac353a7e7ba63fa188ffac0 Mon Sep 17 00:00:00 2001 +From 6f89a93a630dac9cd6588c69040f81c9ddebb0df Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Tue, 2 Jun 2015 20:51:59 -0500 -Subject: [PATCH 040/139] northbridge/amd/amdmct: Read SPD data into cache to +Subject: [PATCH 041/143] northbridge/amd/amdmct: Read SPD data into cache to decrease bootup time Change-Id: Ic16a927a3f1fc6f7cb1aea36a8abe8cc1999cb52 Signed-off-by: Timothy Pearson --- - src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 161 +++++++++++++++------------- - src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 7 ++ + src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 161 ++++++++++++++------------- + src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 7 ++ 2 files changed, 92 insertions(+), 76 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -457,5 +457,5 @@ index 50fbff7..5bb09b4 100644 struct amd_s3_persistent_mct_channel_data { -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0041-cpu-amd-car-Initialize-entire-CAR-space-instead-of-o.patch b/resources/libreboot/patch/kgpe-d16/0042-cpu-amd-car-Initialize-entire-CAR-space-instead-of-o.patch index ced4d6e..aed4b9d 100644 --- a/resources/libreboot/patch/kgpe-d16/0041-cpu-amd-car-Initialize-entire-CAR-space-instead-of-o.patch +++ b/resources/libreboot/patch/kgpe-d16/0042-cpu-amd-car-Initialize-entire-CAR-space-instead-of-o.patch @@ -1,13 +1,13 @@ -From 25cdb73c425c4f6a074308a69e0225ea2ee657ab Mon Sep 17 00:00:00 2001 +From 60a55771f802ef5c3fa3b080e7d130ca24acab45 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Thu, 4 Jun 2015 00:07:05 -0500 -Subject: [PATCH 041/139] cpu/amd/car: Initialize entire CAR space instead of +Subject: [PATCH 042/143] cpu/amd/car: Initialize entire CAR space instead of only half Change-Id: If2b6c875e523f595e662d5d62322c3c3f96ccb4a Signed-off-by: Timothy Pearson --- - src/cpu/amd/car/cache_as_ram.inc | 4 ++-- + src/cpu/amd/car/cache_as_ram.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc @@ -30,5 +30,5 @@ index 4ccde3f..9edc41f 100644 rep stosl -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0042-amd-amdmct-mct_ddr3-Improve-SPD-DIMM-detect-reliabil.patch b/resources/libreboot/patch/kgpe-d16/0043-amd-amdmct-mct_ddr3-Improve-SPD-DIMM-detect-reliabil.patch index d0f9f58..8445869 100644 --- a/resources/libreboot/patch/kgpe-d16/0042-amd-amdmct-mct_ddr3-Improve-SPD-DIMM-detect-reliabil.patch +++ b/resources/libreboot/patch/kgpe-d16/0043-amd-amdmct-mct_ddr3-Improve-SPD-DIMM-detect-reliabil.patch @@ -1,13 +1,13 @@ -From 32a016ee1dea33731b9994fe23a4c43421006f99 Mon Sep 17 00:00:00 2001 +From 3333f1b6ab84234f51aa901ec29cdc6d7f0998c5 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Thu, 4 Jun 2015 00:10:03 -0500 -Subject: [PATCH 042/139] amd/amdmct/mct_ddr3: Improve SPD DIMM detect +Subject: [PATCH 043/143] amd/amdmct/mct_ddr3: Improve SPD DIMM detect reliability Change-Id: Ifab63eca2233c63a6a42ab8b7e742f8e47fb2a09 Signed-off-by: Timothy Pearson --- - src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 13 ++++++++++++- + src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -45,5 +45,5 @@ index 5344ff9..e60adb7 100644 if (byte == JED_DDR3SDRAM) { /*Dimm is 'Present'*/ -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0043-amd-amdmct-mct_ddr3-Use-training-values-from-previou.patch b/resources/libreboot/patch/kgpe-d16/0044-amd-amdmct-mct_ddr3-Use-training-values-from-previou.patch index 8884130..e1c7c3f 100644 --- a/resources/libreboot/patch/kgpe-d16/0043-amd-amdmct-mct_ddr3-Use-training-values-from-previou.patch +++ b/resources/libreboot/patch/kgpe-d16/0044-amd-amdmct-mct_ddr3-Use-training-values-from-previou.patch @@ -1,7 +1,7 @@ -From dbe04aaef5ba56c90824eb62aea47e281b75149f Mon Sep 17 00:00:00 2001 +From d95a5bb7caa2d95f531ff529269509b9c38bbf72 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Thu, 4 Jun 2015 00:11:03 -0500 -Subject: [PATCH 043/139] amd/amdmct/mct_ddr3: Use training values from +Subject: [PATCH 044/143] amd/amdmct/mct_ddr3: Use training values from previous boot if possible DRAM training accounts for most of the romstage startup time, yet @@ -12,12 +12,12 @@ if the DIMM configuration has not changed since the last boot. Change-Id: I37ed277b16476d38e4af76c6ae827a575c6b017d Signed-off-by: Timothy Pearson --- - src/mainboard/asus/kgpe-d16/cmos.layout | 1 + - src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 206 +++++++++++++++++--------- - src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 6 + - src/northbridge/amd/amdmct/mct_ddr3/s3utils.c | 175 +++++++++++++++++++--- - src/northbridge/amd/amdmct/mct_ddr3/s3utils.h | 10 +- - src/northbridge/amd/amdmct/wrappers/mcti_d.c | 4 + + src/mainboard/asus/kgpe-d16/cmos.layout | 1 + + src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 206 +++++++++++++++++-------- + src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 6 + + src/northbridge/amd/amdmct/mct_ddr3/s3utils.c | 175 ++++++++++++++++++--- + src/northbridge/amd/amdmct/mct_ddr3/s3utils.h | 10 +- + src/northbridge/amd/amdmct/wrappers/mcti_d.c | 4 + 6 files changed, 308 insertions(+), 94 deletions(-) diff --git a/src/mainboard/asus/kgpe-d16/cmos.layout b/src/mainboard/asus/kgpe-d16/cmos.layout @@ -754,10 +754,10 @@ index dcddcad..82f73a7 100644 +void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persistent_data, uint8_t training_only); \ No newline at end of file diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c -index 1d4eade..af34d3b 100644 +index 9969c4f..5ca8eac 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c -@@ -399,14 +399,18 @@ static void mctHookAfterCPU(void) +@@ -400,14 +400,18 @@ static void mctHookAfterCPU(void) } @@ -777,5 +777,5 @@ index 1d4eade..af34d3b 100644 static void mctHookBeforeECC(void) -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0044-northbridge-amd-amdfam10-Enable-CC6-DRAM-save-area-s.patch b/resources/libreboot/patch/kgpe-d16/0045-northbridge-amd-amdfam10-Enable-CC6-DRAM-save-area-s.patch index 9ed1c3d..1437a1f 100644 --- a/resources/libreboot/patch/kgpe-d16/0044-northbridge-amd-amdfam10-Enable-CC6-DRAM-save-area-s.patch +++ b/resources/libreboot/patch/kgpe-d16/0045-northbridge-amd-amdfam10-Enable-CC6-DRAM-save-area-s.patch @@ -1,18 +1,18 @@ -From a8478c829628eb43b1222ad981600ff742d271e8 Mon Sep 17 00:00:00 2001 +From a43c033cd8bcfd0742d1f52847c09bef8280b5f3 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Fri, 5 Jun 2015 21:13:30 -0500 -Subject: [PATCH 044/139] northbridge/amd/amdfam10: Enable CC6 DRAM save area +Subject: [PATCH 045/143] northbridge/amd/amdfam10: Enable CC6 DRAM save area setup Change-Id: Ibeb35da3395dc77a21a2f92f0e1d0845be53d175 Signed-off-by: Timothy Pearson --- - src/northbridge/amd/amdfam10/northbridge.c | 70 +++++++++++++++ - src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 132 ++++++++++++++++++++++++++++ + src/northbridge/amd/amdfam10/northbridge.c | 70 ++++++++++++++ + src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 132 +++++++++++++++++++++++++++ 2 files changed, 202 insertions(+) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c -index baf77d6..51eac77 100644 +index fcf85a7..e5612fa 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -706,6 +706,8 @@ struct chip_operations northbridge_amd_amdfam10_ops = { @@ -257,5 +257,5 @@ index 20e66f2..2798506 100644 printk(BIOS_DEBUG, "mctAutoInitMCT_D Done: Global Status: %x\n", pMCTstat->GStatus); } -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0045-mainboard-asus-kgpe-d16-Enable-CC6.patch b/resources/libreboot/patch/kgpe-d16/0046-mainboard-asus-kgpe-d16-Enable-CC6.patch index 26ddad6..f11eca2 100644 --- a/resources/libreboot/patch/kgpe-d16/0045-mainboard-asus-kgpe-d16-Enable-CC6.patch +++ b/resources/libreboot/patch/kgpe-d16/0046-mainboard-asus-kgpe-d16-Enable-CC6.patch @@ -1,14 +1,14 @@ -From 32b3afadc08bd155e25b12a0af8b11b629c064c3 Mon Sep 17 00:00:00 2001 +From 9517e40030e0b2a648df74095d705ed85a6b7f09 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Fri, 5 Jun 2015 21:14:23 -0500 -Subject: [PATCH 045/139] mainboard/asus/kgpe-d16: Enable CC6 +Subject: [PATCH 046/143] mainboard/asus/kgpe-d16: Enable CC6 Change-Id: Iae1cbe7d3a6471561abfdb8e182bc764c38bb222 Signed-off-by: Timothy Pearson --- - src/mainboard/asus/kgpe-d16/cmos.default | 1 + - src/mainboard/asus/kgpe-d16/cmos.layout | 3 ++- - src/northbridge/amd/amdmct/mct_ddr3/s3utils.c | 10 +++++++++- + src/mainboard/asus/kgpe-d16/cmos.default | 1 + + src/mainboard/asus/kgpe-d16/cmos.layout | 3 ++- + src/northbridge/amd/amdmct/mct_ddr3/s3utils.c | 10 +++++++++- 3 files changed, 12 insertions(+), 2 deletions(-) diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default @@ -66,5 +66,5 @@ index fa1873a..83c7b02 100644 } } -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0046-cpu-amd-Add-CC6-support.patch b/resources/libreboot/patch/kgpe-d16/0047-cpu-amd-Add-CC6-support.patch index 026d843..e063019 100644 --- a/resources/libreboot/patch/kgpe-d16/0046-cpu-amd-Add-CC6-support.patch +++ b/resources/libreboot/patch/kgpe-d16/0047-cpu-amd-Add-CC6-support.patch @@ -1,32 +1,32 @@ -From 674911f61b4b32b0707962fa6a5a7e50811f721a Mon Sep 17 00:00:00 2001 +From 8f0d565329ddc702412d6941a5a0fea7c81e73e8 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Mon, 8 Jun 2015 19:35:06 -0500 -Subject: [PATCH 046/139] cpu/amd: Add CC6 support +Subject: [PATCH 047/143] cpu/amd: Add CC6 support Change-Id: I44ce157cda97fb85f3e8f3d7262d4712b5410670 Signed-off-by: Timothy Pearson --- - src/arch/x86/acpigen.c | 26 +++- - src/arch/x86/include/arch/acpigen.h | 3 + - src/cpu/amd/family_10h-family_15h/fidvid.c | 170 +++++++++++----------- - src/cpu/amd/family_10h-family_15h/init_cpus.c | 80 ++++++++++ - src/cpu/amd/family_10h-family_15h/powernow_acpi.c | 135 +++++++++++++++-- - src/include/cpu/amd/powernow.h | 2 + - src/mainboard/asus/kgpe-d16/cmos.default | 1 + - src/mainboard/asus/kgpe-d16/cmos.layout | 5 +- - src/northbridge/amd/amdfam10/link_control.c | 78 ++++++++++ - src/northbridge/amd/amdfam10/northbridge.c | 58 ++++---- - src/northbridge/amd/amdht/AsPsDefs.h | 3 +- - src/northbridge/amd/amdmct/amddefs.h | 66 +++++---- - src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 57 +++++--- - src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 8 + - src/southbridge/amd/sb700/early_setup.c | 20 ++- - src/southbridge/amd/sb700/fadt.c | 4 + - src/southbridge/amd/sb700/sb700.h | 7 +- - src/southbridge/amd/sb700/sm.c | 5 +- - src/southbridge/amd/sb800/fadt.c | 3 + - src/southbridge/amd/sb800/sb800.h | 8 +- - 20 files changed, 539 insertions(+), 200 deletions(-) + src/arch/x86/acpigen.c | 26 +++- + src/arch/x86/include/arch/acpigen.h | 3 + + src/cpu/amd/family_10h-family_15h/fidvid.c | 170 ++++++++++----------- + src/cpu/amd/family_10h-family_15h/init_cpus.c | 81 ++++++++++ + src/cpu/amd/family_10h-family_15h/powernow_acpi.c | 135 ++++++++++++++-- + src/include/cpu/amd/powernow.h | 2 + + src/mainboard/asus/kgpe-d16/cmos.default | 1 + + src/mainboard/asus/kgpe-d16/cmos.layout | 5 +- + src/northbridge/amd/amdfam10/link_control.c | 81 +++++++++- + src/northbridge/amd/amdfam10/northbridge.c | 58 ++++--- + src/northbridge/amd/amdht/AsPsDefs.h | 3 +- + src/northbridge/amd/amdmct/amddefs.h | 66 ++++---- + src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 57 ++++--- + src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 8 + + src/southbridge/amd/sb700/early_setup.c | 20 ++- + src/southbridge/amd/sb700/fadt.c | 5 + + src/southbridge/amd/sb700/sb700.h | 7 +- + src/southbridge/amd/sb700/sm.c | 5 +- + src/southbridge/amd/sb800/fadt.c | 4 + + src/southbridge/amd/sb800/sb800.h | 8 +- + 20 files changed, 544 insertions(+), 201 deletions(-) diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index 3aa823c..4136e65 100644 @@ -119,7 +119,7 @@ index a3e65eb..8e50960 100644 void acpigen_write_TSS_package(int entries, acpi_tstate_t *tstate_list); void acpigen_write_TSD_package(u32 domain, u32 numprocs, PSD_coord coordtype); diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c -index 2e26645..0e870e3 100644 +index e8e0818..0e7d299 100644 --- a/src/cpu/amd/family_10h-family_15h/fidvid.c +++ b/src/cpu/amd/family_10h-family_15h/fidvid.c @@ -169,87 +169,87 @@ static void applyBoostFIDOffset(device_t dev, uint32_t nodeid) { @@ -348,7 +348,7 @@ index 2e26645..0e870e3 100644 }; diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c -index aced850..818431b 100644 +index aced850..061bba2 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -30,6 +30,14 @@ @@ -366,20 +366,21 @@ index aced850..818431b 100644 #if IS_ENABLED(CONFIG_SET_FIDVID) static void prep_fid_change(void); static void init_fidvid_stage2(u32 apicid, u32 nodeid); -@@ -874,6 +882,8 @@ void cpuSetAMDMSR(uint8_t node_id) +@@ -874,6 +882,7 @@ void cpuSetAMDMSR(uint8_t node_id) u8 i; u32 platform; uint64_t revision; -+ uint8_t nvram; + uint8_t enable_c_states; printk(BIOS_DEBUG, "cpuSetAMDMSR "); -@@ -936,6 +946,42 @@ void cpuSetAMDMSR(uint8_t node_id) +@@ -936,6 +945,44 @@ void cpuSetAMDMSR(uint8_t node_id) wrmsr(FP_CFG, msr); } +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB800) ++ uint8_t nvram; ++ + if (revision & (AMD_DR_GT_D0 | AMD_FAM15_ALL)) { + /* Set up message triggered C1E */ + msr = rdmsr(0xc0010055); @@ -418,7 +419,7 @@ index aced850..818431b 100644 printk(BIOS_DEBUG, " done\n"); } -@@ -950,6 +996,7 @@ static void cpuSetAMDPCI(u8 node) +@@ -950,6 +997,7 @@ static void cpuSetAMDPCI(u8 node) u32 platform; u32 val; u8 offset; @@ -426,7 +427,7 @@ index aced850..818431b 100644 uint64_t revision; printk(BIOS_DEBUG, "cpuSetAMDPCI %02d", node); -@@ -1008,6 +1055,39 @@ static void cpuSetAMDPCI(u8 node) +@@ -1008,6 +1056,39 @@ static void cpuSetAMDPCI(u8 node) if (revision & (AMD_DR_B2 | AMD_DR_B3)) dctPhyDiag(); */ @@ -714,14 +715,13 @@ index 630219e..7f9f661 100644 728 256 h 0 user_data 984 16 h 0 check_sum diff --git a/src/northbridge/amd/amdfam10/link_control.c b/src/northbridge/amd/amdfam10/link_control.c -index 1091ef4..4acd66c 100644 +index 1091ef4..7fa9f12 100644 --- a/src/northbridge/amd/amdfam10/link_control.c +++ b/src/northbridge/amd/amdfam10/link_control.c -@@ -49,15 +49,93 @@ static inline uint8_t is_fam15h(void) +@@ -49,15 +49,94 @@ static inline uint8_t is_fam15h(void) static void nb_control_init(struct device *dev) { -+ uint8_t nvram; + uint8_t enable_c_states; + uint8_t enable_cc6; uint32_t dword; @@ -767,6 +767,8 @@ index 1091ef4..4acd66c 100644 + enable_c_states = 0; + enable_cc6 = 0; +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) ++ uint8_t nvram; ++ + if (get_option(&nvram, "cpu_c_states") == CB_SUCCESS) + enable_c_states = !!nvram; + @@ -811,8 +813,15 @@ index 1091ef4..4acd66c 100644 } printk(BIOS_DEBUG, "done.\n"); +@@ -83,4 +162,4 @@ static const struct pci_driver mcf4_driver_fam15 __pci_driver = { + .ops = &mcf4_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = 0x1604, +-}; +\ No newline at end of file ++}; diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c -index 51eac77..3fc31c0 100644 +index e5612fa..9fe0ccb 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -770,53 +770,49 @@ static void amdfam10_domain_read_resources(device_t dev) @@ -1193,7 +1202,7 @@ index a6849b0..fd3b099 100644 // /* Enable automatic C1e state switch */ // byte = pmio_read(0xc9); diff --git a/src/southbridge/amd/sb700/fadt.c b/src/southbridge/amd/sb700/fadt.c -index 96996a3..6b1924f 100644 +index 96996a3..e860016 100644 --- a/src/southbridge/amd/sb700/fadt.c +++ b/src/southbridge/amd/sb700/fadt.c @@ -2,6 +2,7 @@ @@ -1212,11 +1221,12 @@ index 96996a3..6b1924f 100644 #include "sb700.h" void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -@@ -156,5 +158,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +@@ -156,5 +158,8 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->x_gpe1_blk.addrl = 0; fadt->x_gpe1_blk.addrh = 0x0; -+ amd_powernow_update_fadt(fadt); ++ if (IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX)) ++ amd_powernow_update_fadt(fadt); + header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); } @@ -1240,10 +1250,10 @@ index b477091..941a4fd 100644 extern void pm_iowrite(u8 reg, u8 value); extern u8 pm_ioread(u8 reg); diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c -index a4b78d0..81e3046 100644 +index 71253b5..5bd49c5 100644 --- a/src/southbridge/amd/sb700/sm.c +++ b/src/southbridge/amd/sb700/sm.c -@@ -114,7 +114,10 @@ static void sm_init(device_t dev) +@@ -117,7 +117,10 @@ static void sm_init(device_t dev) pci_write_config8(dev, 0x41, byte); byte = pm_ioread(0x61); @@ -1256,7 +1266,7 @@ index a4b78d0..81e3046 100644 /* disable SMI */ diff --git a/src/southbridge/amd/sb800/fadt.c b/src/southbridge/amd/sb800/fadt.c -index fea98f9..5250e20 100644 +index fea98f9..30b4496 100644 --- a/src/southbridge/amd/sb800/fadt.c +++ b/src/southbridge/amd/sb800/fadt.c @@ -26,6 +26,7 @@ @@ -1267,11 +1277,12 @@ index fea98f9..5250e20 100644 #include "sb800.h" void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -@@ -156,5 +157,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +@@ -156,5 +157,8 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->x_gpe1_blk.addrl = 0; fadt->x_gpe1_blk.addrh = 0x0; -+ amd_powernow_update_fadt(fadt); ++ if (IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX)) ++ amd_powernow_update_fadt(fadt); + header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); } @@ -1303,5 +1314,5 @@ index 9049182..3e3f077 100644 void pm_iowrite(u8 reg, u8 value); u8 pm_ioread(u8 reg); -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0047-northbridge-amd-amdmct-Skip-DCT-config-write-to-Flas.patch b/resources/libreboot/patch/kgpe-d16/0048-northbridge-amd-amdmct-Skip-DCT-config-write-to-Flas.patch index 8bd1471..a3de30d 100644 --- a/resources/libreboot/patch/kgpe-d16/0047-northbridge-amd-amdmct-Skip-DCT-config-write-to-Flas.patch +++ b/resources/libreboot/patch/kgpe-d16/0048-northbridge-amd-amdmct-Skip-DCT-config-write-to-Flas.patch @@ -1,15 +1,15 @@ -From cac705ed59bc27d7eacdfdc16ed3c762fd41e84f Mon Sep 17 00:00:00 2001 +From e513231d8e07299c740ef0cb8750816d5ac69998 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Mon, 8 Jun 2015 19:54:56 -0500 -Subject: [PATCH 047/139] northbridge/amd/amdmct: Skip DCT config write to +Subject: [PATCH 048/143] northbridge/amd/amdmct: Skip DCT config write to Flash if unchanged Change-Id: I5fee5f5fdf30ab6e3c4f94ed3e54ea66c1204352 Signed-off-by: Timothy Pearson --- - src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 3 +++ - src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 1 + - src/northbridge/amd/amdmct/mct_ddr3/s3utils.c | 21 +++++++++++++++++++-- + src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 3 +++ + src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 1 + + src/northbridge/amd/amdmct/mct_ddr3/s3utils.c | 21 +++++++++++++++++++-- 3 files changed, 23 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -99,5 +99,5 @@ index 83c7b02..1e5c1a0 100644 /* Obtain CBFS file offset */ s3nv_offset = get_s3nv_file_offset(); -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0048-southbridge-amd-sb700-Add-AHCI-support.patch b/resources/libreboot/patch/kgpe-d16/0049-southbridge-amd-sb700-Add-AHCI-support.patch index ed4bd52..7f5d402 100644 --- a/resources/libreboot/patch/kgpe-d16/0048-southbridge-amd-sb700-Add-AHCI-support.patch +++ b/resources/libreboot/patch/kgpe-d16/0049-southbridge-amd-sb700-Add-AHCI-support.patch @@ -1,20 +1,20 @@ -From 5c3cca2a8c938c140d6d217fd3fa9a646713678c Mon Sep 17 00:00:00 2001 +From 2ddaf32b63d12d630da6726ba6fa46caa0e5940f Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Tue, 9 Jun 2015 18:09:50 -0500 -Subject: [PATCH 048/139] southbridge/amd/sb700: Add AHCI support +Subject: [PATCH 049/143] southbridge/amd/sb700: Add AHCI support Change-Id: I147284e6a435f4b96d6821a122c1f4f9ddc2ea33 Signed-off-by: Timothy Pearson --- - src/include/device/pci_ids.h | 2 + - src/mainboard/asus/kgpe-d16/Kconfig | 4 + - src/mainboard/asus/kgpe-d16/cmos.default | 1 + - src/mainboard/asus/kgpe-d16/cmos.layout | 3 +- - src/southbridge/amd/sb700/Kconfig | 4 + - src/southbridge/amd/sb700/early_setup.c | 73 ++++++--- - src/southbridge/amd/sb700/ide.c | 42 +++-- - src/southbridge/amd/sb700/sata.c | 256 +++++++++++++++++++++---------- - src/southbridge/amd/sb800/fadt.c | 1 + + src/include/device/pci_ids.h | 2 + + src/mainboard/asus/kgpe-d16/Kconfig | 4 + + src/mainboard/asus/kgpe-d16/cmos.default | 1 + + src/mainboard/asus/kgpe-d16/cmos.layout | 3 +- + src/southbridge/amd/sb700/Kconfig | 4 + + src/southbridge/amd/sb700/early_setup.c | 73 ++++++--- + src/southbridge/amd/sb700/ide.c | 42 +++-- + src/southbridge/amd/sb700/sata.c | 256 ++++++++++++++++++++---------- + src/southbridge/amd/sb800/fadt.c | 1 + 9 files changed, 267 insertions(+), 119 deletions(-) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h @@ -72,7 +72,7 @@ index 7f9f661..247fd7b 100644 728 256 h 0 user_data 984 16 h 0 check_sum diff --git a/src/southbridge/amd/sb700/Kconfig b/src/southbridge/amd/sb700/Kconfig -index f56f84a..92fb9ab 100644 +index bca74fb..05eac5f 100644 --- a/src/southbridge/amd/sb700/Kconfig +++ b/src/southbridge/amd/sb700/Kconfig @@ -46,6 +46,10 @@ config SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA @@ -640,7 +640,7 @@ index 172ad36..d97288a 100644 + .device = PCI_DEVICE_ID_ATI_SB700_SATA_AHCI_AMD, +}; diff --git a/src/southbridge/amd/sb800/fadt.c b/src/southbridge/amd/sb800/fadt.c -index 5250e20..95e3354 100644 +index 30b4496..5eb83d7 100644 --- a/src/southbridge/amd/sb800/fadt.c +++ b/src/southbridge/amd/sb800/fadt.c @@ -2,6 +2,7 @@ @@ -652,5 +652,5 @@ index 5250e20..95e3354 100644 * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0049-mainboard-asus-kgpe-d16-Properly-initialize-SB700-SA.patch b/resources/libreboot/patch/kgpe-d16/0050-mainboard-asus-kgpe-d16-Properly-initialize-SB700-SA.patch index 28bdf5f..6788b6f 100644 --- a/resources/libreboot/patch/kgpe-d16/0049-mainboard-asus-kgpe-d16-Properly-initialize-SB700-SA.patch +++ b/resources/libreboot/patch/kgpe-d16/0050-mainboard-asus-kgpe-d16-Properly-initialize-SB700-SA.patch @@ -1,13 +1,13 @@ -From 8402270ff9ebd9f118f28daa2eda5d3852843a32 Mon Sep 17 00:00:00 2001 +From b67e436ab3de506fe4421ccd2bd2e50f0e3ad652 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Tue, 9 Jun 2015 18:57:23 -0500 -Subject: [PATCH 049/139] mainboard/asus/kgpe-d16: Properly initialize SB700 +Subject: [PATCH 050/143] mainboard/asus/kgpe-d16: Properly initialize SB700 SATA PHYs Change-Id: I5323462dcb8a4e84786be38cc85070eb48d4a31d Signed-off-by: Timothy Pearson --- - src/mainboard/asus/kgpe-d16/mainboard.c | 23 +++++++++++++++++++++++ + src/mainboard/asus/kgpe-d16/mainboard.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/src/mainboard/asus/kgpe-d16/mainboard.c b/src/mainboard/asus/kgpe-d16/mainboard.c @@ -45,5 +45,5 @@ index 47ede34..8de6f26 100644 .enable_dev = mainboard_enable, }; -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0050-southbridge-amd-sb700-Disable-broken-SATA-MSI-functi.patch b/resources/libreboot/patch/kgpe-d16/0051-southbridge-amd-sb700-Disable-broken-SATA-MSI-functi.patch index 8bc23ec..98ef19d 100644 --- a/resources/libreboot/patch/kgpe-d16/0050-southbridge-amd-sb700-Disable-broken-SATA-MSI-functi.patch +++ b/resources/libreboot/patch/kgpe-d16/0051-southbridge-amd-sb700-Disable-broken-SATA-MSI-functi.patch @@ -1,13 +1,13 @@ -From 77b9c8b935e51ba8eb779fcf050f8ac407d0c4f3 Mon Sep 17 00:00:00 2001 +From 178c14e07187ad4315db638af03fb6593f147c4f Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Tue, 9 Jun 2015 19:12:35 -0500 -Subject: [PATCH 050/139] southbridge/amd/sb700: Disable broken SATA MSI +Subject: [PATCH 051/143] southbridge/amd/sb700: Disable broken SATA MSI functionality Change-Id: I4e0a52eb90910604f8640ad7533b5d71be6c8e20 Signed-off-by: Timothy Pearson --- - src/southbridge/amd/sb700/early_setup.c | 7 ++++--- + src/southbridge/amd/sb700/early_setup.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c @@ -37,5 +37,5 @@ index a06a72f..da03961 100644 pci_write_config8(dev, 0x40, byte); } -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0051-southbridge-amd-sb700-Indicate-iSATA-eSATA-port-type.patch b/resources/libreboot/patch/kgpe-d16/0052-southbridge-amd-sb700-Indicate-iSATA-eSATA-port-type.patch index e2dda8b..a53e25e 100644 --- a/resources/libreboot/patch/kgpe-d16/0051-southbridge-amd-sb700-Indicate-iSATA-eSATA-port-type.patch +++ b/resources/libreboot/patch/kgpe-d16/0052-southbridge-amd-sb700-Indicate-iSATA-eSATA-port-type.patch @@ -1,14 +1,15 @@ -From 2480454b78d3ad98e1107f07bcd8175b80b69219 Mon Sep 17 00:00:00 2001 +From 0092df93ab131ead3c4f738e35a8371c603f9f83 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Tue, 9 Jun 2015 19:34:16 -0500 -Subject: [PATCH 051/139] southbridge/amd/sb700: Indicate iSATA/eSATA port type +Subject: [PATCH 052/143] southbridge/amd/sb700: Indicate iSATA/eSATA port + type Change-Id: I8ee757d07c82c151b36def6b709163ff144d244f Signed-off-by: Timothy Pearson --- - src/mainboard/asus/kgpe-d16/mainboard.c | 16 ++++++++++++++++ - src/southbridge/amd/sb700/sata.c | 19 +++++++++++++++++++ - src/southbridge/amd/sb700/sb700.h | 1 + + src/mainboard/asus/kgpe-d16/mainboard.c | 16 ++++++++++++++++ + src/southbridge/amd/sb700/sata.c | 19 +++++++++++++++++++ + src/southbridge/amd/sb700/sb700.h | 1 + 3 files changed, 36 insertions(+) diff --git a/src/mainboard/asus/kgpe-d16/mainboard.c b/src/mainboard/asus/kgpe-d16/mainboard.c @@ -89,5 +90,5 @@ index 941a4fd..8f792e7 100644 #endif -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0052-northbridge-amd-amdfam10-Add-ability-to-set-maximum-.patch b/resources/libreboot/patch/kgpe-d16/0053-northbridge-amd-amdfam10-Add-ability-to-set-maximum-.patch index 909f3df..7f45663 100644 --- a/resources/libreboot/patch/kgpe-d16/0052-northbridge-amd-amdfam10-Add-ability-to-set-maximum-.patch +++ b/resources/libreboot/patch/kgpe-d16/0053-northbridge-amd-amdfam10-Add-ability-to-set-maximum-.patch @@ -1,15 +1,15 @@ -From f12fffe558a4ffd6ea77eadac08a2292ce2d8c96 Mon Sep 17 00:00:00 2001 +From 1103d319eede186dc340a9c1701432f3ff33c468 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Wed, 10 Jun 2015 00:35:05 -0500 -Subject: [PATCH 052/139] northbridge/amd/amdfam10: Add ability to set maximum +Subject: [PATCH 053/143] northbridge/amd/amdfam10: Add ability to set maximum P-state limit Change-Id: Ifdbb1ad11a856f855c59702ae0ee99e95b08520e Signed-off-by: Timothy Pearson --- - src/mainboard/asus/kgpe-d16/cmos.default | 1 + - src/mainboard/asus/kgpe-d16/cmos.layout | 3 ++- - src/northbridge/amd/amdfam10/misc_control.c | 24 ++++++++++++++++++++---- + src/mainboard/asus/kgpe-d16/cmos.default | 1 + + src/mainboard/asus/kgpe-d16/cmos.layout | 3 ++- + src/northbridge/amd/amdfam10/misc_control.c | 24 ++++++++++++++++++++---- 3 files changed, 23 insertions(+), 5 deletions(-) diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default @@ -80,5 +80,5 @@ index 8777e8f..703ae51 100644 printk(BIOS_DEBUG, "done.\n"); } -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0053-northbridge-amd-amdmct-Verify-MCT-NVRAM-options-befo.patch b/resources/libreboot/patch/kgpe-d16/0054-northbridge-amd-amdmct-Verify-MCT-NVRAM-options-befo.patch index 2d97530..b7eead1 100644 --- a/resources/libreboot/patch/kgpe-d16/0053-northbridge-amd-amdmct-Verify-MCT-NVRAM-options-befo.patch +++ b/resources/libreboot/patch/kgpe-d16/0054-northbridge-amd-amdmct-Verify-MCT-NVRAM-options-befo.patch @@ -1,16 +1,16 @@ -From 5ae82615bbd3e9a7a5f6d7b5c7c203b0a780c554 Mon Sep 17 00:00:00 2001 +From fdb1ff9b466c0fb32c019ceeeeefb23e857cf00e Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Wed, 10 Jun 2015 10:46:17 -0500 -Subject: [PATCH 053/139] northbridge/amd/amdmct: Verify MCT NVRAM options +Subject: [PATCH 054/143] northbridge/amd/amdmct: Verify MCT NVRAM options before skipping training Change-Id: If26e5d148a906d63bd1407b8ffa58f08ae6b4275 Signed-off-by: Timothy Pearson --- - src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 9 ++++++- - src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 2 ++ - src/northbridge/amd/amdmct/mct_ddr3/s3utils.c | 36 ++++++++++++++++++++++++++- - src/northbridge/amd/amdmct/mct_ddr3/s3utils.h | 3 ++- + src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 9 ++++++- + src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 2 ++ + src/northbridge/amd/amdmct/mct_ddr3/s3utils.c | 36 ++++++++++++++++++++++++- + src/northbridge/amd/amdmct/mct_ddr3/s3utils.h | 3 ++- 4 files changed, 47 insertions(+), 3 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -145,5 +145,5 @@ index 82f73a7..74922c4 100644 #ifdef __RAMSTAGE__ -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0054-src-northbridge-amd-amdmct-Add-option-to-override-ba.patch b/resources/libreboot/patch/kgpe-d16/0055-src-northbridge-amd-amdmct-Add-option-to-override-ba.patch index 4bbc1c7..b41d65e 100644 --- a/resources/libreboot/patch/kgpe-d16/0054-src-northbridge-amd-amdmct-Add-option-to-override-ba.patch +++ b/resources/libreboot/patch/kgpe-d16/0055-src-northbridge-amd-amdmct-Add-option-to-override-ba.patch @@ -1,17 +1,17 @@ -From da111dc0736f1101683c5e596fdfed46fd48717d Mon Sep 17 00:00:00 2001 +From 0609ebe6ead8e3024e9ceeba7b46817ff6fc47a8 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Thu, 11 Jun 2015 16:14:15 -0500 -Subject: [PATCH 054/139] src/northbridge/amd/amdmct: Add option to override +Subject: [PATCH 055/143] src/northbridge/amd/amdmct: Add option to override bad SPD checksum Change-Id: Ia743a13348d0a6e5e4dfffa04ed9582e0f7f3dad Signed-off-by: Timothy Pearson --- - src/mainboard/asus/kgpe-d16/cmos.default | 1 + - src/mainboard/asus/kgpe-d16/cmos.layout | 7 ++++++- - src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 5 +++-- - src/northbridge/amd/amdmct/wrappers/mcti_d.c | 8 ++++++++ - 4 files changed, 18 insertions(+), 3 deletions(-) + src/mainboard/asus/kgpe-d16/cmos.default | 1 + + src/mainboard/asus/kgpe-d16/cmos.layout | 6 +++++- + src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 5 +++-- + src/northbridge/amd/amdmct/wrappers/mcti_d.c | 8 ++++++++ + 4 files changed, 17 insertions(+), 3 deletions(-) diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default index a52b7fa..73f2a38 100644 @@ -26,10 +26,10 @@ index a52b7fa..73f2a38 100644 ECC_redirection = Enable ecc_scrub_rate = 1.28us diff --git a/src/mainboard/asus/kgpe-d16/cmos.layout b/src/mainboard/asus/kgpe-d16/cmos.layout -index 307bddc..e91568c 100644 +index 307bddc..068eaf4 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.layout +++ b/src/mainboard/asus/kgpe-d16/cmos.layout -@@ -47,8 +47,10 @@ entries +@@ -47,7 +47,8 @@ entries 466 1 e 1 cpu_cc6_state 467 1 e 1 sata_ahci_mode 468 4 h 0 maximum_p_state_limit @@ -37,11 +37,9 @@ index 307bddc..e91568c 100644 +472 2 e 13 dimm_spd_checksum +474 1 r 0 allow_spd_nvram_cache_restore 477 1 e 1 ieee1394 -+>>>>>>> bed9a97... src/northbridge/amd/amdmct: Add option to override bad SPD checksum 728 256 h 0 user_data 984 16 h 0 check_sum - # Reserve the extended AMD configuration registers -@@ -142,6 +144,9 @@ enumerations +@@ -142,6 +143,9 @@ enumerations 12 1 1.35V 12 2 1.25V 12 3 1.15V @@ -81,7 +79,7 @@ index 4d7e5aa..f4859d0 100644 if (SPDCtrl == 0) { pDCTstat->ErrStatus |= 1 << SB_DIMMChkSum; diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c -index af34d3b..86a0b14 100644 +index 5ca8eac..3053d58 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -150,6 +150,14 @@ static u16 mctGet_NVbits(u8 index) @@ -100,5 +98,5 @@ index af34d3b..86a0b14 100644 case NV_DQSTrainCTL: //val = 0; /*Skip dqs training */ -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0055-mainboard-asus-kgpe-d16-Add-missing-IRQ-routing-for-.patch b/resources/libreboot/patch/kgpe-d16/0056-mainboard-asus-kgpe-d16-Add-missing-IRQ-routing-for-.patch index 518947d..1a0b92a 100644 --- a/resources/libreboot/patch/kgpe-d16/0055-mainboard-asus-kgpe-d16-Add-missing-IRQ-routing-for-.patch +++ b/resources/libreboot/patch/kgpe-d16/0056-mainboard-asus-kgpe-d16-Add-missing-IRQ-routing-for-.patch @@ -1,13 +1,13 @@ -From ffdb5fd36669b7f722d46777f421d4ee37005f1c Mon Sep 17 00:00:00 2001 +From a4b96f105cfdefd258e743eebe920b9fc6dd3d24 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Fri, 12 Jun 2015 13:32:52 -0500 -Subject: [PATCH 055/139] mainboard/asus/kgpe-d16: Add missing IRQ routing for +Subject: [PATCH 056/143] mainboard/asus/kgpe-d16: Add missing IRQ routing for PIKE card Change-Id: I6eba36dad71a2a2713181382484dc0e0976e1dad Signed-off-by: Timothy Pearson --- - src/mainboard/asus/kgpe-d16/dsdt.asl | 74 +++++++++++++++++++++++++++--------- + src/mainboard/asus/kgpe-d16/dsdt.asl | 74 +++++++++++++++++++++++++--------- 1 file changed, 55 insertions(+), 19 deletions(-) diff --git a/src/mainboard/asus/kgpe-d16/dsdt.asl b/src/mainboard/asus/kgpe-d16/dsdt.asl @@ -205,5 +205,5 @@ index b6f10d9..bbe445f 100644 } Device (SLT1) -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0056-northbridge-amd-amdmct-Fix-hang-on-boot-due-to-inval.patch b/resources/libreboot/patch/kgpe-d16/0057-northbridge-amd-amdmct-Fix-hang-on-boot-due-to-inval.patch index 6c11daf..495ee91 100644 --- a/resources/libreboot/patch/kgpe-d16/0056-northbridge-amd-amdmct-Fix-hang-on-boot-due-to-inval.patch +++ b/resources/libreboot/patch/kgpe-d16/0057-northbridge-amd-amdmct-Fix-hang-on-boot-due-to-inval.patch @@ -1,23 +1,23 @@ -From b0454d907b46b7d117a8778e18aa01c4258aeb1a Mon Sep 17 00:00:00 2001 +From 117171290f9890f7e12f9252bf59e798bc6a8cf3 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Fri, 12 Jun 2015 19:43:06 -0500 -Subject: [PATCH 056/139] northbridge/amd/amdmct: Fix hang on boot due to +Subject: [PATCH 057/143] northbridge/amd/amdmct: Fix hang on boot due to invalid array access Change-Id: I47755caf7d2ff59463c817e739f9cb2ddd367c18 Signed-off-by: Timothy Pearson --- - src/northbridge/amd/amdmct/wrappers/mcti_d.c | 4 ++-- + src/northbridge/amd/amdmct/wrappers/mcti_d.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c -index 86a0b14..0a31aad 100644 +index 3053d58..295397a 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c -@@ -344,7 +344,7 @@ static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat) - } - +@@ -345,7 +345,7 @@ static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat) #if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */ + uint8_t dimm; + - for (i = 0; i < 15; i = i + 2) { + for (i = 0; i < MAX_DIMMS_SUPPORTED; i = i + 2) { if (pDCTstat->DIMMValid & (1 << i)) @@ -33,5 +33,5 @@ index 86a0b14..0a31aad 100644 highest_rank_count[i] = pDCTData->DimmRanks[dimm]; } -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0057-southbridge-amd-sr5650-Fix-GPP3a-link-training-in-hi.patch b/resources/libreboot/patch/kgpe-d16/0058-southbridge-amd-sr5650-Fix-GPP3a-link-training-in-hi.patch index dc2ad90..dd284cf 100644 --- a/resources/libreboot/patch/kgpe-d16/0057-southbridge-amd-sr5650-Fix-GPP3a-link-training-in-hi.patch +++ b/resources/libreboot/patch/kgpe-d16/0058-southbridge-amd-sr5650-Fix-GPP3a-link-training-in-hi.patch @@ -1,13 +1,13 @@ -From c6ad4c2dc41378273147690741de931ca2f292f5 Mon Sep 17 00:00:00 2001 +From 2b66ecd9eefad11d8f3456784208804f29e53b0b Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Fri, 12 Jun 2015 19:43:38 -0500 -Subject: [PATCH 057/139] southbridge/amd/sr5650: Fix GPP3a link training in +Subject: [PATCH 058/143] southbridge/amd/sr5650: Fix GPP3a link training in higher width modes Change-Id: I7503ae42eb8bc91411413ef2cc7e7a723df7091a Signed-off-by: Timothy Pearson --- - src/southbridge/amd/sr5650/pcie.c | 51 ++++++++++++++++++++++++++++++++++++--- + src/southbridge/amd/sr5650/pcie.c | 51 ++++++++++++++++++++++++++++++++++--- 1 file changed, 47 insertions(+), 4 deletions(-) diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c @@ -81,5 +81,5 @@ index d306b5a..79f2a5f 100644 AtiPcieCfg.PortDetect |= 1 << port; } else { -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0058-southbridge-amd-sr5650-Add-optional-delay-after-link.patch b/resources/libreboot/patch/kgpe-d16/0059-southbridge-amd-sr5650-Add-optional-delay-after-link.patch index 9466989..e24676d 100644 --- a/resources/libreboot/patch/kgpe-d16/0058-southbridge-amd-sr5650-Add-optional-delay-after-link.patch +++ b/resources/libreboot/patch/kgpe-d16/0059-southbridge-amd-sr5650-Add-optional-delay-after-link.patch @@ -1,8 +1,8 @@ -From fbb842e25841100adff123f3154c3149d241fd30 Mon Sep 17 00:00:00 2001 +From 4e2f99afb90497195aae6491ecf9d931e77dc90d Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Fri, 12 Jun 2015 20:08:29 -0500 -Subject: [PATCH 058/139] southbridge/amd/sr5650: Add optional delay after link - training +Subject: [PATCH 059/143] southbridge/amd/sr5650: Add optional delay after + link training Certain devices (such as the LSI SAS 2008 controller) do not respond to PCI probes immediately after link training. If it @@ -12,8 +12,8 @@ mainboard to insert an appropriate delay. Change-Id: Ibcd9426628cacd6f88e6e3fcbc2b3eb7e3a92081 Signed-off-by: Timothy Pearson --- - src/southbridge/amd/sr5650/chip.h | 4 ++++ - src/southbridge/amd/sr5650/sr5650.c | 3 +++ + src/southbridge/amd/sr5650/chip.h | 4 ++++ + src/southbridge/amd/sr5650/sr5650.c | 3 +++ 2 files changed, 7 insertions(+) diff --git a/src/southbridge/amd/sr5650/chip.h b/src/southbridge/amd/sr5650/chip.h @@ -67,5 +67,5 @@ index 75383de..6db1eb1 100644 } -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0059-mainboard-asus-kgpe-d16-Properly-configure-SR5690-so.patch b/resources/libreboot/patch/kgpe-d16/0060-mainboard-asus-kgpe-d16-Properly-configure-SR5690-so.patch index 822d763..40a2116 100644 --- a/resources/libreboot/patch/kgpe-d16/0059-mainboard-asus-kgpe-d16-Properly-configure-SR5690-so.patch +++ b/resources/libreboot/patch/kgpe-d16/0060-mainboard-asus-kgpe-d16-Properly-configure-SR5690-so.patch @@ -1,17 +1,17 @@ -From 64ad6ee510824d3804a38a538f1822e5313eb3a3 Mon Sep 17 00:00:00 2001 +From c3b35b628326f2b6f8b6b8fca8ab744654e8631b Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Fri, 12 Jun 2015 20:10:58 -0500 -Subject: [PATCH 059/139] mainboard/asus/kgpe-d16: Properly configure SR5690 +Subject: [PATCH 060/143] mainboard/asus/kgpe-d16: Properly configure SR5690 southbridge PIKE slot Change-Id: I2f1373905ffd6460ac3c7c21738e2e2a9aa2e463 Signed-off-by: Timothy Pearson --- - src/mainboard/asus/kgpe-d16/devicetree.cb | 6 +++--- + src/mainboard/asus/kgpe-d16/devicetree.cb | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/asus/kgpe-d16/devicetree.cb b/src/mainboard/asus/kgpe-d16/devicetree.cb -index 18e337e..ada268b 100644 +index cd22893..8eeb33e 100644 --- a/src/mainboard/asus/kgpe-d16/devicetree.cb +++ b/src/mainboard/asus/kgpe-d16/devicetree.cb @@ -43,9 +43,9 @@ chip northbridge/amd/amdfam10/root_complex # Root complex @@ -28,5 +28,5 @@ index 18e337e..ada268b 100644 chip southbridge/amd/sb700 # Secondary southbridge device pci 11.0 on end # SATA -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0060-southbridge-amd-sb700-Add-option-to-disable-SATA-ALP.patch b/resources/libreboot/patch/kgpe-d16/0061-southbridge-amd-sb700-Add-option-to-disable-SATA-ALP.patch index 84cd46a..fa54029 100644 --- a/resources/libreboot/patch/kgpe-d16/0060-southbridge-amd-sb700-Add-option-to-disable-SATA-ALP.patch +++ b/resources/libreboot/patch/kgpe-d16/0061-southbridge-amd-sb700-Add-option-to-disable-SATA-ALP.patch @@ -1,16 +1,16 @@ -From c13f090d6aa84c3537521bdb89cfb8dd10e70006 Mon Sep 17 00:00:00 2001 +From 59fece51e2abd69a5cf5829096d4f2b55ad994bf Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Thu, 18 Jun 2015 11:48:02 -0500 -Subject: [PATCH 060/139] southbridge/amd/sb700: Add option to disable SATA +Subject: [PATCH 061/143] southbridge/amd/sb700: Add option to disable SATA ALPM Change-Id: I88055cbb4df4d7ba811cef7056c0a6ca2612fcb0 Signed-off-by: Timothy Pearson --- - src/mainboard/asus/kgpe-d16/cmos.default | 1 + - src/mainboard/asus/kgpe-d16/cmos.layout | 8 ++++---- - src/southbridge/amd/sb700/sata.c | 12 ++++++++++++ - 3 files changed, 17 insertions(+), 4 deletions(-) + src/mainboard/asus/kgpe-d16/cmos.default | 1 + + src/mainboard/asus/kgpe-d16/cmos.layout | 7 ++++--- + src/southbridge/amd/sb700/sata.c | 12 ++++++++++++ + 3 files changed, 17 insertions(+), 3 deletions(-) diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default index 73f2a38..9b30b00 100644 @@ -25,10 +25,10 @@ index 73f2a38..9b30b00 100644 ieee1394 = Enable power_on_after_fail = On diff --git a/src/mainboard/asus/kgpe-d16/cmos.layout b/src/mainboard/asus/kgpe-d16/cmos.layout -index e91568c..f705af2 100644 +index 068eaf4..f705af2 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.layout +++ b/src/mainboard/asus/kgpe-d16/cmos.layout -@@ -46,11 +46,11 @@ entries +@@ -46,9 +46,10 @@ entries 465 1 e 1 cpu_c_states 466 1 e 1 cpu_cc6_state 467 1 e 1 sata_ahci_mode @@ -40,10 +40,8 @@ index e91568c..f705af2 100644 +473 2 e 13 dimm_spd_checksum +475 1 r 0 allow_spd_nvram_cache_restore 477 1 e 1 ieee1394 -->>>>>>> bed9a97... src/northbridge/amd/amdmct: Add option to override bad SPD checksum 728 256 h 0 user_data 984 16 h 0 check_sum - # Reserve the extended AMD configuration registers diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c index d35f84d..b09ae73 100644 --- a/src/southbridge/amd/sb700/sata.c @@ -82,5 +80,5 @@ index d35f84d..b09ae73 100644 byte = pci_read_config8(dev, 0x40); byte &= ~(1 << 0); -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0061-mainboard-asus-kgpe-d16-Set-SP5100-subtype.patch b/resources/libreboot/patch/kgpe-d16/0062-mainboard-asus-kgpe-d16-Set-SP5100-subtype.patch index d5a3a46..ceb3f87 100644 --- a/resources/libreboot/patch/kgpe-d16/0061-mainboard-asus-kgpe-d16-Set-SP5100-subtype.patch +++ b/resources/libreboot/patch/kgpe-d16/0062-mainboard-asus-kgpe-d16-Set-SP5100-subtype.patch @@ -1,12 +1,12 @@ -From 226e682880c316f193d58fc00b31265563c7ac38 Mon Sep 17 00:00:00 2001 +From 779dcaaff5ef6b357daa86e1f3f14223f34b9fc3 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Thu, 18 Jun 2015 12:37:08 -0500 -Subject: [PATCH 061/139] mainboard/asus/kgpe-d16: Set SP5100 subtype +Subject: [PATCH 062/143] mainboard/asus/kgpe-d16: Set SP5100 subtype Change-Id: If839fd71ed12c1fe27aeab374e242a6855737f5d Signed-off-by: Timothy Pearson --- - src/mainboard/asus/kgpe-d16/Kconfig | 1 + + src/mainboard/asus/kgpe-d16/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/asus/kgpe-d16/Kconfig b/src/mainboard/asus/kgpe-d16/Kconfig @@ -22,5 +22,5 @@ index 75bf0ee..084a412 100644 select PARALLEL_CPU_INIT select HAVE_ROMSTAGE_CONSOLE_SPINLOCK -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0062-northbridge-amd-amdmct-Fix-crash-on-startup-due-to-N.patch b/resources/libreboot/patch/kgpe-d16/0063-northbridge-amd-amdmct-Fix-crash-on-startup-due-to-N.patch index 34b14f0..12f420d 100644 --- a/resources/libreboot/patch/kgpe-d16/0062-northbridge-amd-amdmct-Fix-crash-on-startup-due-to-N.patch +++ b/resources/libreboot/patch/kgpe-d16/0063-northbridge-amd-amdmct-Fix-crash-on-startup-due-to-N.patch @@ -1,21 +1,21 @@ -From 136ca22907a8f16c8cce4d05a208ded2f2f054ac Mon Sep 17 00:00:00 2001 +From ba0eb2ea4d36eb0ce92b8512c7d5e26dfd2c9bc7 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sat, 20 Jun 2015 14:40:56 -0500 -Subject: [PATCH 062/139] northbridge/amd/amdmct: Fix crash on startup due to +Subject: [PATCH 063/143] northbridge/amd/amdmct: Fix crash on startup due to NULL pointer access Change-Id: I47089f2ad886a6fda4e0cd4472efd975bb8e06c5 Signed-off-by: Timothy Pearson --- - src/northbridge/amd/amdmct/wrappers/mcti_d.c | 5 ++--- + src/northbridge/amd/amdmct/wrappers/mcti_d.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c -index 0a31aad..ce2329d 100644 +index 295397a..116fb92 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -353,11 +353,10 @@ static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat) - #endif + } for (i = 0; i < 2; i++) { - sDCTStruct *pDCTData = pDCTstat->C_DCTPtr[i]; @@ -27,7 +27,7 @@ index 0a31aad..ce2329d 100644 + highest_rank_count[i] = pDCTstat->DimmRanks[dimm]; } } - + #endif -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0063-northbridge-amd-amdmct-Clear-memory-before-enabling-.patch b/resources/libreboot/patch/kgpe-d16/0064-northbridge-amd-amdmct-Clear-memory-before-enabling-.patch index da29a67..e444072 100644 --- a/resources/libreboot/patch/kgpe-d16/0063-northbridge-amd-amdmct-Clear-memory-before-enabling-.patch +++ b/resources/libreboot/patch/kgpe-d16/0064-northbridge-amd-amdmct-Clear-memory-before-enabling-.patch @@ -1,14 +1,14 @@ -From 1900ff138ed07b4cbe30aa4f73cb59b9ec5b4720 Mon Sep 17 00:00:00 2001 +From 337818cec631161582a2e65d73cf3e1f9a611bb7 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sat, 20 Jun 2015 20:02:49 -0500 -Subject: [PATCH 063/139] northbridge/amd/amdmct: Clear memory before enabling +Subject: [PATCH 064/143] northbridge/amd/amdmct: Clear memory before enabling ECC Change-Id: I992e7040520570893ba6a213138dd57bfa14733b Signed-off-by: Timothy Pearson --- - src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 45 ++++++++------------------ - src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 38 +++++++++++++++++++++- + src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 45 ++++++++---------------- + src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 38 +++++++++++++++++++- 2 files changed, 51 insertions(+), 32 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -181,5 +181,5 @@ index 3a9fecc..918e91e 100644 pMCTstat->GStatus |= 1< Date: Sat, 20 Jun 2015 21:31:15 -0500 -Subject: [PATCH 064/139] southbridge/amd/sb700: Do drive detection even in +Subject: [PATCH 065/143] southbridge/amd/sb700: Do drive detection even in AHCI mode SeaBIOS AHCI drive detection randomly fails for drives present @@ -11,7 +11,7 @@ drive detection in AHCI mode resolves this issue. Change-Id: I34eb1d5d3f2f8aefb749a4eeb911c1373d184938 Signed-off-by: Timothy Pearson --- - src/southbridge/amd/sb700/sata.c | 99 +++++++++++++++++++++------------------- + src/southbridge/amd/sb700/sata.c | 99 ++++++++++++++++++++------------------ 1 file changed, 53 insertions(+), 46 deletions(-) diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c @@ -138,5 +138,5 @@ index b09ae73..24f78dd 100644 } -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0065-src-southbridge-amd-sb700-Reset-SATA-controller-in-A.patch b/resources/libreboot/patch/kgpe-d16/0066-src-southbridge-amd-sb700-Reset-SATA-controller-in-A.patch index f63be47..b414899 100644 --- a/resources/libreboot/patch/kgpe-d16/0065-src-southbridge-amd-sb700-Reset-SATA-controller-in-A.patch +++ b/resources/libreboot/patch/kgpe-d16/0066-src-southbridge-amd-sb700-Reset-SATA-controller-in-A.patch @@ -1,7 +1,7 @@ -From 15a27b612b1da36173017dd671763ce455f319ad Mon Sep 17 00:00:00 2001 +From f2d97b4ed0b0594b8983dbe4d551aca7f9e6a32e Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sun, 21 Jun 2015 16:27:03 -0500 -Subject: [PATCH 065/139] src/southbridge/amd/sb700: Reset SATA controller in +Subject: [PATCH 066/143] src/southbridge/amd/sb700: Reset SATA controller in AHCI mode during startup In AHCI mode SeaBIOS randomly fails to detect disks (AHCI timeouts), @@ -13,7 +13,7 @@ detection code to attempt link renegotiation as needed. Change-Id: Ib1f7c5f830a0cdba41cb6f5b05d759adee5ce369 Signed-off-by: Timothy Pearson --- - src/southbridge/amd/sb700/sata.c | 47 ++++++++++++++++++++++++++++++---------- + src/southbridge/amd/sb700/sata.c | 47 ++++++++++++++++++++++++++++---------- 1 file changed, 35 insertions(+), 12 deletions(-) diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c @@ -92,5 +92,5 @@ index 24f78dd..d51baa1 100644 /* ????? why CIM does not set the AcpiGpe0BlkAddr , but use it??? */ -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0066-southbridge-amd-sb700-Recover-if-AHCI-disk-detection.patch b/resources/libreboot/patch/kgpe-d16/0067-southbridge-amd-sb700-Recover-if-AHCI-disk-detection.patch index 68138ca..407952e 100644 --- a/resources/libreboot/patch/kgpe-d16/0066-southbridge-amd-sb700-Recover-if-AHCI-disk-detection.patch +++ b/resources/libreboot/patch/kgpe-d16/0067-southbridge-amd-sb700-Recover-if-AHCI-disk-detection.patch @@ -1,13 +1,13 @@ -From c1413dd2277df0bd10fd2faf94302232889e95d8 Mon Sep 17 00:00:00 2001 +From e80d2ec15e83fe1e6bb1ee4c8b3d4dad196e023f Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Mon, 22 Jun 2015 02:21:29 -0500 -Subject: [PATCH 066/139] southbridge/amd/sb700: Recover if AHCI disk detection - fails +Subject: [PATCH 067/143] southbridge/amd/sb700: Recover if AHCI disk + detection fails Change-Id: I29051af5eca5d31b6aecc261e9a48028380eccb3 Signed-off-by: Timothy Pearson --- - src/southbridge/amd/sb700/sata.c | 83 ++++++++++++++++++++++++++++++++++++---- + src/southbridge/amd/sb700/sata.c | 83 ++++++++++++++++++++++++++++++++++---- 1 file changed, 75 insertions(+), 8 deletions(-) diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c @@ -159,5 +159,5 @@ index d51baa1..ce242c1 100644 if (sata_ahci_mode) printk(BIOS_DEBUG, "AHCI device %d is %sready after %i tries\n", -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0067-southbridge-amd-sb700-Fix-SATA-port-4-5-drive-detect.patch b/resources/libreboot/patch/kgpe-d16/0068-southbridge-amd-sb700-Fix-SATA-port-4-5-drive-detect.patch index 6466354..2db0453 100644 --- a/resources/libreboot/patch/kgpe-d16/0067-southbridge-amd-sb700-Fix-SATA-port-4-5-drive-detect.patch +++ b/resources/libreboot/patch/kgpe-d16/0068-southbridge-amd-sb700-Fix-SATA-port-4-5-drive-detect.patch @@ -1,13 +1,13 @@ -From 0785e1c4b21ee56c6265df7b6c7f95ad94a43fbb Mon Sep 17 00:00:00 2001 +From 20cecb2ba215a7c8021cc76631d388cbf63fb8b5 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Mon, 22 Jun 2015 02:56:10 -0500 -Subject: [PATCH 067/139] southbridge/amd/sb700: Fix SATA port 4/5 drive +Subject: [PATCH 068/143] southbridge/amd/sb700: Fix SATA port 4/5 drive detection Change-Id: I01481f25189d01b6f4ed778902b2ecc4d39c7912 Signed-off-by: Timothy Pearson --- - src/southbridge/amd/sb700/sata.c | 42 ++++++++++++++++++++++++++++++++++++---- + src/southbridge/amd/sb700/sata.c | 42 ++++++++++++++++++++++++++++++++++---- 1 file changed, 38 insertions(+), 4 deletions(-) diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c @@ -93,5 +93,5 @@ index ce242c1..dc64082 100644 byte = read8(sata_bar5 + 0x4); byte |= 1 << 1; -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0068-southbridge-amd-sb700-Fix-random-persistent-SATA-AHC.patch b/resources/libreboot/patch/kgpe-d16/0069-southbridge-amd-sb700-Fix-random-persistent-SATA-AHC.patch index 0d16a01..7b92fab 100644 --- a/resources/libreboot/patch/kgpe-d16/0068-southbridge-amd-sb700-Fix-random-persistent-SATA-AHC.patch +++ b/resources/libreboot/patch/kgpe-d16/0069-southbridge-amd-sb700-Fix-random-persistent-SATA-AHC.patch @@ -1,13 +1,13 @@ -From 6b5ae665f42bf04cb5dd54d719a18f5f1e670c63 Mon Sep 17 00:00:00 2001 +From f4472e05253e15f9324e3a9b669e0cb1f4dce5cb Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Mon, 22 Jun 2015 20:57:39 -0500 -Subject: [PATCH 068/139] southbridge/amd/sb700: Fix random persistent SATA +Subject: [PATCH 069/143] southbridge/amd/sb700: Fix random persistent SATA AHCI drive detection failure Change-Id: I4202a62217a7aaeaba07e4b994a350e83e064c9c Signed-off-by: Timothy Pearson --- - src/southbridge/amd/sb700/sata.c | 81 +++++++++++++++++++++------------------- + src/southbridge/amd/sb700/sata.c | 81 ++++++++++++++++++++------------------ 1 file changed, 42 insertions(+), 39 deletions(-) diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c @@ -161,5 +161,5 @@ index dc64082..9d354bb 100644 } if (sata_ahci_mode) -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0069-northbridge-amd-amdmct-mct_ddr3-Fix-lockups-and-wast.patch b/resources/libreboot/patch/kgpe-d16/0070-northbridge-amd-amdmct-mct_ddr3-Fix-lockups-and-wast.patch index 4b7392b..6a95d9d 100644 --- a/resources/libreboot/patch/kgpe-d16/0069-northbridge-amd-amdmct-mct_ddr3-Fix-lockups-and-wast.patch +++ b/resources/libreboot/patch/kgpe-d16/0070-northbridge-amd-amdmct-mct_ddr3-Fix-lockups-and-wast.patch @@ -1,20 +1,20 @@ -From c942d174cfc1a0ba6e91e0131c0a105addddbbd4 Mon Sep 17 00:00:00 2001 +From e37c51fbf56695813ee545da5507eb465c688241 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Wed, 24 Jun 2015 19:15:09 -0500 -Subject: [PATCH 069/139] northbridge/amd/amdmct/mct_ddr3: Fix lockups and +Subject: [PATCH 070/143] northbridge/amd/amdmct/mct_ddr3: Fix lockups and wasted time during ECC init Change-Id: I09a8ea83024186b7ece7d78a4bef1201ab34ff8a Signed-off-by: Timothy Pearson --- - src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 142 +++++++++++++++---------- - src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 39 ++++++- - src/northbridge/amd/amdmct/mct_ddr3/mctproc.c | 22 +++- - src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c | 3 +- - 4 files changed, 145 insertions(+), 61 deletions(-) + src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 144 +++++++++++++++--------- + src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 39 ++++++- + src/northbridge/amd/amdmct/mct_ddr3/mctproc.c | 22 +++- + src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c | 3 +- + 4 files changed, 147 insertions(+), 61 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c -index d8a09f0..68957f5 100644 +index d8a09f0..78bc8b3 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -1498,11 +1498,12 @@ restartinit: @@ -127,12 +127,14 @@ index d8a09f0..68957f5 100644 struct DCTStatStruc *pDCTstat; if (!mctGet_NVbits(NV_DQSTrainCTL)){ -@@ -2357,6 +2363,16 @@ static void MCTMemClr_D(struct MCTStatStruc *pMCTstat, +@@ -2357,6 +2363,18 @@ static void MCTMemClr_D(struct MCTStatStruc *pMCTstat, } } } + + for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { ++ pDCTstat = pDCTstatA + Node; ++ + /* Configure and enable prefetchers */ + if (is_fam15h()) + dword = 0x0ce00f41; /* BKDG recommended */ @@ -144,7 +146,7 @@ index d8a09f0..68957f5 100644 } static void DCTMemClr_Init_D(struct MCTStatStruc *pMCTstat, -@@ -2364,48 +2380,59 @@ static void DCTMemClr_Init_D(struct MCTStatStruc *pMCTstat, +@@ -2364,48 +2382,59 @@ static void DCTMemClr_Init_D(struct MCTStatStruc *pMCTstat, { u32 val; u32 dev; @@ -193,10 +195,10 @@ index d8a09f0..68957f5 100644 - val = Get_NB32(dev, reg); - } while (val & (1 << MemClrBusy)); + dword = Get_NB32(dev, 0x110); - ++ + printk(BIOS_DEBUG, "."); + } while (dword & (1 << MemClrBusy)); -+ + + printk(BIOS_DEBUG, "\n"); do { - val = Get_NB32(dev, reg); @@ -223,7 +225,7 @@ index d8a09f0..68957f5 100644 } static u8 NodePresent_D(u8 Node) -@@ -3346,8 +3373,8 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, +@@ -3346,8 +3375,8 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, dev = pDCTstat->dev_dct; /* Build Dram Control Register Value */ @@ -234,7 +236,7 @@ index d8a09f0..68957f5 100644 /* FIXME: Skip mct_checkForDxSupport */ /* REV_CALL mct_DoRdPtrInit if not Dx */ -@@ -3402,9 +3429,15 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, +@@ -3402,9 +3431,15 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, /* set only if x8 Registered DIMMs in System*/ DramConfigHi |= 1 << RDqsEn; @@ -253,7 +255,7 @@ index d8a09f0..68957f5 100644 /* Control Bank Swizzle */ if (0) /* call back not needed mctBankSwizzleControl_D()) */ -@@ -4112,8 +4145,7 @@ static void mct_preInitDCT(struct MCTStatStruc *pMCTstat, +@@ -4112,8 +4147,7 @@ static void mct_preInitDCT(struct MCTStatStruc *pMCTstat, if (load_spd_hashes_from_nvram(pMCTstat, pDCTstat) < 0) { pDCTstat->spd_data.nvram_spd_match = 0; @@ -263,7 +265,7 @@ index d8a09f0..68957f5 100644 compare_nvram_spd_hashes(pMCTstat, pDCTstat); } #else -@@ -4311,8 +4343,8 @@ static u8 mct_PlatformSpec(struct MCTStatStruc *pMCTstat, +@@ -4311,8 +4345,8 @@ static u8 mct_PlatformSpec(struct MCTStatStruc *pMCTstat, } for (i=i_start; iErrCode; -@@ -6102,11 +6134,11 @@ void ProgDramMRSReg_D(struct MCTStatStruc *pMCTstat, +@@ -6102,11 +6136,11 @@ void ProgDramMRSReg_D(struct MCTStatStruc *pMCTstat, DramMRS |= 1 << 1; dword = Get_NB32_DCT(pDCTstat->dev_dct, dct, 0x84); @@ -389,7 +391,7 @@ index 5ef4a2c..32b447f 100644 misc2 |= 1 << SubMemclkRegDly; if (mctGet_NVbits(NV_MAX_DIMMS) == 8) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c -index 7ea7901..c760bac 100644 +index 35378c8..0e626fa 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c @@ -209,7 +209,8 @@ void AgesaHwWlPhase2(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTsta @@ -403,5 +405,5 @@ index 7ea7901..c760bac 100644 pDCTData->WLFineDelay[index+ByteLane] = pDCTData->WLSeedFineDelay[index+ByteLane]; } -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0070-cpu-amd-Fix-AMD-Family-15h-ECC-initialization-reliab.patch b/resources/libreboot/patch/kgpe-d16/0071-cpu-amd-Fix-AMD-Family-15h-ECC-initialization-reliab.patch index 0b55b83..7a84e72 100644 --- a/resources/libreboot/patch/kgpe-d16/0070-cpu-amd-Fix-AMD-Family-15h-ECC-initialization-reliab.patch +++ b/resources/libreboot/patch/kgpe-d16/0071-cpu-amd-Fix-AMD-Family-15h-ECC-initialization-reliab.patch @@ -1,20 +1,20 @@ -From 589c0f7e4f80b82bdf8e604f0a7ded82cc9c09fe Mon Sep 17 00:00:00 2001 +From b2b65511ad56a90e2f206d99d348854d379a719b Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Thu, 25 Jun 2015 15:07:34 -0500 -Subject: [PATCH 070/139] cpu/amd: Fix AMD Family 15h ECC initialization +Subject: [PATCH 071/143] cpu/amd: Fix AMD Family 15h ECC initialization reliability issues Change-Id: I7f009b655f8500aeb22981f7020f1db74cdd6925 Signed-off-by: Timothy Pearson --- - src/cpu/amd/car/cache_as_ram.inc | 4 + - src/cpu/amd/family_10h-family_15h/init_cpus.c | 16 ++++ - src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 12 +-- - src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 6 +- - src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 21 ++++- - src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 110 +++++++++++-------------- - src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c | 6 +- - src/northbridge/amd/amdmct/mct_ddr3/s3utils.c | 57 ++++++++----- + src/cpu/amd/car/cache_as_ram.inc | 4 + + src/cpu/amd/family_10h-family_15h/init_cpus.c | 16 ++++ + src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 12 +-- + src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 6 +- + src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 21 ++++- + src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 110 +++++++++++------------- + src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c | 6 +- + src/northbridge/amd/amdmct/mct_ddr3/s3utils.c | 57 +++++++----- 8 files changed, 136 insertions(+), 96 deletions(-) diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc @@ -39,7 +39,7 @@ index 9edc41f..5db9224 100644 /* Enable write base caching so we can do execute in place (XIP) diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c -index 818431b..0044dc6 100644 +index 061bba2..d45671c 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -317,6 +317,22 @@ static void STOP_CAR_AND_CPU(uint8_t skip_sharedc_config, uint32_t apicid) @@ -66,7 +66,7 @@ index 818431b..0044dc6 100644 disable_cache_as_ram(skip_sharedc_config); // inline diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c -index 68957f5..fadb353 100644 +index 78bc8b3..dda997e 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -1458,8 +1458,7 @@ restartinit: @@ -470,5 +470,5 @@ index fe89af1..b4a084c 100644 if (is_fam15h()) /* Set LockDramCfg and CC6SaveEn */ -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0071-northbridge-amd-amdfam10-Properly-indicate-node-and-.patch b/resources/libreboot/patch/kgpe-d16/0072-northbridge-amd-amdfam10-Properly-indicate-node-and-.patch index 460ea7d..4b628b1 100644 --- a/resources/libreboot/patch/kgpe-d16/0071-northbridge-amd-amdfam10-Properly-indicate-node-and-.patch +++ b/resources/libreboot/patch/kgpe-d16/0072-northbridge-amd-amdfam10-Properly-indicate-node-and-.patch @@ -1,21 +1,21 @@ -From ad1418509321ae8765b2e4692f10e5becc28073e Mon Sep 17 00:00:00 2001 +From a00183866e0083ead7735ef5dcb974a98cd0de98 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Thu, 25 Jun 2015 15:28:23 -0500 -Subject: [PATCH 071/139] northbridge/amd/amdfam10: Properly indicate node and +Subject: [PATCH 072/143] northbridge/amd/amdfam10: Properly indicate node and channel in SMBIOS tables Change-Id: Ie7278745358daf0c78cdb9c579db5291a1a2a0cb Signed-off-by: Timothy Pearson --- - src/northbridge/amd/amdfam10/northbridge.c | 7 ++++++- - src/northbridge/amd/amdmct/mct/mct_d.c | 12 ++++++++++++ - src/northbridge/amd/amdmct/mct/mct_d.h | 7 +++++-- - src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 12 ++++++++++++ - src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 8 +++++--- + src/northbridge/amd/amdfam10/northbridge.c | 7 ++++++- + src/northbridge/amd/amdmct/mct/mct_d.c | 12 ++++++++++++ + src/northbridge/amd/amdmct/mct/mct_d.h | 7 +++++-- + src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 12 ++++++++++++ + src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 8 +++++--- 5 files changed, 40 insertions(+), 6 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c -index 3fc31c0..95e902d 100644 +index 9fe0ccb..52b5ffb 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -1207,7 +1207,12 @@ static int amdfam10_get_smbios_data17(int* count, int handle, int parent_handle, @@ -74,7 +74,7 @@ index 6b6194d..7569300 100644 1= Variance Error, DCT is running but not in an optimal configuration. 2= Stop Error, DCT is NOT running diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c -index fadb353..573c0af 100644 +index dda997e..571e18d 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -1389,6 +1389,18 @@ restartinit: @@ -116,5 +116,5 @@ index ac8c934..8c9da47 100644 1= Variance Error, DCT is running but not in an optimal configuration. 2= Stop Error, DCT is NOT running -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0072-amd-amdmct-mct_ddr3-Add-Family-15h-RDIMM-timing-and-.patch b/resources/libreboot/patch/kgpe-d16/0073-amd-amdmct-mct_ddr3-Add-Family-15h-RDIMM-timing-and-.patch index 682326b..6f2398e 100644 --- a/resources/libreboot/patch/kgpe-d16/0072-amd-amdmct-mct_ddr3-Add-Family-15h-RDIMM-timing-and-.patch +++ b/resources/libreboot/patch/kgpe-d16/0073-amd-amdmct-mct_ddr3-Add-Family-15h-RDIMM-timing-and-.patch @@ -1,17 +1,17 @@ -From e2624058dba93cd3820dffbf7964cd84b3ddd973 Mon Sep 17 00:00:00 2001 +From 88204b8dc65003163e2f02ea14b4d8513a6d16bc Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Thu, 25 Jun 2015 17:07:57 -0500 -Subject: [PATCH 072/139] amd/amdmct/mct_ddr3: Add Family 15h RDIMM timing and +Subject: [PATCH 073/143] amd/amdmct/mct_ddr3: Add Family 15h RDIMM timing and ODT values Change-Id: Ia9ee770d9f9c22e18c12e38b5bb4a7bae0a99062 Signed-off-by: Timothy Pearson --- - src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 422 +++++++++++++++++++--------- + src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 422 ++++++++++++++++++--------- 1 file changed, 290 insertions(+), 132 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c -index 573c0af..643fa39 100644 +index 571e18d..999e4ae 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -822,28 +822,12 @@ static uint32_t fam15h_output_driver_compensation_code(struct DCTStatStruc *pDCT @@ -504,5 +504,5 @@ index 573c0af..643fa39 100644 } else { /* TODO -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0073-northbridge-amd-amdmct-mct_ddr3-Attempt-to-recover-f.patch b/resources/libreboot/patch/kgpe-d16/0074-northbridge-amd-amdmct-mct_ddr3-Attempt-to-recover-f.patch index 43ba5d1..d054245 100644 --- a/resources/libreboot/patch/kgpe-d16/0073-northbridge-amd-amdmct-mct_ddr3-Attempt-to-recover-f.patch +++ b/resources/libreboot/patch/kgpe-d16/0074-northbridge-amd-amdmct-mct_ddr3-Attempt-to-recover-f.patch @@ -1,14 +1,14 @@ -From 15e1fd712629a70457b1dfd76fe46c539e7c64e5 Mon Sep 17 00:00:00 2001 +From 42807626761e52746fd88b39c76223bc85e49e50 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Thu, 25 Jun 2015 18:08:53 -0500 -Subject: [PATCH 073/139] northbridge/amd/amdmct/mct_ddr3: Attempt to recover +Subject: [PATCH 074/143] northbridge/amd/amdmct/mct_ddr3: Attempt to recover from phy training errors Change-Id: Ia2c3022534c9ad44714eef6e118869f054bd9f6b Signed-off-by: Timothy Pearson --- - src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c | 68 +++++++++++++++++++++------ - src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c | 36 +++++++++++--- + src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c | 68 +++++++++++++++++++------ + src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c | 36 ++++++++++--- 2 files changed, 83 insertions(+), 21 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c b/src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c @@ -162,7 +162,7 @@ index 5e81808..539cb0d 100644 for (dct = 0; dct < 2; dct++) { sDCTStruct *pDCTData = pDCTstat->C_DCTPtr[dct]; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c -index c760bac..bb076cb 100644 +index 0e626fa..403c87c 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c @@ -54,7 +54,7 @@ static int32_t abs(int32_t val) { @@ -252,5 +252,5 @@ index c760bac..bb076cb 100644 /*---------------------------------------------------------------------------- -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0074-northbridge-amd-amdmct-mct_ddr3-Work-around-strange-.patch b/resources/libreboot/patch/kgpe-d16/0075-northbridge-amd-amdmct-mct_ddr3-Work-around-strange-.patch index 5703442..ed90d9f 100644 --- a/resources/libreboot/patch/kgpe-d16/0074-northbridge-amd-amdmct-mct_ddr3-Work-around-strange-.patch +++ b/resources/libreboot/patch/kgpe-d16/0075-northbridge-amd-amdmct-mct_ddr3-Work-around-strange-.patch @@ -1,17 +1,17 @@ -From 91caf442aef8c846b9d860bf3e8d2954a2a5e21b Mon Sep 17 00:00:00 2001 +From 557954beb8c452750f9ffdd176896b2afb764f27 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Thu, 25 Jun 2015 18:37:45 -0500 -Subject: [PATCH 074/139] northbridge/amd/amdmct/mct_ddr3: Work around strange +Subject: [PATCH 075/143] northbridge/amd/amdmct/mct_ddr3: Work around strange phy training issue Change-Id: Ic7a19d24954f47c922126e3da7be1f7e85f7396f Signed-off-by: Timothy Pearson --- - src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c | 16 ++++++++++++++++ + src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c -index bb076cb..bd37ba7 100644 +index 403c87c..85b8378 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c @@ -207,6 +207,22 @@ uint8_t AgesaHwWlPhase2(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCT @@ -38,5 +38,5 @@ index bb076cb..bd37ba7 100644 for (ByteLane = 0; ByteLane < MAX_BYTE_LANES; ByteLane++) { uint8_t faulty_value_detected = 0; -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0075-northbridge-amd-amdmct-mct_ddr3-Add-additional-debug.patch b/resources/libreboot/patch/kgpe-d16/0076-northbridge-amd-amdmct-mct_ddr3-Add-additional-debug.patch index 728e747..e233545 100644 --- a/resources/libreboot/patch/kgpe-d16/0075-northbridge-amd-amdmct-mct_ddr3-Add-additional-debug.patch +++ b/resources/libreboot/patch/kgpe-d16/0076-northbridge-amd-amdmct-mct_ddr3-Add-additional-debug.patch @@ -1,21 +1,21 @@ -From feb85d8596ae2447a8ec82e370350e30cfefbc90 Mon Sep 17 00:00:00 2001 +From 2d90214ad2153d723398d5c1175a7dc1769f86a4 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Fri, 26 Jun 2015 00:17:10 -0500 -Subject: [PATCH 075/139] northbridge/amd/amdmct/mct_ddr3: Add additional debug - trace statements +Subject: [PATCH 076/143] northbridge/amd/amdmct/mct_ddr3: Add additional + debug trace statements Change-Id: Iacd789b3572dc8ee85e76d56c46685e6df31d1a6 Signed-off-by: Timothy Pearson --- - src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 8 ++++++++ - src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c | 16 ++++++++++++++++ + src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 8 ++++++++ + src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c | 16 ++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c -index 643fa39..f9a7934 100644 +index 999e4ae..6448eb4 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c -@@ -5815,7 +5815,11 @@ static void mct_ResetDataStruct_D(struct MCTStatStruc *pMCTstat, +@@ -5817,7 +5817,11 @@ static void mct_ResetDataStruct_D(struct MCTStatStruc *pMCTstat, static void mct_BeforeDramInit_Prod_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct) { @@ -27,7 +27,7 @@ index 643fa39..f9a7934 100644 } static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat, -@@ -5825,6 +5829,8 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat, +@@ -5827,6 +5831,8 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat, u32 dword; u32 dev = pDCTstat->dev_dct; @@ -36,7 +36,7 @@ index 643fa39..f9a7934 100644 /* FIXME * Mainboards need to be able to specify the maximum number of DIMMs installable per channel * For now assume a maximum of 2 DIMMs per channel can be installed -@@ -6139,6 +6145,8 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat, +@@ -6141,6 +6147,8 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat, Set_NB32_index_wait_DCT(dev, i, 0xf0, 0x183, odt_pattern_2); } } @@ -116,5 +116,5 @@ index 51cbf16..380c5f2 100644 + printk(BIOS_DEBUG, "%s: Done\n", __func__); } -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0076-northbridge-amd-amdmct-mct_ddr3-Fix-null-pointer-acc.patch b/resources/libreboot/patch/kgpe-d16/0077-northbridge-amd-amdmct-mct_ddr3-Fix-null-pointer-acc.patch index 73d5696..cdfa99b 100644 --- a/resources/libreboot/patch/kgpe-d16/0076-northbridge-amd-amdmct-mct_ddr3-Fix-null-pointer-acc.patch +++ b/resources/libreboot/patch/kgpe-d16/0077-northbridge-amd-amdmct-mct_ddr3-Fix-null-pointer-acc.patch @@ -1,18 +1,18 @@ -From 55d9af79adf271287c8cf9091da53b707f67e02f Mon Sep 17 00:00:00 2001 +From fd59dbd74e335c9337f4c2fedf76575a454f4e19 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Fri, 26 Jun 2015 12:17:48 -0500 -Subject: [PATCH 076/139] northbridge/amd/amdmct/mct_ddr3: Fix null pointer +Subject: [PATCH 077/143] northbridge/amd/amdmct/mct_ddr3: Fix null pointer access and related hangs Change-Id: Iaf826b6a0c8e929372519f6d97933515a80f0b39 Signed-off-by: Timothy Pearson --- - src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 58 +++++++++++++++------------- - src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c | 8 ++-- + src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 58 ++++++++++++++------------ + src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c | 8 ++-- 2 files changed, 34 insertions(+), 32 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c -index f9a7934..e859c54 100644 +index 6448eb4..2009fd3 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -826,7 +826,7 @@ static uint32_t fam15h_output_driver_compensation_code(struct DCTStatStruc *pDCT @@ -115,7 +115,7 @@ index f9a7934..e859c54 100644 if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6) || (MemClkFreq == 0xa)) { -@@ -5851,14 +5851,18 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat, +@@ -5853,14 +5853,18 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat, uint8_t write_odt_delay; uint8_t read_odt_delay; @@ -136,7 +136,7 @@ index f9a7934..e859c54 100644 if (rank_count_dimm1 == 1) { odt_pattern_0 = 0x00000000; odt_pattern_1 = 0x00000000; -@@ -5883,8 +5887,8 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat, +@@ -5885,8 +5889,8 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat, } } else { /* 2 DIMMs detected */ @@ -147,7 +147,7 @@ index f9a7934..e859c54 100644 if ((rank_count_dimm0 < 4) && (rank_count_dimm1 < 4)) { odt_pattern_0 = 0x00000000; odt_pattern_1 = 0x01010202; -@@ -5922,7 +5926,7 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat, +@@ -5924,7 +5928,7 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat, odt_pattern_2 = 0x00000000; odt_pattern_3 = 0x00000000; } @@ -156,7 +156,7 @@ index f9a7934..e859c54 100644 /* TODO * Load reduced dimms UNIMPLEMENTED */ -@@ -5934,7 +5938,7 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat, +@@ -5936,7 +5940,7 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat, if (MaxDimmsInstallable == 2) { if (dimm_count == 1) { /* 1 DIMM detected */ @@ -165,7 +165,7 @@ index f9a7934..e859c54 100644 if (rank_count_dimm1 == 1) { odt_pattern_0 = 0x00000000; odt_pattern_1 = 0x00000000; -@@ -5970,7 +5974,7 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat, +@@ -5972,7 +5976,7 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat, } } @@ -174,7 +174,7 @@ index f9a7934..e859c54 100644 /* TODO * Load reduced dimms UNIMPLEMENTED */ -@@ -6030,11 +6034,11 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat, +@@ -6032,11 +6036,11 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat, /* Select appropriate ODT pattern for installed DIMMs * Refer to the Fam10h BKDG Rev. 3.62, page 120 onwards */ @@ -188,7 +188,7 @@ index f9a7934..e859c54 100644 if (rank_count_dimm1 == 1) { odt_pattern_0 = 0x00000000; odt_pattern_1 = 0x00000000; -@@ -6059,8 +6063,8 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat, +@@ -6061,8 +6065,8 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat, } } else { /* 2 DIMMs detected */ @@ -199,7 +199,7 @@ index f9a7934..e859c54 100644 if ((rank_count_dimm0 < 4) && (rank_count_dimm1 < 4)) { odt_pattern_0 = 0x00000000; odt_pattern_1 = 0x01010202; -@@ -6102,7 +6106,7 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat, +@@ -6104,7 +6108,7 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat, if (MaxDimmsInstallable == 2) { if (dimm_count == 1) { /* 1 DIMM detected */ @@ -236,5 +236,5 @@ index 380c5f2..c7d7463 100644 if (is_fam15h()) -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0077-northbridge-amd-amdmct-mct_ddr3-Add-missing-Family-1.patch b/resources/libreboot/patch/kgpe-d16/0078-northbridge-amd-amdmct-mct_ddr3-Add-missing-Family-1.patch index b406fc9..cb40f86 100644 --- a/resources/libreboot/patch/kgpe-d16/0077-northbridge-amd-amdmct-mct_ddr3-Add-missing-Family-1.patch +++ b/resources/libreboot/patch/kgpe-d16/0078-northbridge-amd-amdmct-mct_ddr3-Add-missing-Family-1.patch @@ -1,18 +1,18 @@ -From bc99fcbab8c0bd2851216a34f3d72fddbe790332 Mon Sep 17 00:00:00 2001 +From 85be24f8b0bbe7ddea842457438837c48ca0ae13 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Fri, 26 Jun 2015 14:15:57 -0500 -Subject: [PATCH 077/139] northbridge/amd/amdmct/mct_ddr3: Add missing Family +Subject: [PATCH 078/143] northbridge/amd/amdmct/mct_ddr3: Add missing Family 15h RDIMM Rtt values Change-Id: I80cd7f8aec12951611d802f33e5e167a41dd532e Signed-off-by: Timothy Pearson --- - src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 4 +- - src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c | 201 ++++++++++++++++++++++++++- + src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 4 +- + src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c | 201 +++++++++++++++++++++++++- 2 files changed, 198 insertions(+), 7 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c -index e859c54..8ca2c25 100644 +index 2009fd3..bb5593d 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -897,8 +897,8 @@ static uint32_t fam15h_output_driver_compensation_code(struct DCTStatStruc *pDCT @@ -264,5 +264,5 @@ index c7d7463..dfbd2d9 100644 /* Socket G34: Fam15h BKDG v3.14 Table 56 */ if (MaxDimmsInstallable == 1) { -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0078-northbridge-amd-amdmct-mct_ddr3-Set-SkewMemClk-when-.patch b/resources/libreboot/patch/kgpe-d16/0079-northbridge-amd-amdmct-mct_ddr3-Set-SkewMemClk-when-.patch index 7b3d0f1..d06c447 100644 --- a/resources/libreboot/patch/kgpe-d16/0078-northbridge-amd-amdmct-mct_ddr3-Set-SkewMemClk-when-.patch +++ b/resources/libreboot/patch/kgpe-d16/0079-northbridge-amd-amdmct-mct_ddr3-Set-SkewMemClk-when-.patch @@ -1,21 +1,21 @@ -From e8926cb6ee7046c3b4ceacb1ca8c885a2ec1c037 Mon Sep 17 00:00:00 2001 +From 77935659fbe9426e7a65ecc5506beb4491171e7f Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Fri, 26 Jun 2015 17:49:25 -0500 -Subject: [PATCH 078/139] northbridge/amd/amdmct/mct_ddr3: Set SkewMemClk when +Subject: [PATCH 079/143] northbridge/amd/amdmct/mct_ddr3: Set SkewMemClk when both DCTs are in use Change-Id: Ibcce54fc53b79beba2f790994bcf87cc0354213a Signed-off-by: Timothy Pearson --- - src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 41 +++++++++++++++++++++++------ - src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 2 +- + src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 41 +++++++++++++++++++++------ + src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 2 +- 2 files changed, 34 insertions(+), 9 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c -index 8ca2c25..aea17a1 100644 +index bb5593d..f3d5cb8 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c -@@ -2643,7 +2643,7 @@ static void DCTPreInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDC +@@ -2645,7 +2645,7 @@ static void DCTPreInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDC /* Reset DCT registers */ ClearDCT_D(pMCTstat, pDCTstat, dct); @@ -24,7 +24,7 @@ index 8ca2c25..aea17a1 100644 if (!is_fam15h()) { /* Enable DDR3 support */ -@@ -2654,7 +2654,7 @@ static void DCTPreInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDC +@@ -2656,7 +2656,7 @@ static void DCTPreInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDC /* Read the SPD information into the data structures */ if (mct_DIMMPresence(pMCTstat, pDCTstat, dct) < SC_StopError) { @@ -33,7 +33,7 @@ index 8ca2c25..aea17a1 100644 } } -@@ -2680,17 +2680,40 @@ static void DCTInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTst +@@ -2682,17 +2682,40 @@ static void DCTInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTst printk(BIOS_DEBUG, "\t\tDCTInit_D: AutoConfig_D Done\n"); if (PlatformSpec_D(pMCTstat, pDCTstat, dct) < SC_StopError) { printk(BIOS_DEBUG, "\t\tDCTInit_D: PlatformSpec_D Done\n"); @@ -80,7 +80,7 @@ index 8ca2c25..aea17a1 100644 dword = 1 << DisDramInterface; Set_NB32_DCT(pDCTstat->dev_dct, dct, 0x94, dword); -@@ -4348,6 +4371,7 @@ static void mct_initDCT(struct MCTStatStruc *pMCTstat, +@@ -4350,6 +4373,7 @@ static void mct_initDCT(struct MCTStatStruc *pMCTstat, /* Config. DCT0 for Ganged or unganged mode */ DCTInit_D(pMCTstat, pDCTstat, 0); @@ -88,7 +88,7 @@ index 8ca2c25..aea17a1 100644 if (pDCTstat->ErrCode == SC_FatalErr) { /* Do nothing goto exitDCTInit; any fatal errors? */ } else { -@@ -4357,6 +4381,7 @@ static void mct_initDCT(struct MCTStatStruc *pMCTstat, +@@ -4359,6 +4383,7 @@ static void mct_initDCT(struct MCTStatStruc *pMCTstat, err_code = pDCTstat->ErrCode; /* save DCT0 errors */ pDCTstat->ErrCode = 0; DCTInit_D(pMCTstat, pDCTstat, 1); @@ -110,5 +110,5 @@ index 8c9da47..7bc392b 100644 0= no error 1= Variance Error, DCT is running but not in an optimal configuration. -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0079-northbridge-amd-amdmct-mct_ddr3-Properly-indicate-cl.patch b/resources/libreboot/patch/kgpe-d16/0080-northbridge-amd-amdmct-mct_ddr3-Properly-indicate-cl.patch index 2f8a513..da17100 100644 --- a/resources/libreboot/patch/kgpe-d16/0079-northbridge-amd-amdmct-mct_ddr3-Properly-indicate-cl.patch +++ b/resources/libreboot/patch/kgpe-d16/0080-northbridge-amd-amdmct-mct_ddr3-Properly-indicate-cl.patch @@ -1,13 +1,13 @@ -From 146d781ece056408e0ba28b4c8d7a46df6d0257a Mon Sep 17 00:00:00 2001 +From e4cb65c6451563032f027e526250ac5e4bd614bb Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sat, 27 Jun 2015 17:52:18 -0500 -Subject: [PATCH 079/139] northbridge/amd/amdmct/mct_ddr3: Properly indicate +Subject: [PATCH 080/143] northbridge/amd/amdmct/mct_ddr3: Properly indicate clobbered registers Change-Id: Icb2754143762bd64ee1df5674fa071de1c595eaf Signed-off-by: Timothy Pearson --- - src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h | 11 +++++++++-- + src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h @@ -54,5 +54,5 @@ index f6aa755..cc8d971 100644 } -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0080-northbridge-amd-amdmct-mct_ddr3-Fix-Family-10h-boot-.patch b/resources/libreboot/patch/kgpe-d16/0081-northbridge-amd-amdmct-mct_ddr3-Fix-Family-10h-boot-.patch index 4f7af96..5d2b74f 100644 --- a/resources/libreboot/patch/kgpe-d16/0080-northbridge-amd-amdmct-mct_ddr3-Fix-Family-10h-boot-.patch +++ b/resources/libreboot/patch/kgpe-d16/0081-northbridge-amd-amdmct-mct_ddr3-Fix-Family-10h-boot-.patch @@ -1,18 +1,18 @@ -From ddbdb1b748edc2f8a8c453d93a36f28e7d26f2e5 Mon Sep 17 00:00:00 2001 +From 5045c1b894492d4e818c41861d2c21e4eef242b4 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sat, 27 Jun 2015 17:52:45 -0500 -Subject: [PATCH 080/139] northbridge/amd/amdmct/mct_ddr3: Fix Family 10h boot +Subject: [PATCH 081/143] northbridge/amd/amdmct/mct_ddr3: Fix Family 10h boot failure Change-Id: I5dcb333d3a5a49318fe7bddd4c386642205c343e Signed-off-by: Timothy Pearson --- - src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 28 +++++++++++++++++++++------- - src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 8 +++++++- + src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 28 +++++++++++++++++++------- + src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 8 +++++++- 2 files changed, 28 insertions(+), 8 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c -index aea17a1..1758bd6 100644 +index f3d5cb8..cfdfd43 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -1628,6 +1628,11 @@ restartinit: @@ -57,7 +57,7 @@ index aea17a1..1758bd6 100644 printk(BIOS_DEBUG, "mctAutoInitMCT_D: mct_ForceNBPState0_Dis_Fam15\n"); for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { -@@ -6343,11 +6355,13 @@ void ProgDramMRSReg_D(struct MCTStatStruc *pMCTstat, +@@ -6345,11 +6357,13 @@ void ProgDramMRSReg_D(struct MCTStatStruc *pMCTstat, DramMRS |= 1 << 1; dword = Get_NB32_DCT(pDCTstat->dev_dct, dct, 0x84); @@ -96,5 +96,5 @@ index 011a94f..57641a1 100644 MaxDelay_CH[Channel] = CTLRMaxDelay; } -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0082-cpu-amd-family_10h-family_15h-Fix-BSP-stack-corrupti.patch b/resources/libreboot/patch/kgpe-d16/0082-cpu-amd-family_10h-family_15h-Fix-BSP-stack-corrupti.patch deleted file mode 100644 index 72f6948..0000000 --- a/resources/libreboot/patch/kgpe-d16/0082-cpu-amd-family_10h-family_15h-Fix-BSP-stack-corrupti.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 170af60b6ef005f40458f7d55d370dbc083a9a8b Mon Sep 17 00:00:00 2001 -From: Timothy Pearson -Date: Fri, 24 Jul 2015 17:34:29 -0500 -Subject: [PATCH 082/139] cpu/amd/family_10h-family_15h: Fix BSP stack - corruption on 32-core Fam10 systems - -Change-Id: I72ae8f7abeb9a83b57505469922818f9ec5bdf3f -Signed-off-by: Timothy Pearson ---- - src/cpu/amd/family_10h-family_15h/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig -index 81b1d1e..b95943f 100644 ---- a/src/cpu/amd/family_10h-family_15h/Kconfig -+++ b/src/cpu/amd/family_10h-family_15h/Kconfig -@@ -37,7 +37,7 @@ config DCACHE_BSP_STACK_SIZE - - config DCACHE_BSP_STACK_SLUSH - hex -- default 0x1000 -+ default 0x4000 - - config DCACHE_AP_STACK_SIZE - hex --- -1.9.1 - diff --git a/resources/libreboot/patch/kgpe-d16/0081-src-southbridge-amd-sr5650-Always-configure-lane-dir.patch b/resources/libreboot/patch/kgpe-d16/0082-src-southbridge-amd-sr5650-Always-configure-lane-dir.patch index 32a1e8a..8d4fc4a 100644 --- a/resources/libreboot/patch/kgpe-d16/0081-src-southbridge-amd-sr5650-Always-configure-lane-dir.patch +++ b/resources/libreboot/patch/kgpe-d16/0082-src-southbridge-amd-sr5650-Always-configure-lane-dir.patch @@ -1,7 +1,7 @@ -From 789bac438e1ab4c10ec6bbeb9f62a78d0abcd156 Mon Sep 17 00:00:00 2001 +From 841de11861037d80ef651107d2be0f7fb31c8cf1 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Fri, 3 Jul 2015 17:16:22 -0500 -Subject: [PATCH 081/139] src/southbridge/amd/sr5650: Always configure lane +Subject: [PATCH 082/143] src/southbridge/amd/sr5650: Always configure lane director on startup On the ASUS KGPE-D16 it was noted that the pin straps did not properly @@ -12,7 +12,7 @@ on startup resolves this problem. Change-Id: I5b78cef84960e0f42cc3e0406a7031d12d21f3ad Signed-off-by: Timothy Pearson --- - src/southbridge/amd/sr5650/pcie.c | 13 +++---------- + src/southbridge/amd/sr5650/pcie.c | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c @@ -47,5 +47,5 @@ index 79f2a5f..09ce217 100644 } -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0083-cpu-amd-family_10h-family_15h-Fix-BSP-stack-corrupti.patch b/resources/libreboot/patch/kgpe-d16/0083-cpu-amd-family_10h-family_15h-Fix-BSP-stack-corrupti.patch new file mode 100644 index 0000000..284750c --- /dev/null +++ b/resources/libreboot/patch/kgpe-d16/0083-cpu-amd-family_10h-family_15h-Fix-BSP-stack-corrupti.patch @@ -0,0 +1,40 @@ +From dbc09e431b4023385d3733a1b157053ff6e8c9f0 Mon Sep 17 00:00:00 2001 +From: Timothy Pearson +Date: Fri, 24 Jul 2015 17:34:29 -0500 +Subject: [PATCH 083/143] cpu/amd/family_10h-family_15h: Fix BSP stack + corruption on 32-core Fam10 systems + +Change-Id: I72ae8f7abeb9a83b57505469922818f9ec5bdf3f +Signed-off-by: Timothy Pearson +--- + src/cpu/amd/family_10h-family_15h/Kconfig | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig +index 81b1d1e..bfb6751 100644 +--- a/src/cpu/amd/family_10h-family_15h/Kconfig ++++ b/src/cpu/amd/family_10h-family_15h/Kconfig +@@ -15,6 +15,12 @@ config CPU_AMD_MODEL_10XXX + + if CPU_AMD_MODEL_10XXX + ++config USE_LARGE_DCACHE ++ bool ++ default y if CPU_AMD_SOCKET_G34_NON_AGESA ++ default y if CPU_AMD_SOCKET_C32_NON_AGESA ++ default n ++ + config NUM_IPI_STARTS + int + default 1 +@@ -37,6 +43,7 @@ config DCACHE_BSP_STACK_SIZE + + config DCACHE_BSP_STACK_SLUSH + hex ++ default 0x4000 if USE_LARGE_DCACHE + default 0x1000 + + config DCACHE_AP_STACK_SIZE +-- +1.7.9.5 + diff --git a/resources/libreboot/patch/kgpe-d16/0083-northbridge-amd-amdmct-mct_ddr3-Fix-RDIMM-errors-due.patch b/resources/libreboot/patch/kgpe-d16/0084-northbridge-amd-amdmct-mct_ddr3-Fix-RDIMM-errors-due.patch index 6bf6885..6fd6ad5 100644 --- a/resources/libreboot/patch/kgpe-d16/0083-northbridge-amd-amdmct-mct_ddr3-Fix-RDIMM-errors-due.patch +++ b/resources/libreboot/patch/kgpe-d16/0084-northbridge-amd-amdmct-mct_ddr3-Fix-RDIMM-errors-due.patch @@ -1,24 +1,24 @@ -From 34c8a0f868d298f787713a2dd3ba6852c794ae86 Mon Sep 17 00:00:00 2001 +From 162cfc9db14b515dd154ff683049bd07b994d346 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sat, 25 Jul 2015 01:23:17 -0500 -Subject: [PATCH 083/139] northbridge/amd/amdmct/mct_ddr3: Fix RDIMM errors due - to undefined number of slots +Subject: [PATCH 084/143] northbridge/amd/amdmct/mct_ddr3: Fix RDIMM errors + due to undefined number of slots Change-Id: I488511d6262ffa8207c442d133314aed0f75acfb Signed-off-by: Timothy Pearson --- - src/northbridge/amd/amdmct/mct/mct_d.h | 2 ++ - src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 24 ++++-------------------- - src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 2 ++ - src/northbridge/amd/amdmct/mct_ddr3/mctproc.c | 6 +----- - src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c | 12 ++---------- - src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 6 +----- - src/northbridge/amd/amdmct/mct_ddr3/mctwl.c | 2 -- - src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c | 20 ++++++-------------- - src/northbridge/amd/amdmct/mct_ddr3/modtrdim.c | 11 ++++++----- - src/northbridge/amd/amdmct/mct_ddr3/mwlc_d.h | 4 ---- - src/northbridge/amd/amdmct/wrappers/mcti_d.c | 7 +++++++ - 11 files changed, 31 insertions(+), 65 deletions(-) + src/northbridge/amd/amdmct/mct/mct_d.h | 2 ++ + src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 24 ++++-------------------- + src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 2 ++ + src/northbridge/amd/amdmct/mct_ddr3/mctproc.c | 6 +----- + src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c | 12 ++---------- + src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 6 +----- + src/northbridge/amd/amdmct/mct_ddr3/mctwl.c | 2 -- + src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c | 12 ++---------- + src/northbridge/amd/amdmct/mct_ddr3/modtrdim.c | 11 ++++++----- + src/northbridge/amd/amdmct/mct_ddr3/mwlc_d.h | 4 ---- + src/northbridge/amd/amdmct/wrappers/mcti_d.c | 7 +++++++ + 11 files changed, 27 insertions(+), 61 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct/mct_d.h b/src/northbridge/amd/amdmct/mct/mct_d.h index 7569300..296f3f0 100644 @@ -34,7 +34,7 @@ index 7569300..296f3f0 100644 CBMEM storage ===============================================================================*/ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c -index 1758bd6..b616c2d 100644 +index cfdfd43..9a86c08 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -803,11 +803,7 @@ static uint32_t fam15h_phy_predriver_clk_calibration_code(struct DCTStatStruc *p @@ -76,7 +76,7 @@ index 1758bd6..b616c2d 100644 uint8_t package_type; uint32_t slow_access = 0; -@@ -5868,11 +5856,7 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat, +@@ -5870,11 +5858,7 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "%s: Start\n", __func__); @@ -180,7 +180,7 @@ index 0ff4484..6b63ba0 100644 void PrepareC_DCT(struct MCTStatStruc *pMCTstat, diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c -index bd37ba7..47ad152 100644 +index 85b8378..47ad152 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c @@ -419,11 +419,7 @@ static uint16_t unbuffered_dimm_nominal_termination_emrs(uint8_t number_of_dimms @@ -209,32 +209,6 @@ index bd37ba7..47ad152 100644 if (number_of_dimms == 1) { if (MaxDimmsInstallable < 3) { -@@ -574,7 +566,7 @@ void prepareDimms(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, - if (number_of_dimms > 1) { - if (rank == 0) { - /* Get Rtt_WR for the current DIMM and rank */ -- uint16_t dynamic_term = unbuffered_dimm_dynamic_termination_emrs(pDCTData->MaxDimmsInstalled, MemClkFreq, pDCTData->DimmRanks[currDimm]); -+ uint16_t dynamic_term = unbuffered_dimm_dynamic_termination_emrs(pDCTData->MaxDimmsInstalled, MemClkFreq, pDCTData->DimmRanks[dimm]); - - /* Convert dynamic termination code to corresponding nominal termination code */ - if (dynamic_term == 0x200) -@@ -584,13 +576,13 @@ void prepareDimms(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, - else - tempW1 = 0x0; - } else { -- tempW1 = unbuffered_dimm_nominal_termination_emrs(pDCTData->MaxDimmsInstalled, MemClkFreq, pDCTData->DimmRanks[currDimm], rank); -+ tempW1 = unbuffered_dimm_nominal_termination_emrs(pDCTData->MaxDimmsInstalled, MemClkFreq, pDCTData->DimmRanks[dimm], rank); - } - } else { -- tempW1 = unbuffered_dimm_nominal_termination_emrs(pDCTData->MaxDimmsInstalled, MemClkFreq, pDCTData->DimmRanks[currDimm], rank); -+ tempW1 = unbuffered_dimm_nominal_termination_emrs(pDCTData->MaxDimmsInstalled, MemClkFreq, pDCTData->DimmRanks[dimm], rank); - } - } else { -- tempW1 = unbuffered_dimm_nominal_termination_emrs(pDCTData->MaxDimmsInstalled, MemClkFreq, pDCTData->DimmRanks[currDimm], rank); -+ tempW1 = unbuffered_dimm_nominal_termination_emrs(pDCTData->MaxDimmsInstalled, MemClkFreq, pDCTData->DimmRanks[dimm], rank); - } - } - } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/modtrdim.c b/src/northbridge/amd/amdmct/mct_ddr3/modtrdim.c index c92143c..bb4c3c0 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/modtrdim.c @@ -308,7 +282,7 @@ index 162340e..12e7c4a 100644 } sMCTStruct; diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c -index ce2329d..28d298f 100644 +index 116fb92..c8572ef 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -74,6 +74,13 @@ static u16 mctGet_NVbits(u8 index) @@ -326,5 +300,5 @@ index ce2329d..28d298f 100644 /* Maximum platform supported memclk */ val = MEM_MAX_LOAD_FREQ; -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0084-amd-amdmct-mct_ddr3-Partially-fix-up-registered-DIMM.patch b/resources/libreboot/patch/kgpe-d16/0085-amd-amdmct-mct_ddr3-Partially-fix-up-registered-DIMM.patch index 565f248..719d849 100644 --- a/resources/libreboot/patch/kgpe-d16/0084-amd-amdmct-mct_ddr3-Partially-fix-up-registered-DIMM.patch +++ b/resources/libreboot/patch/kgpe-d16/0085-amd-amdmct-mct_ddr3-Partially-fix-up-registered-DIMM.patch @@ -1,7 +1,7 @@ -From 02fa90cabc031623e5a5e05888588fb1f22949d2 Mon Sep 17 00:00:00 2001 +From a65c5d799d59fb722f56aae29f6553def67bbf99 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sun, 26 Jul 2015 00:55:43 -0500 -Subject: [PATCH 084/139] amd/amdmct/mct_ddr3: Partially fix up registered +Subject: [PATCH 085/143] amd/amdmct/mct_ddr3: Partially fix up registered DIMMs on Fam10h Sufficient support has been added to allow booting with registered @@ -11,17 +11,17 @@ work; the ECC data lanes appear to cause boot failures in some slots. Change-Id: Ieaf4cbf351908e5a89760be49a6667dc55dbc575 Signed-off-by: Timothy Pearson --- - src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 196 ++++++++++++++++++++++--- - src/northbridge/amd/amdmct/mct_ddr3/mctardk5.c | 32 ++-- - src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 58 +++++--- - src/northbridge/amd/amdmct/mct_ddr3/mctrci.c | 151 ++++++++++++------- - src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c | 8 + - src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 26 ++-- - src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c | 72 ++++++--- + src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 196 ++++++++++++++++++++++-- + src/northbridge/amd/amdmct/mct_ddr3/mctardk5.c | 32 ++-- + src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 58 ++++--- + src/northbridge/amd/amdmct/mct_ddr3/mctrci.c | 151 ++++++++++++------ + src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c | 8 + + src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 26 ++-- + src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c | 72 ++++++--- 7 files changed, 399 insertions(+), 144 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c -index b616c2d..8102f2a 100644 +index 9a86c08..b29ff3c 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -305,6 +305,120 @@ static uint16_t mhz_to_memclk_config(uint16_t freq) @@ -240,7 +240,7 @@ index b616c2d..8102f2a 100644 } if (is_fam15h()) { -@@ -2717,6 +2853,10 @@ static void DCTFinalInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *p +@@ -2719,6 +2855,10 @@ static void DCTFinalInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *p dword = 1 << DisDramInterface; Set_NB32_DCT(pDCTstat->dev_dct, dct, 0x94, dword); @@ -251,7 +251,7 @@ index b616c2d..8102f2a 100644 /* To maximize power savings when DisDramInterface=1b, * all of the MemClkDis bits should also be set. */ -@@ -3600,7 +3740,9 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, +@@ -3602,7 +3742,9 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, dword++; } @@ -262,7 +262,7 @@ index b616c2d..8102f2a 100644 DramConfigLo |= 1 << UnBuffDimm; /* Unbuffered DIMMs */ if (mctGet_NVbits(NV_ECC_CAP)) -@@ -4089,6 +4231,9 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, +@@ -4091,6 +4233,9 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, if (status >= 0) { /* SPD access is ok */ pDCTstat->DIMMPresent |= 1 << i; read_spd_bytes(pMCTstat, pDCTstat, i); @@ -272,7 +272,7 @@ index b616c2d..8102f2a 100644 crc_status = crcCheck(pDCTstat, i); if (!crc_status) { /* Try again in case there was a transient glitch */ -@@ -4388,6 +4533,10 @@ static void mct_initDCT(struct MCTStatStruc *pMCTstat, +@@ -4390,6 +4535,10 @@ static void mct_initDCT(struct MCTStatStruc *pMCTstat, val = 1 << DisDramInterface; Set_NB32_DCT(pDCTstat->dev_dct, 1, 0x94, val); @@ -283,7 +283,7 @@ index b616c2d..8102f2a 100644 /* To maximize power savings when DisDramInterface=1b, * all of the MemClkDis bits should also be set. */ -@@ -4540,8 +4689,9 @@ static u8 mct_PlatformSpec(struct MCTStatStruc *pMCTstat, +@@ -4542,8 +4691,9 @@ static u8 mct_PlatformSpec(struct MCTStatStruc *pMCTstat, } for (i=i_start; iErrCode; -@@ -4598,11 +4748,19 @@ static u8 mct_SPDCalcWidth(struct MCTStatStruc *pMCTstat, +@@ -4600,11 +4750,19 @@ static u8 mct_SPDCalcWidth(struct MCTStatStruc *pMCTstat, val = Get_NB32_DCT(pDCTstat->dev_dct, 0, 0x94); val |= 1 << DisDramInterface; Set_NB32_DCT(pDCTstat->dev_dct, 0, 0x94, val); @@ -315,7 +315,7 @@ index b616c2d..8102f2a 100644 } printk(BIOS_DEBUG, "SPDCalcWidth: Status %x\n", pDCTstat->Status); -@@ -6033,6 +6191,8 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat, +@@ -6035,6 +6193,8 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat, dword &= ~(0xf); /* RdOdtTrnOnDly = read_odt_delay */ dword |= (read_odt_delay & 0xf); Set_NB32_DCT(dev, dct, 0x240, dword); @@ -324,7 +324,7 @@ index b616c2d..8102f2a 100644 } else if (pDCTstat->LogicalCPUID & AMD_DR_Dx) { if (pDCTstat->Speed == 3) dword = 0x00000800; -@@ -6168,6 +6328,8 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat, +@@ -6170,6 +6330,8 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat, Set_NB32_index_wait_DCT(dev, i, 0xf0, 0x181, odt_pattern_0); Set_NB32_index_wait_DCT(dev, i, 0xf0, 0x182, odt_pattern_3); Set_NB32_index_wait_DCT(dev, i, 0xf0, 0x183, odt_pattern_2); @@ -956,5 +956,5 @@ index 47ad152..e5e4031 100644 + printk(BIOS_SPEW, "\tLane %02x final adjusted value: %04x\n", ByteLane, ((gross & 0x1f) << 5) | (fine & 0x1f)); } -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0085-northbridge-amd-amdmct-Fix-Family-15h-detection.patch b/resources/libreboot/patch/kgpe-d16/0086-northbridge-amd-amdmct-Fix-Family-15h-detection.patch index f9d5afb..569e6e7 100644 --- a/resources/libreboot/patch/kgpe-d16/0085-northbridge-amd-amdmct-Fix-Family-15h-detection.patch +++ b/resources/libreboot/patch/kgpe-d16/0086-northbridge-amd-amdmct-Fix-Family-15h-detection.patch @@ -1,13 +1,13 @@ -From 5ab09d94caec3d1b2cbc156fdf0b32bd7c2e518c Mon Sep 17 00:00:00 2001 +From bcab168a4fe68defa0683d49d2b7b1b73721bc8b Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Tue, 28 Jul 2015 13:45:29 -0500 -Subject: [PATCH 085/139] northbridge/amd/amdmct: Fix Family 15h detection +Subject: [PATCH 086/143] northbridge/amd/amdmct: Fix Family 15h detection Change-Id: I3623f8945bd62b7050ec609934f96543552c792b Signed-off-by: Timothy Pearson --- - src/northbridge/amd/amdmct/mct/mct.h | 3 ++- - src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 2 +- + src/northbridge/amd/amdmct/mct/mct.h | 3 ++- + src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct/mct.h b/src/northbridge/amd/amdmct/mct/mct.h @@ -45,5 +45,5 @@ index 6b5d8c1..e327d38 100644 void TrainReceiverEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA, u8 Pass); void mct_TrainDQSPos_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0087-cpu-amd-family_10h-family_15h-Fix-Family-15h-multipl.patch b/resources/libreboot/patch/kgpe-d16/0087-cpu-amd-family_10h-family_15h-Fix-Family-15h-multipl.patch deleted file mode 100644 index 2037f44..0000000 --- a/resources/libreboot/patch/kgpe-d16/0087-cpu-amd-family_10h-family_15h-Fix-Family-15h-multipl.patch +++ /dev/null @@ -1,1931 +0,0 @@ -From 0489e5c40921fd2ec7c7b5adb7ae69d180af8f9c Mon Sep 17 00:00:00 2001 -From: Timothy Pearson -Date: Thu, 30 Jul 2015 14:07:15 -0500 -Subject: [PATCH 087/139] cpu/amd/family_10h-family_15h: Fix Family 15h - multiple package support - -TEST: Booted ASUS KGPE-D16 with two Opteron 6328 processors -and several different RDIMM configurations. - -Change-Id: I171197c90f72d3496a385465937b7666cbf7e308 -Signed-off-by: Timothy Pearson ---- - src/cpu/amd/car/cache_as_ram.inc | 17 ++- - src/cpu/amd/family_10h-family_15h/defaults.h | 101 +++++++++++++-- - src/cpu/amd/family_10h-family_15h/fidvid.c | 81 ++++++------ - src/cpu/amd/family_10h-family_15h/init_cpus.c | 66 +++++++++- - src/cpu/amd/quadcore/quadcore.c | 19 +-- - src/cpu/amd/quadcore/quadcore_id.c | 1 - - src/mainboard/advansus/a785e-i/romstage.c | 2 +- - src/mainboard/amd/bimini_fam10/romstage.c | 2 +- - src/mainboard/amd/dbm690t/romstage.c | 2 +- - src/mainboard/amd/mahogany/romstage.c | 2 +- - src/mainboard/amd/mahogany_fam10/romstage.c | 2 +- - src/mainboard/amd/pistachio/romstage.c | 2 +- - src/mainboard/amd/serengeti_cheetah/romstage.c | 2 +- - .../amd/serengeti_cheetah_fam10/romstage.c | 2 +- - src/mainboard/amd/tilapia_fam10/romstage.c | 2 +- - src/mainboard/arima/hdama/romstage.c | 2 +- - src/mainboard/asrock/939a785gmh/romstage.c | 2 +- - src/mainboard/asus/a8n_e/romstage.c | 2 +- - src/mainboard/asus/a8v-e_deluxe/romstage.c | 2 +- - src/mainboard/asus/a8v-e_se/romstage.c | 2 +- - src/mainboard/asus/k8v-x/romstage.c | 2 +- - src/mainboard/asus/kfsn4-dre/romstage.c | 2 +- - src/mainboard/asus/kgpe-d16/romstage.c | 46 +++++-- - src/mainboard/asus/m2n-e/romstage.c | 2 +- - src/mainboard/asus/m2v-mx_se/romstage.c | 2 +- - src/mainboard/asus/m2v/romstage.c | 2 +- - src/mainboard/asus/m4a78-em/romstage.c | 2 +- - src/mainboard/asus/m4a785-m/romstage.c | 2 +- - src/mainboard/asus/m5a88-v/romstage.c | 2 +- - src/mainboard/avalue/eax-785e/romstage.c | 2 +- - src/mainboard/broadcom/blast/romstage.c | 2 +- - src/mainboard/gigabyte/ga_2761gxdk/romstage.c | 2 +- - src/mainboard/gigabyte/m57sli/romstage.c | 2 +- - src/mainboard/gigabyte/ma785gm/romstage.c | 2 +- - src/mainboard/gigabyte/ma785gmt/romstage.c | 2 +- - src/mainboard/gigabyte/ma78gm/romstage.c | 2 +- - src/mainboard/hp/dl145_g1/romstage.c | 2 +- - src/mainboard/hp/dl145_g3/romstage.c | 2 +- - src/mainboard/hp/dl165_g6_fam10/romstage.c | 2 +- - src/mainboard/ibm/e325/romstage.c | 2 +- - src/mainboard/ibm/e326/romstage.c | 2 +- - src/mainboard/iei/kino-780am2-fam10/romstage.c | 2 +- - src/mainboard/iwill/dk8_htx/romstage.c | 2 +- - src/mainboard/iwill/dk8s2/romstage.c | 2 +- - src/mainboard/iwill/dk8x/romstage.c | 2 +- - src/mainboard/jetway/pa78vm5/romstage.c | 2 +- - src/mainboard/kontron/kt690/romstage.c | 2 +- - src/mainboard/msi/ms7135/romstage.c | 2 +- - src/mainboard/msi/ms7260/romstage.c | 2 +- - src/mainboard/msi/ms9185/romstage.c | 2 +- - src/mainboard/msi/ms9282/romstage.c | 2 +- - src/mainboard/msi/ms9652_fam10/romstage.c | 2 +- - src/mainboard/newisys/khepri/romstage.c | 2 +- - src/mainboard/nvidia/l1_2pvv/romstage.c | 2 +- - src/mainboard/siemens/sitemp_g1p1/romstage.c | 2 +- - src/mainboard/sunw/ultra40/romstage.c | 2 +- - src/mainboard/supermicro/h8dme/romstage.c | 2 +- - src/mainboard/supermicro/h8dmr/romstage.c | 2 +- - src/mainboard/supermicro/h8dmr_fam10/romstage.c | 2 +- - src/mainboard/supermicro/h8qme_fam10/romstage.c | 2 +- - src/mainboard/supermicro/h8scm_fam10/romstage.c | 2 +- - src/mainboard/technexion/tim5690/romstage.c | 2 +- - src/mainboard/technexion/tim8690/romstage.c | 2 +- - src/mainboard/tyan/s2850/romstage.c | 2 +- - src/mainboard/tyan/s2875/romstage.c | 2 +- - src/mainboard/tyan/s2880/romstage.c | 2 +- - src/mainboard/tyan/s2881/romstage.c | 2 +- - src/mainboard/tyan/s2882/romstage.c | 2 +- - src/mainboard/tyan/s2885/romstage.c | 2 +- - src/mainboard/tyan/s2891/romstage.c | 2 +- - src/mainboard/tyan/s2892/romstage.c | 2 +- - src/mainboard/tyan/s2895/romstage.c | 2 +- - src/mainboard/tyan/s2912/romstage.c | 2 +- - src/mainboard/tyan/s2912_fam10/romstage.c | 2 +- - src/mainboard/tyan/s4880/romstage.c | 2 +- - src/mainboard/tyan/s4882/romstage.c | 2 +- - src/mainboard/winent/mb6047/romstage.c | 2 +- - src/northbridge/amd/amdht/h3finit.c | 57 ++++++++- - src/northbridge/amd/amdht/h3ncmn.c | 30 ++++- - src/northbridge/amd/amdht/ht_wrapper.c | 141 +++++++++++++++++++-- - src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 1 + - 81 files changed, 528 insertions(+), 172 deletions(-) - -diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc -index 5db9224..6bfb0e6 100644 ---- a/src/cpu/amd/car/cache_as_ram.inc -+++ b/src/cpu/amd/car/cache_as_ram.inc -@@ -525,8 +525,23 @@ CAR_FAM10_ap: - /* Fam10h NB config bit 54 was not set */ - rolb %cl, %bl - roll_cfg: -+ jmp_if_not_fam15h(ap_apicid_ready) -+ cmp $0x5, %ecx -+ jne ap_apicid_ready - -- /* Calculate stack pointer. */ -+ /* This is a multi-node CPU -+ * Adjust the maximum APIC ID to a more reasonable value -+ * given that no 32-core Family 15h processors exist -+ */ -+ movl %ebx, %ecx -+ and $0x0f, %ecx /* Get lower 4 bits of CPU number */ -+ and $0x60, %ebx /* Get node ID */ -+ shrl $0x1, %ebx /* Shift node ID part of APIC ID down by 1 */ -+ or %ecx, %ebx /* Recombine node ID and CPU number */ -+ -+ap_apicid_ready: -+ -+ /* Calculate stack pointer using adjusted APIC ID stored in ebx */ - movl $CacheSizeAPStack, %eax - mull %ebx - movl $(CacheBase + (CacheSize - (CacheSizeBSPStack + CacheSizeBSPSlush))), %esp -diff --git a/src/cpu/amd/family_10h-family_15h/defaults.h b/src/cpu/amd/family_10h-family_15h/defaults.h -index 24f87ba..513d169 100644 ---- a/src/cpu/amd/family_10h-family_15h/defaults.h -+++ b/src/cpu/amd/family_10h-family_15h/defaults.h -@@ -244,18 +244,50 @@ static const struct { - { 0, 0x68, (AMD_DR_B0 | AMD_DR_B1), - AMD_PTYPE_SVR, 0x00200000, 0x00600000 }, /* [22:21] DsNpReqLmt0 = 01b */ - -- { 0, 0x84, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, -+ { 0, 0x84, AMD_FAM10_ALL, AMD_PTYPE_ALL, - 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ - -- { 0, 0xA4, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, -+ { 0, 0xA4, AMD_FAM10_ALL, AMD_PTYPE_ALL, - 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ - -- { 0, 0xC4, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, -+ { 0, 0xC4, AMD_FAM10_ALL, AMD_PTYPE_ALL, - 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ - -- { 0, 0xE4, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, -+ { 0, 0xE4, AMD_FAM10_ALL, AMD_PTYPE_ALL, - 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ - -+ /* FIXME -+ * Non-C32 packages only -+ */ -+ { 0, 0x84, AMD_FAM15_ALL, AMD_PTYPE_ALL, -+ 0x00000000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ -+ -+ { 0, 0xA4, AMD_FAM15_ALL, AMD_PTYPE_ALL, -+ 0x00000000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ -+ -+ { 0, 0xC4, AMD_FAM15_ALL, AMD_PTYPE_ALL, -+ 0x00000000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ -+ -+ { 0, 0xE4, AMD_FAM15_ALL, AMD_PTYPE_ALL, -+ 0x00000000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ -+ -+ /* FIXME -+ * C32 package only -+ */ -+#if 0 -+ { 0, 0x84, AMD_FAM15_ALL, AMD_PTYPE_ALL, -+ 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ -+ -+ { 0, 0xA4, AMD_FAM15_ALL, AMD_PTYPE_ALL, -+ 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ -+ -+ { 0, 0xC4, AMD_FAM15_ALL, AMD_PTYPE_ALL, -+ 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ -+ -+ { 0, 0xE4, AMD_FAM15_ALL, AMD_PTYPE_ALL, -+ 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ -+#endif -+ - /* Link Global Retry Control Register */ - { 0, 0x150, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, - 0x00073900, 0x00073F00 }, -@@ -614,38 +646,79 @@ static const struct { - { 0x530A, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, - 0x00004400, 0x00006400 }, /* HT_PHY_DLL_REG */ - -- { 0xCF, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, -+ { 0xCF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, -+ 0x00000000, 0x000000FF }, /* Provide clear setting for logical -+ completeness */ -+ -+ { 0xDF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, -+ 0x00000000, 0x000000FF }, /* Provide clear setting for logical -+ completeness */ -+ -+ { 0xCF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, -+ 0x0000006D, 0x000000FF }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */ -+ -+ { 0xDF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, -+ 0x0000006D, 0x000000FF }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */ -+ -+ /* Link Phy Receiver Loop Filter Registers */ -+ { 0xD1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, -+ 0x08040000, 0x3FFFC000 }, /* [29:22] LfcMax = 20h, -+ [21:14] LfcMin = 10h */ -+ -+ { 0xC1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, -+ 0x08040000, 0x3FFFC000 }, /* [29:22] LfcMax = 20h, -+ [21:14] LfcMin = 10h */ -+ -+ { 0xD1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, -+ 0x04020000, 0x3FFFC000 }, /* [29:22] LfcMax = 10h, -+ [21:14] LfcMin = 08h */ -+ -+ { 0xC1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, -+ 0x04020000, 0x3FFFC000 }, /* [29:22] LfcMax = 10h, -+ [21:14] LfcMin = 08h */ -+ -+ { 0xC0, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, -+ 0x40040000, 0xe01F0000 }, /* [31:29] RttCtl = 02h, -+ [20:16] RttIndex = 04h */ -+ -+/* FIXME -+ * Causes lockups for some reason when more than one package is installed -+ * Debug and reactivate! -+ */ -+// #if 0 -+ { 0xCF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, - 0x00000000, 0x000000FF }, /* Provide clear setting for logical - completeness */ - -- { 0xDF, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, -+ { 0xDF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, - 0x00000000, 0x000000FF }, /* Provide clear setting for logical - completeness */ - -- { 0xCF, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, -+ { 0xCF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, - 0x0000006D, 0x000000FF }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */ - -- { 0xDF, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, -+ { 0xDF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, - 0x0000006D, 0x000000FF }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */ - - /* Link Phy Receiver Loop Filter Registers */ -- { 0xD1, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, -+ { 0xD1, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, - 0x08040000, 0x3FFFC000 }, /* [29:22] LfcMax = 20h, - [21:14] LfcMin = 10h */ - -- { 0xC1, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, -+ { 0xC1, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, - 0x08040000, 0x3FFFC000 }, /* [29:22] LfcMax = 20h, - [21:14] LfcMin = 10h */ - -- { 0xD1, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, -+ { 0xD1, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, - 0x04020000, 0x3FFFC000 }, /* [29:22] LfcMax = 10h, - [21:14] LfcMin = 08h */ - -- { 0xC1, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, -+ { 0xC1, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, - 0x04020000, 0x3FFFC000 }, /* [29:22] LfcMax = 10h, - [21:14] LfcMin = 08h */ - -- { 0xC0, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, -+ { 0xC0, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, - 0x40040000, 0xe01F0000 }, /* [31:29] RttCtl = 02h, -- [20:16] RttIndex = 04h */ -+ [20:16] RttIndex = 04h */ -+// #endif - }; -diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c -index 0e870e3..471456a 100644 ---- a/src/cpu/amd/family_10h-family_15h/fidvid.c -+++ b/src/cpu/amd/family_10h-family_15h/fidvid.c -@@ -633,44 +633,45 @@ static void prep_fid_change(void) - } - - static void waitCurrentPstate(u32 target_pstate) { -- msr_t initial_msr = rdmsr(TSC_MSR); -- msr_t pstate_msr = rdmsr(CUR_PSTATE_MSR); -- msr_t tsc_msr; -- u8 timedout ; -- -- /* paranoia ? I fear when we run fixPsNbVidBeforeWR we can enter a -- * P1 that is a copy of P0, therefore has the same NB DID but the -- * TSC will count twice per tick, so we have to wait for twice the -- * count to achieve the desired timeout. But I'm likely to -- * misunderstand this... -- */ -- u32 corrected_timeout = ( (pstate_msr.lo==1) -- && (!(rdmsr(0xC0010065).lo & NB_DID_M_ON)) ) ? -- WAIT_PSTATE_TIMEOUT*2 : WAIT_PSTATE_TIMEOUT ; -- msr_t timeout; -- -- timeout.lo = initial_msr.lo + corrected_timeout ; -- timeout.hi = initial_msr.hi; -- if ( (((u32)0xffffffff) - initial_msr.lo) < corrected_timeout ) { -- timeout.hi++; -- } -- -- // assuming TSC ticks at 1.25 ns per tick (800 MHz) -- do { -- pstate_msr = rdmsr(CUR_PSTATE_MSR); -- tsc_msr = rdmsr(TSC_MSR); -- timedout = (tsc_msr.hi > timeout.hi) -- || ((tsc_msr.hi == timeout.hi) && (tsc_msr.lo > timeout.lo )); -- } while ( (pstate_msr.lo != target_pstate) && (! timedout) ) ; -- -- if (pstate_msr.lo != target_pstate) { -- msr_t limit_msr = rdmsr(0xc0010061); -- printk(BIOS_ERR, "*** Time out waiting for P-state %01x. Current P-state %01x P-state current limit MSRC001_0061=%08x %08x\n", target_pstate, pstate_msr.lo, limit_msr.hi, limit_msr.lo); -- -- do { // should we just go on instead ? -- pstate_msr = rdmsr(CUR_PSTATE_MSR); -- } while ( pstate_msr.lo != target_pstate ) ; -- } -+ msr_t initial_msr = rdmsr(TSC_MSR); -+ msr_t pstate_msr = rdmsr(CUR_PSTATE_MSR); -+ msr_t tsc_msr; -+ u8 timedout ; -+ -+ /* paranoia ? I fear when we run fixPsNbVidBeforeWR we can enter a -+ * P1 that is a copy of P0, therefore has the same NB DID but the -+ * TSC will count twice per tick, so we have to wait for twice the -+ * count to achieve the desired timeout. But I'm likely to -+ * misunderstand this... -+ */ -+ u32 corrected_timeout = ((pstate_msr.lo==1) -+ && (!(rdmsr(0xC0010065).lo & NB_DID_M_ON)) ) ? -+ WAIT_PSTATE_TIMEOUT*2 : WAIT_PSTATE_TIMEOUT; -+ msr_t timeout; -+ -+ timeout.lo = initial_msr.lo + corrected_timeout ; -+ timeout.hi = initial_msr.hi; -+ if ( (((u32)0xffffffff) - initial_msr.lo) < corrected_timeout ) { -+ timeout.hi++; -+ } -+ -+ // assuming TSC ticks at 1.25 ns per tick (800 MHz) -+ do { -+ pstate_msr = rdmsr(CUR_PSTATE_MSR); -+ tsc_msr = rdmsr(TSC_MSR); -+ timedout = (tsc_msr.hi > timeout.hi) -+ || ((tsc_msr.hi == timeout.hi) && (tsc_msr.lo > timeout.lo )); -+ } while ( (pstate_msr.lo != target_pstate) && (! timedout) ) ; -+ -+ if (pstate_msr.lo != target_pstate) { -+ msr_t limit_msr = rdmsr(0xc0010061); -+ printk(BIOS_ERR, "*** APIC ID %02x: timed out waiting for P-state %01x. Current P-state %01x P-state current limit MSRC001_0061=%08x %08x\n", -+ cpuid_ebx(0x00000001) >> 24, target_pstate, pstate_msr.lo, limit_msr.hi, limit_msr.lo); -+ -+ do { // should we just go on instead ? -+ pstate_msr = rdmsr(CUR_PSTATE_MSR); -+ } while ( pstate_msr.lo != target_pstate ) ; -+ } - } - - static void set_pstate(u32 nonBoostedPState) { -@@ -1063,13 +1064,13 @@ static int init_fidvid_bsp(u32 bsp_apicid, u32 nodes) - APs and BSP */ - ap_apicidx.num = 0; - -- for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE_RANGE, store_ap_apicid, &ap_apicidx); -+ for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE_RANGE, -1, store_ap_apicid, &ap_apicidx); - - for (i = 0; i < ap_apicidx.num; i++) { - init_fidvid_bsp_stage1(ap_apicidx.apicid[i], &fv); - } - #else -- for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage1, &fv); -+ for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE0_ONLY, -1, init_fidvid_bsp_stage1, &fv); - #endif - - print_debug_fv("common_fid = ", fv.common_fid); -diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c -index 0044dc6..986c024 100644 ---- a/src/cpu/amd/family_10h-family_15h/init_cpus.c -+++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c -@@ -59,6 +59,8 @@ static void set_EnableCf8ExtCfg(void) - static void set_EnableCf8ExtCfg(void) { } - #endif - -+// #define DEBUG_HT_SETUP 1 -+// #define FAM10_AP_NODE_SEQUENTIAL_START 1 - - typedef void (*process_ap_t) (u32 apicid, void *gp); - -@@ -143,8 +145,8 @@ uint32_t get_boot_apic_id(uint8_t node, uint32_t core) { - //core range = 1 : core 0 only - //core range = 2 : cores other than core0 - --static void for_each_ap(u32 bsp_apicid, u32 core_range, process_ap_t process_ap, -- void *gp) -+static void for_each_ap(uint32_t bsp_apicid, uint32_t core_range, int8_t node, -+ process_ap_t process_ap, void *gp) - { - // here assume the OS don't change our apicid - u32 ap_apicid; -@@ -165,6 +167,9 @@ static void for_each_ap(u32 bsp_apicid, u32 core_range, process_ap_t process_ap, - } - - for (i = 0; i < nodes; i++) { -+ if ((node >= 0) && (i != node)) -+ continue; -+ - cores_found = get_core_num_in_bsp(i); - - u32 jstart, jend; -@@ -280,7 +285,7 @@ void wait_all_other_cores_started(u32 bsp_apicid) - { - // all aps other than core0 - printk(BIOS_DEBUG, "started ap apicid: "); -- for_each_ap(bsp_apicid, 2, wait_ap_started, (void *)0); -+ for_each_ap(bsp_apicid, 2, -1, wait_ap_started, (void *)0); - printk(BIOS_DEBUG, "\n"); - } - -@@ -373,8 +378,10 @@ static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo) - /* NB_CFG MSR is shared between cores, so we need make sure - core0 is done at first --- use wait_all_core0_started */ - if (id.coreid == 0) { -- set_apicid_cpuid_lo(); /* only set it on core0 */ -- set_EnableCf8ExtCfg(); /* only set it on core0 */ -+ /* Set InitApicIdCpuIdLo / EnableCf8ExtCfg on core0 only */ -+ if (!is_fam15h()) -+ set_apicid_cpuid_lo(); -+ set_EnableCf8ExtCfg(); - #if CONFIG_ENABLE_APIC_EXT_ID - enable_apic_ext_id(id.nodeid); - #endif -@@ -427,6 +434,7 @@ static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo) - } - // Mark the core as started. - lapic_write(LAPIC_MSG_REG, (apicid << 24) | F10_APSTATE_STARTED); -+ printk(BIOS_DEBUG, "CPU APICID %02x start flag set\n", apicid); - - if (apicid != bsp_apicid) { - /* Setup each AP's cores MSRs. -@@ -588,6 +596,34 @@ static void setup_remote_node(u8 node) - } - #endif /* CONFIG_MAX_PHYSICAL_CPUS > 1 */ - -+//it is running on core0 of node0 -+static void start_other_cores(uint32_t bsp_apicid) -+{ -+ u32 nodes; -+ u32 nodeid; -+ -+ // disable multi_core -+ if (read_option(multi_core, 0) != 0) { -+ printk(BIOS_DEBUG, "Skip additional core init\n"); -+ return; -+ } -+ -+ nodes = get_nodes(); -+ -+ for (nodeid = 0; nodeid < nodes; nodeid++) { -+ u32 cores = get_core_num_in_bsp(nodeid); -+ printk(BIOS_DEBUG, "init node: %02x cores: %02x pass 1\n", nodeid, cores); -+ if (cores > 0) { -+ real_start_other_core(nodeid, cores); -+#ifdef FAM10_AP_NODE_SEQUENTIAL_START -+ printk(BIOS_DEBUG, "waiting for core start on node %d...\n", nodeid); -+ for_each_ap(bsp_apicid, 2, nodeid, wait_ap_started, (void *)0); -+ printk(BIOS_DEBUG, "...started\n"); -+#endif -+ } -+ } -+} -+ - static void AMD_Errata281(u8 node, uint64_t revision, u32 platform) - { - /* Workaround for Transaction Scheduling Conflict in -@@ -847,6 +883,10 @@ static void AMD_SetHtPhyRegister(u8 node, u8 link, u8 entry) - - phyBase = ((u32) link << 3) | 0x180; - -+ /* Determine if link is connected and abort if not */ -+ if (!(pci_read_config32(NODE_PCI(node, 0), 0x98 + (link * 0x20)) & 0x1)) -+ return; -+ - /* Get the portal control register's initial value - * and update it to access the desired phy register - */ -@@ -1008,10 +1048,11 @@ static void cpuSetAMDPCI(u8 node) - * Hypertransport initialization has taken place. Also note - * that it is run for the first core on each node - */ -- u8 i, j; -+ uint8_t i; -+ uint8_t j; - u32 platform; - u32 val; -- u8 offset; -+ uint8_t offset; - uint32_t dword; - uint64_t revision; - -@@ -1038,6 +1079,17 @@ static void cpuSetAMDPCI(u8 node) - } - } - -+#ifdef DEBUG_HT_SETUP -+ /* Dump link settings */ -+ for (i = 0; i < 4; i++) { -+ for (j = 0; j < 4; j++) { -+ printk(BIOS_DEBUG, "Node %d link %d: type register: %08x control register: %08x extended control sublink 0: %08x 1: %08x\n", i, j, -+ pci_read_config32(NODE_PCI(i, 0), 0x98 + (j * 0x20)), pci_read_config32(NODE_PCI(i, 0), 0x84 + (j * 0x20)), -+ pci_read_config32(NODE_PCI(i, 0), 0x170 + (j * 0x4)), pci_read_config32(NODE_PCI(i, 0), 0x180 + (j * 0x4))); -+ } -+ } -+#endif -+ - for (i = 0; i < ARRAY_SIZE(fam10_htphy_default); i++) { - if ((fam10_htphy_default[i].revision & revision) && - (fam10_htphy_default[i].platform & platform)) { -diff --git a/src/cpu/amd/quadcore/quadcore.c b/src/cpu/amd/quadcore/quadcore.c -index 8a9b5ed..9c31eac 100644 ---- a/src/cpu/amd/quadcore/quadcore.c -+++ b/src/cpu/amd/quadcore/quadcore.c -@@ -31,21 +31,6 @@ - uint32_t get_boot_apic_id(uint8_t node, uint32_t core); - uint32_t wait_cpu_state(uint32_t apicid, uint32_t state, uint32_t state2); - --static inline uint8_t is_fam15h(void) --{ -- uint8_t fam15h = 0; -- uint32_t family; -- -- family = cpuid_eax(0x80000001); -- family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); -- -- if (family >= 0x6f) -- /* Family 15h or later */ -- fam15h = 1; -- -- return fam15h; --} -- - static u32 get_core_num_in_bsp(u32 nodeid) - { - u32 dword; -@@ -141,6 +126,7 @@ static void real_start_other_core(uint32_t nodeid, uint32_t cores) - } - } - -+#if (!IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX)) - //it is running on core0 of node0 - static void start_other_cores(void) - { -@@ -157,9 +143,10 @@ static void start_other_cores(void) - - for (nodeid = 0; nodeid < nodes; nodeid++) { - u32 cores = get_core_num_in_bsp(nodeid); -- printk(BIOS_DEBUG, "init node: %02x cores: %02x pass 1 \n", nodeid, cores); -+ printk(BIOS_DEBUG, "init node: %02x cores: %02x pass 1\n", nodeid, cores); - if (cores > 0) { - real_start_other_core(nodeid, cores); - } - } - } -+#endif -diff --git a/src/cpu/amd/quadcore/quadcore_id.c b/src/cpu/amd/quadcore/quadcore_id.c -index c0537b3..1f5cbd8 100644 ---- a/src/cpu/amd/quadcore/quadcore_id.c -+++ b/src/cpu/amd/quadcore/quadcore_id.c -@@ -108,7 +108,6 @@ struct node_core_id get_node_core_id(u32 nb_cfg_54) - id.nodeid = apicid & 0x7; - } - } -- - if (fam15h && dual_node) { - /* Coreboot expects each separate processor die to be on a different nodeid. - * Since the code above returns nodeid 0 even on internal node 1 some fixup is needed... -diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c -index ab717fd..591faab 100644 ---- a/src/mainboard/advansus/a785e-i/romstage.c -+++ b/src/mainboard/advansus/a785e-i/romstage.c -@@ -155,7 +155,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - #if CONFIG_LOGICAL_CPUS - /* Core0 on each node is configured. Now setup any additional cores. */ - printk(BIOS_DEBUG, "start_other_cores()\n"); -- start_other_cores(); -+ start_other_cores(bsp_apicid); - post_code(0x37); - wait_all_other_cores_started(bsp_apicid); - #endif -diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c -index 5e2cf82..95384ac 100644 ---- a/src/mainboard/amd/bimini_fam10/romstage.c -+++ b/src/mainboard/amd/bimini_fam10/romstage.c -@@ -147,7 +147,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - #if CONFIG_LOGICAL_CPUS - /* Core0 on each node is configured. Now setup any additional cores. */ - printk(BIOS_DEBUG, "start_other_cores()\n"); -- start_other_cores(); -+ start_other_cores(bsp_apicid); - post_code(0x37); - wait_all_other_cores_started(bsp_apicid); - #endif -diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c -index 1f77afa..29edf30 100644 ---- a/src/mainboard/amd/dbm690t/romstage.c -+++ b/src/mainboard/amd/dbm690t/romstage.c -@@ -98,7 +98,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - #if CONFIG_LOGICAL_CPUS - /* It is said that we should start core1 after all core0 launched */ - wait_all_core0_started(); -- start_other_cores(); -+ start_other_cores(bsp_apicid); - #endif - wait_all_aps_started(bsp_apicid); - -diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c -index 542ee60..a52a69f 100644 ---- a/src/mainboard/amd/mahogany/romstage.c -+++ b/src/mainboard/amd/mahogany/romstage.c -@@ -99,7 +99,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - #if CONFIG_LOGICAL_CPUS - /* It is said that we should start core1 after all core0 launched */ - wait_all_core0_started(); -- start_other_cores(); -+ start_other_cores(bsp_apicid); - #endif - wait_all_aps_started(bsp_apicid); - -diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c -index 025a8bb..aac6b4e 100644 ---- a/src/mainboard/amd/mahogany_fam10/romstage.c -+++ b/src/mainboard/amd/mahogany_fam10/romstage.c -@@ -149,7 +149,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - #if CONFIG_LOGICAL_CPUS - /* Core0 on each node is configured. Now setup any additional cores. */ - printk(BIOS_DEBUG, "start_other_cores()\n"); -- start_other_cores(); -+ start_other_cores(bsp_apicid); - post_code(0x37); - wait_all_other_cores_started(bsp_apicid); - #endif -diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c -index ca2edae..3ba011e 100644 ---- a/src/mainboard/amd/pistachio/romstage.c -+++ b/src/mainboard/amd/pistachio/romstage.c -@@ -97,7 +97,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - #if CONFIG_LOGICAL_CPUS - /* It is said that we should start core1 after all core0 launched */ - wait_all_core0_started(); -- start_other_cores(); -+ start_other_cores(bsp_apicid); - #endif - wait_all_aps_started(bsp_apicid); - -diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c -index 7da7925..20a34bf 100644 ---- a/src/mainboard/amd/serengeti_cheetah/romstage.c -+++ b/src/mainboard/amd/serengeti_cheetah/romstage.c -@@ -126,7 +126,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - * So here need to make sure last core0 is started, esp for two way system, - * (there may be apic id conflicts in that case) - */ -- start_other_cores(); -+ start_other_cores(bsp_apicid); - wait_all_other_cores_started(bsp_apicid); - #endif - -diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c -index 5063439..6d36575 100644 ---- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c -+++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c -@@ -255,7 +255,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - #if CONFIG_LOGICAL_CPUS - /* Core0 on each node is configured. Now setup any additional cores. */ - printk(BIOS_DEBUG, "start_other_cores()\n"); -- start_other_cores(); -+ start_other_cores(bsp_apicid); - post_code(0x37); - wait_all_other_cores_started(bsp_apicid); - #endif -diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c -index e37bc08..c9a9928 100644 ---- a/src/mainboard/amd/tilapia_fam10/romstage.c -+++ b/src/mainboard/amd/tilapia_fam10/romstage.c -@@ -149,7 +149,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - #if CONFIG_LOGICAL_CPUS - /* Core0 on each node is configured. Now setup any additional cores. */ - printk(BIOS_DEBUG, "start_other_cores()\n"); -- start_other_cores(); -+ start_other_cores(bsp_apicid); - post_code(0x37); - wait_all_other_cores_started(bsp_apicid); - #endif -diff --git a/src/mainboard/arima/hdama/romstage.c b/src/mainboard/arima/hdama/romstage.c -index d1e1c5f..0b6a833 100644 ---- a/src/mainboard/arima/hdama/romstage.c -+++ b/src/mainboard/arima/hdama/romstage.c -@@ -91,7 +91,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - - #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched -- start_other_cores(); -+ start_other_cores(bsp_apicid); - wait_all_other_cores_started(bsp_apicid); - #endif - /* This is needed to be able to call udelay(). It could be moved to -diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c -index 09c5b18..48862fd 100644 ---- a/src/mainboard/asrock/939a785gmh/romstage.c -+++ b/src/mainboard/asrock/939a785gmh/romstage.c -@@ -164,7 +164,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - #if CONFIG_LOGICAL_CPUS - /* It is said that we should start core1 after all core0 launched */ - wait_all_core0_started(); -- start_other_cores(); -+ start_other_cores(bsp_apicid); - #endif - wait_all_aps_started(bsp_apicid); - -diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c -index d1485bf..5c89a83 100644 ---- a/src/mainboard/asus/a8n_e/romstage.c -+++ b/src/mainboard/asus/a8n_e/romstage.c -@@ -121,7 +121,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - wait_all_core0_started(); - #if CONFIG_LOGICAL_CPUS - /* It is said that we should start core1 after all core0 launched. */ -- start_other_cores(); -+ start_other_cores(bsp_apicid); - wait_all_other_cores_started(bsp_apicid); - #endif - -diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c -index dc1d6ff..cf713ee 100644 ---- a/src/mainboard/asus/a8v-e_deluxe/romstage.c -+++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c -@@ -181,7 +181,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - - #if CONFIG_LOGICAL_CPUS - /* It is said that we should start core1 after all core0 launched. */ -- start_other_cores(); -+ start_other_cores(bsp_apicid); - wait_all_other_cores_started(bsp_apicid); - #endif - init_timer(); -diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c -index 0531cd3..eba2acf 100644 ---- a/src/mainboard/asus/a8v-e_se/romstage.c -+++ b/src/mainboard/asus/a8v-e_se/romstage.c -@@ -181,7 +181,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - - #if CONFIG_LOGICAL_CPUS - /* It is said that we should start core1 after all core0 launched. */ -- start_other_cores(); -+ start_other_cores(bsp_apicid); - wait_all_other_cores_started(bsp_apicid); - #endif - init_timer(); -diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c -index 45103fd..f1100dd 100644 ---- a/src/mainboard/asus/k8v-x/romstage.c -+++ b/src/mainboard/asus/k8v-x/romstage.c -@@ -136,7 +136,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - - #if CONFIG_LOGICAL_CPUS - /* It is said that we should start core1 after all core0 launched. */ -- start_other_cores(); -+ start_other_cores(bsp_apicid); - wait_all_other_cores_started(bsp_apicid); - #endif - init_timer(); -diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c -index dd5c7dc..1307e57 100644 ---- a/src/mainboard/asus/kfsn4-dre/romstage.c -+++ b/src/mainboard/asus/kfsn4-dre/romstage.c -@@ -288,7 +288,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) { - /* Core0 on each node is configured. Now setup any additional cores. */ - printk(BIOS_DEBUG, "start_other_cores()\n"); -- start_other_cores(); -+ start_other_cores(bsp_apicid); - post_code(0x37); - wait_all_other_cores_started(bsp_apicid); - } -diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c -index 9ea7cec..3504126 100644 ---- a/src/mainboard/asus/kgpe-d16/romstage.c -+++ b/src/mainboard/asus/kgpe-d16/romstage.c -@@ -97,7 +97,18 @@ static void switch_spd_mux(uint8_t channel) - pci_write_config8(PCI_DEV(0, 0x14, 0), 0x54, byte); - } - --static const uint8_t spd_addr[] = { -+static const uint8_t spd_addr_fam15[] = { -+ // Socket 0 Node 0 ("Node 0") -+ RC00, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0, -+ // Socket 0 Node 1 ("Node 1") -+ RC00, DIMM4, DIMM5, 0, 0, DIMM6, DIMM7, 0, 0, -+ // Socket 1 Node 0 ("Node 2") -+ RC01, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0, -+ // Socket 1 Node 1 ("Node 3") -+ RC01, DIMM4, DIMM5, 0, 0, DIMM6, DIMM7, 0, 0, -+}; -+ -+static const uint8_t spd_addr_fam10[] = { - // Socket 0 Node 0 ("Node 0") - RC00, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0, - // Socket 0 Node 1 ("Node 1") -@@ -117,10 +128,10 @@ static void activate_spd_rom(const struct mem_controller *ctrl) { - switch_spd_mux(0x2); - } else if (ctrl->node_id == 1) { - printk(BIOS_DEBUG, "enable_spd_node1()\n"); -- switch_spd_mux((sysinfo->nodes <= 2)?0x2:0x3); -+ switch_spd_mux((is_fam15h() || (sysinfo->nodes <= 2))?0x2:0x3); - } else if (ctrl->node_id == 2) { - printk(BIOS_DEBUG, "enable_spd_node2()\n"); -- switch_spd_mux((sysinfo->nodes <= 2)?0x3:0x2); -+ switch_spd_mux((is_fam15h() || (sysinfo->nodes <= 2))?0x3:0x2); - } else if (ctrl->node_id == 3) { - printk(BIOS_DEBUG, "enable_spd_node3()\n"); - switch_spd_mux(0x3); -@@ -306,18 +317,25 @@ void initialize_romstage_console_lock(void) - - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - { -+ uint32_t esp; -+ __asm__ volatile ( -+ "movl %%esp, %0" -+ : "=r" (esp) -+ ); -+ - struct sys_info *sysinfo = &sysinfo_car; - - uint32_t bsp_apicid = 0, val; - uint8_t byte; - msr_t msr; - -- timestamp_init(timestamp_get()); -- timestamp_add_now(TS_START_ROMSTAGE); -- - int s3resume = acpi_is_wakeup_s3(); - - if (!cpu_init_detectedx && boot_cpu()) { -+ /* Initial timestamp */ -+ timestamp_init(timestamp_get()); -+ timestamp_add_now(TS_START_ROMSTAGE); -+ - /* Initialize the printk spinlock */ - initialize_romstage_console_lock(); - -@@ -344,6 +362,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - pci_write_config8(PCI_DEV(0, 0x14, 3), 0x78, byte); - } - -+ printk(BIOS_SPEW, "Initial stack pointer: %08x\n", esp); -+ - post_code(0x30); - - if (bist == 0) -@@ -397,7 +417,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) { - /* Core0 on each node is configured. Now setup any additional cores. */ - printk(BIOS_DEBUG, "start_other_cores()\n"); -- start_other_cores(); -+ start_other_cores(bsp_apicid); - post_code(0x37); - wait_all_other_cores_started(bsp_apicid); - } -@@ -455,7 +475,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - - /* It's the time to set ctrl in sysinfo now; */ - printk(BIOS_DEBUG, "fill_mem_ctrl() detected %d nodes\n", sysinfo->nodes); -- fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); -+ if (is_fam15h()) -+ fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr_fam15); -+ else -+ fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr_fam10); - post_code(0x3D); - - #if 0 -@@ -527,5 +550,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - */ - BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) - { -+ /* Force BUID to 0 */ -+ static const u8 swaplist[] = {0, 0, 0xFF, 0, 0xFF}; -+ if ((node == 0) && (link == 1)) { /* BSP SB link */ -+ *List = swaplist; -+ return 1; -+ } -+ - return 0; - } -\ No newline at end of file -diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c -index 306c124..351a411 100644 ---- a/src/mainboard/asus/m2n-e/romstage.c -+++ b/src/mainboard/asus/m2n-e/romstage.c -@@ -129,7 +129,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - * started, esp for two way system (there may be APIC ID conflicts in - * that case). - */ -- start_other_cores(); -+ start_other_cores(bsp_apicid); - wait_all_other_cores_started(bsp_apicid); - #endif - -diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c -index 89e24a4..4364c6c 100644 ---- a/src/mainboard/asus/m2v-mx_se/romstage.c -+++ b/src/mainboard/asus/m2v-mx_se/romstage.c -@@ -147,7 +147,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - - #if CONFIG_LOGICAL_CPUS - /* It is said that we should start core1 after all core0 launched. */ -- start_other_cores(); -+ start_other_cores(bsp_apicid); - wait_all_other_cores_started(bsp_apicid); - #endif - init_timer(); -diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c -index 8c99080..60cb1d4 100644 ---- a/src/mainboard/asus/m2v/romstage.c -+++ b/src/mainboard/asus/m2v/romstage.c -@@ -247,7 +247,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - - #if CONFIG_LOGICAL_CPUS - /* It is said that we should start core1 after all core0 launched. */ -- start_other_cores(); -+ start_other_cores(bsp_apicid); - wait_all_other_cores_started(bsp_apicid); - #endif - init_timer(); -diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c -index 82b96bf..75894d8 100644 ---- a/src/mainboard/asus/m4a78-em/romstage.c -+++ b/src/mainboard/asus/m4a78-em/romstage.c -@@ -151,7 +151,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - #if CONFIG_LOGICAL_CPUS - /* Core0 on each node is configured. Now setup any additional cores. */ - printk(BIOS_DEBUG, "start_other_cores()\n"); -- start_other_cores(); -+ start_other_cores(bsp_apicid); - post_code(0x37); - wait_all_other_cores_started(bsp_apicid); - #endif -diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c -index 30975fa..f81cb95 100644 ---- a/src/mainboard/asus/m4a785-m/romstage.c -+++ b/src/mainboard/asus/m4a785-m/romstage.c -@@ -151,7 +151,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - #if CONFIG_LOGICAL_CPUS - /* Core0 on each node is configured. Now setup any additional cores. */ - printk(BIOS_DEBUG, "start_other_cores()\n"); -- start_other_cores(); -+ start_other_cores(bsp_apicid); - post_code(0x37); - wait_all_other_cores_started(bsp_apicid); - #endif -diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c -index 4edaba2..9914025 100644 ---- a/src/mainboard/asus/m5a88-v/romstage.c -+++ b/src/mainboard/asus/m5a88-v/romstage.c -@@ -152,7 +152,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - #if CONFIG_LOGICAL_CPUS - /* Core0 on each node is configured. Now setup any additional cores. */ - printk(BIOS_DEBUG, "start_other_cores()\n"); -- start_other_cores(); -+ start_other_cores(bsp_apicid); - post_code(0x37); - wait_all_other_cores_started(bsp_apicid); - #endif -diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c -index 447012b..c57454d 100644 ---- a/src/mainboard/avalue/eax-785e/romstage.c -+++ b/src/mainboard/avalue/eax-785e/romstage.c -@@ -156,7 +156,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - #if CONFIG_LOGICAL_CPUS - /* Core0 on each node is configured. Now setup any additional cores. */ - printk(BIOS_DEBUG, "start_other_cores()\n"); -- start_other_cores(); -+ start_other_cores(bsp_apicid); - post_code(0x37); - wait_all_other_cores_started(bsp_apicid); - #endif -diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c -index d7ba383..a7c0a84 100644 ---- a/src/mainboard/broadcom/blast/romstage.c -+++ b/src/mainboard/broadcom/blast/romstage.c -@@ -93,7 +93,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched - wait_all_core0_started(); -- start_other_cores(); -+ start_other_cores(bsp_apicid); - #endif - wait_all_aps_started(bsp_apicid); - -diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c -index 008a23f..8045164 100644 ---- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c -+++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c -@@ -150,7 +150,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - * So here need to make sure last core0 is started, esp for two way system, - * (there may be apic id conflicts in that case) - */ -- start_other_cores(); -+ start_other_cores(bsp_apicid); - wait_all_other_cores_started(bsp_apicid); - #endif - -diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c -index fe97e68..e1c2fe3 100644 ---- a/src/mainboard/gigabyte/m57sli/romstage.c -+++ b/src/mainboard/gigabyte/m57sli/romstage.c -@@ -157,7 +157,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - * So here need to make sure last core0 is started, esp for two way system, - * (there may be apic id conflicts in that case) - */ -- start_other_cores(); -+ start_other_cores(bsp_apicid); - wait_all_other_cores_started(bsp_apicid); - #endif - -diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c -index 444e59d..ae661e8 100644 ---- a/src/mainboard/gigabyte/ma785gm/romstage.c -+++ b/src/mainboard/gigabyte/ma785gm/romstage.c -@@ -146,7 +146,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - #if CONFIG_LOGICAL_CPUS - /* Core0 on each node is configured. Now setup any additional cores. */ - printk(BIOS_DEBUG, "start_other_cores()\n"); -- start_other_cores(); -+ start_other_cores(bsp_apicid); - post_code(0x37); - wait_all_other_cores_started(bsp_apicid); - #endif -diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c -index 705d7c5..968aa8f 100644 ---- a/src/mainboard/gigabyte/ma785gmt/romstage.c -+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c -@@ -146,7 +146,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - #if CONFIG_LOGICAL_CPUS - /* Core0 on each node is configured. Now setup any additional cores. */ - printk(BIOS_DEBUG, "start_other_cores()\n"); -- start_other_cores(); -+ start_other_cores(bsp_apicid); - post_code(0x37); - wait_all_other_cores_started(bsp_apicid); - #endif -diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c -index 5d21801..7e18724 100644 ---- a/src/mainboard/gigabyte/ma78gm/romstage.c -+++ b/src/mainboard/gigabyte/ma78gm/romstage.c -@@ -149,7 +149,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - #if CONFIG_LOGICAL_CPUS - /* Core0 on each node is configured. Now setup any additional cores. */ - printk(BIOS_DEBUG, "start_other_cores()\n"); -- start_other_cores(); -+ start_other_cores(bsp_apicid); - post_code(0x37); - wait_all_other_cores_started(bsp_apicid); - #endif -diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c -index 8b5b428..e2b215b 100644 ---- a/src/mainboard/hp/dl145_g1/romstage.c -+++ b/src/mainboard/hp/dl145_g1/romstage.c -@@ -129,7 +129,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - wait_all_core0_started(); - #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched -- start_other_cores(); -+ start_other_cores(bsp_apicid); - wait_all_other_cores_started(bsp_apicid); - #endif - -diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c -index d8e8a16..d6e72d2 100644 ---- a/src/mainboard/hp/dl145_g3/romstage.c -+++ b/src/mainboard/hp/dl145_g3/romstage.c -@@ -163,7 +163,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - * So here need to make sure last core0 is started, esp for two way system, - * (there may be apic id conflicts in that case) - */ -- start_other_cores(); -+ start_other_cores(bsp_apicid); - wait_all_other_cores_started(bsp_apicid); - #endif - -diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c -index 26c0bb9..e70d274 100644 ---- a/src/mainboard/hp/dl165_g6_fam10/romstage.c -+++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c -@@ -160,7 +160,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - #if CONFIG_LOGICAL_CPUS - /* Core0 on each node is configured. Now setup any additional cores. */ - printk(BIOS_DEBUG, "start_other_cores()\n"); -- start_other_cores(); -+ start_other_cores(bsp_apicid); - post_code(0x37); - wait_all_other_cores_started(bsp_apicid); - #endif -diff --git a/src/mainboard/ibm/e325/romstage.c b/src/mainboard/ibm/e325/romstage.c -index 48e7de8..960b46b 100644 ---- a/src/mainboard/ibm/e325/romstage.c -+++ b/src/mainboard/ibm/e325/romstage.c -@@ -100,7 +100,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - - #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched -- start_other_cores(); -+ start_other_cores(bsp_apicid); - #endif - // automatically set that for you, but you might meet tight space - needs_reset |= ht_setup_chains_x(); -diff --git a/src/mainboard/ibm/e326/romstage.c b/src/mainboard/ibm/e326/romstage.c -index a27a218..1b88035 100644 ---- a/src/mainboard/ibm/e326/romstage.c -+++ b/src/mainboard/ibm/e326/romstage.c -@@ -100,7 +100,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - - #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched -- start_other_cores(); -+ start_other_cores(bsp_apicid); - #endif - // automatically set that for you, but you might meet tight space - needs_reset |= ht_setup_chains_x(); -diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c -index 321eea6..89cfe83 100644 ---- a/src/mainboard/iei/kino-780am2-fam10/romstage.c -+++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c -@@ -149,7 +149,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - #if CONFIG_LOGICAL_CPUS - /* Core0 on each node is configured. Now setup any additional cores. */ - printk(BIOS_DEBUG, "start_other_cores()\n"); -- start_other_cores(); -+ start_other_cores(bsp_apicid); - post_code(0x37); - wait_all_other_cores_started(bsp_apicid); - #endif -diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c -index 9b5b38d..a1e45f0 100644 ---- a/src/mainboard/iwill/dk8_htx/romstage.c -+++ b/src/mainboard/iwill/dk8_htx/romstage.c -@@ -104,7 +104,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - * So here need to make sure last core0 is started, esp for two way system, - * (there may be apic id conflicts in that case) - */ -- start_other_cores(); -+ start_other_cores(bsp_apicid); - wait_all_other_cores_started(bsp_apicid); - #endif - -diff --git a/src/mainboard/iwill/dk8s2/romstage.c b/src/mainboard/iwill/dk8s2/romstage.c -index 601c649..d140baf 100644 ---- a/src/mainboard/iwill/dk8s2/romstage.c -+++ b/src/mainboard/iwill/dk8s2/romstage.c -@@ -105,7 +105,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - * So here need to make sure last core0 is started, esp for two way system, - * (there may be apic id conflicts in that case) - */ -- start_other_cores(); -+ start_other_cores(bsp_apicid); - wait_all_other_cores_started(bsp_apicid); - #endif - -diff --git a/src/mainboard/iwill/dk8x/romstage.c b/src/mainboard/iwill/dk8x/romstage.c -index 273e9f1..bdac810 100644 ---- a/src/mainboard/iwill/dk8x/romstage.c -+++ b/src/mainboard/iwill/dk8x/romstage.c -@@ -105,7 +105,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - * So here need to make sure last core0 is started, esp for two way system, - * (there may be apic id conflicts in that case) - */ -- start_other_cores(); -+ start_other_cores(bsp_apicid); - wait_all_other_cores_started(bsp_apicid); - #endif - -diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c -index 93dd2ce..6106b66 100644 ---- a/src/mainboard/jetway/pa78vm5/romstage.c -+++ b/src/mainboard/jetway/pa78vm5/romstage.c -@@ -154,7 +154,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - #if CONFIG_LOGICAL_CPUS - /* Core0 on each node is configured. Now setup any additional cores. */ - printk(BIOS_DEBUG, "start_other_cores()\n"); -- start_other_cores(); -+ start_other_cores(bsp_apicid); - post_code(0x37); - wait_all_other_cores_started(bsp_apicid); - #endif -diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c -index d8db6aa..7210dae 100644 ---- a/src/mainboard/kontron/kt690/romstage.c -+++ b/src/mainboard/kontron/kt690/romstage.c -@@ -100,7 +100,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - #if CONFIG_LOGICAL_CPUS - /* It is said that we should start core1 after all core0 launched */ - wait_all_core0_started(); -- start_other_cores(); -+ start_other_cores(bsp_apicid); - #endif - wait_all_aps_started(bsp_apicid); - -diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c -index 68cddad..34dbb8a 100644 ---- a/src/mainboard/msi/ms7135/romstage.c -+++ b/src/mainboard/msi/ms7135/romstage.c -@@ -139,7 +139,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - wait_all_core0_started(); - #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched -- start_other_cores(); -+ start_other_cores(bsp_apicid); - wait_all_other_cores_started(bsp_apicid); - #endif - -diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c -index 15f389a..be82fd0 100644 ---- a/src/mainboard/msi/ms7260/romstage.c -+++ b/src/mainboard/msi/ms7260/romstage.c -@@ -146,7 +146,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - * started, esp for two way system (there may be APIC ID conflicts in - * that case). - */ -- start_other_cores(); -+ start_other_cores(bsp_apicid); - wait_all_other_cores_started(bsp_apicid); - #endif - -diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c -index 795a890..fc5cfd6 100644 ---- a/src/mainboard/msi/ms9185/romstage.c -+++ b/src/mainboard/msi/ms9185/romstage.c -@@ -134,7 +134,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - * So here need to make sure last core0 is started, esp for two way system, - * (there may be apic id conflicts in that case) - */ -- start_other_cores(); -+ start_other_cores(bsp_apicid); - //bx_a010- wait_all_other_cores_started(bsp_apicid); - #endif - -diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c -index f5b75cc..05d8aee 100644 ---- a/src/mainboard/msi/ms9282/romstage.c -+++ b/src/mainboard/msi/ms9282/romstage.c -@@ -144,7 +144,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - - #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched -- start_other_cores(); -+ start_other_cores(bsp_apicid); - //wait_all_other_cores_started(bsp_apicid); - #endif - ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn -diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c -index 5da971f..f552db5 100644 ---- a/src/mainboard/msi/ms9652_fam10/romstage.c -+++ b/src/mainboard/msi/ms9652_fam10/romstage.c -@@ -177,7 +177,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - #if CONFIG_LOGICAL_CPUS - /* Core0 on each node is configured. Now setup any additional cores. */ - printk(BIOS_DEBUG, "start_other_cores()\n"); -- start_other_cores(); -+ start_other_cores(bsp_apicid); - post_code(0x37); - printk(BIOS_DEBUG, "wait_all_other_cores_started()\n"); - wait_all_other_cores_started(bsp_apicid); -diff --git a/src/mainboard/newisys/khepri/romstage.c b/src/mainboard/newisys/khepri/romstage.c -index bf8a0a2..5174f32 100644 ---- a/src/mainboard/newisys/khepri/romstage.c -+++ b/src/mainboard/newisys/khepri/romstage.c -@@ -102,7 +102,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - wait_all_core0_started(); - #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched -- start_other_cores(); -+ start_other_cores(bsp_apicid); - wait_all_other_cores_started(bsp_apicid); - #endif - -diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c -index b5731c8..3725c04 100644 ---- a/src/mainboard/nvidia/l1_2pvv/romstage.c -+++ b/src/mainboard/nvidia/l1_2pvv/romstage.c -@@ -143,7 +143,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - * So here need to make sure last core0 is started, esp for two way system, - * (there may be apic id conflicts in that case) - */ -- start_other_cores(); -+ start_other_cores(bsp_apicid); - wait_all_other_cores_started(bsp_apicid); - #endif - -diff --git a/src/mainboard/siemens/sitemp_g1p1/romstage.c b/src/mainboard/siemens/sitemp_g1p1/romstage.c -index 1b2501f..96cec72 100644 ---- a/src/mainboard/siemens/sitemp_g1p1/romstage.c -+++ b/src/mainboard/siemens/sitemp_g1p1/romstage.c -@@ -127,7 +127,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - #if CONFIG_LOGICAL_CPUS - /* It is said that we should start core1 after all core0 launched */ - wait_all_core0_started(); -- start_other_cores(); -+ start_other_cores(bsp_apicid); - #endif - wait_all_aps_started(bsp_apicid); - -diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c -index ecb7fe7..13aa272 100644 ---- a/src/mainboard/sunw/ultra40/romstage.c -+++ b/src/mainboard/sunw/ultra40/romstage.c -@@ -127,7 +127,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - wait_all_core0_started(); - #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched -- start_other_cores(); -+ start_other_cores(bsp_apicid); - wait_all_other_cores_started(bsp_apicid); - #endif - -diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c -index c10aba4..b9082a3 100644 ---- a/src/mainboard/supermicro/h8dme/romstage.c -+++ b/src/mainboard/supermicro/h8dme/romstage.c -@@ -161,7 +161,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - * So here need to make sure last core0 is started, esp for two way system, - * (there may be apic id conflicts in that case) - */ -- start_other_cores(); -+ start_other_cores(bsp_apicid); - wait_all_other_cores_started(bsp_apicid); - #endif - -diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c -index 1e5582c..f31f586 100644 ---- a/src/mainboard/supermicro/h8dmr/romstage.c -+++ b/src/mainboard/supermicro/h8dmr/romstage.c -@@ -138,7 +138,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - * So here need to make sure last core0 is started, esp for two way system, - * (there may be apic id conflicts in that case) - */ -- start_other_cores(); -+ start_other_cores(bsp_apicid); - wait_all_other_cores_started(bsp_apicid); - #endif - -diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c -index 1425546..333a213 100644 ---- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c -+++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c -@@ -171,7 +171,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - #if CONFIG_LOGICAL_CPUS - /* Core0 on each node is configured. Now setup any additional cores. */ - printk(BIOS_DEBUG, "start_other_cores()\n"); -- start_other_cores(); -+ start_other_cores(bsp_apicid); - post_code(0x37); - wait_all_other_cores_started(bsp_apicid); - #endif -diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c -index 4721eba..8caf615 100644 ---- a/src/mainboard/supermicro/h8qme_fam10/romstage.c -+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c -@@ -238,7 +238,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - #if CONFIG_LOGICAL_CPUS - /* Core0 on each node is configured. Now setup any additional cores. */ - printk(BIOS_DEBUG, "start_other_cores()\n"); -- start_other_cores(); -+ start_other_cores(bsp_apicid); - post_code(0x37); - wait_all_other_cores_started(bsp_apicid); - #endif -diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c -index 858aca0..0e5adcd 100644 ---- a/src/mainboard/supermicro/h8scm_fam10/romstage.c -+++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c -@@ -162,7 +162,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - #if CONFIG_LOGICAL_CPUS - /* Core0 on each node is configured. Now setup any additional cores. */ - printk(BIOS_DEBUG, "start_other_cores()\n"); -- start_other_cores(); -+ start_other_cores(bsp_apicid); - post_code(0x37); - wait_all_other_cores_started(bsp_apicid); - #endif -diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c -index 27c0024..f3f3117 100644 ---- a/src/mainboard/technexion/tim5690/romstage.c -+++ b/src/mainboard/technexion/tim5690/romstage.c -@@ -105,7 +105,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - #if CONFIG_LOGICAL_CPUS - /* It is said that we should start core1 after all core0 launched */ - wait_all_core0_started(); -- start_other_cores(); -+ start_other_cores(bsp_apicid); - #endif - wait_all_aps_started(bsp_apicid); - -diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c -index 4830bf9..368eb0e 100644 ---- a/src/mainboard/technexion/tim8690/romstage.c -+++ b/src/mainboard/technexion/tim8690/romstage.c -@@ -100,7 +100,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - #if CONFIG_LOGICAL_CPUS - /* It is said that we should start core1 after all core0 launched */ - wait_all_core0_started(); -- start_other_cores(); -+ start_other_cores(bsp_apicid); - #endif - wait_all_aps_started(bsp_apicid); - -diff --git a/src/mainboard/tyan/s2850/romstage.c b/src/mainboard/tyan/s2850/romstage.c -index bb91a2a..9b5aff6 100644 ---- a/src/mainboard/tyan/s2850/romstage.c -+++ b/src/mainboard/tyan/s2850/romstage.c -@@ -88,7 +88,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - - #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched -- start_other_cores(); -+ start_other_cores(bsp_apicid); - #endif - needs_reset |= ht_setup_chains_x(); - -diff --git a/src/mainboard/tyan/s2875/romstage.c b/src/mainboard/tyan/s2875/romstage.c -index e63734e..41ae094 100644 ---- a/src/mainboard/tyan/s2875/romstage.c -+++ b/src/mainboard/tyan/s2875/romstage.c -@@ -97,7 +97,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - - #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched -- start_other_cores(); -+ start_other_cores(bsp_apicid); - #endif - needs_reset |= ht_setup_chains_x(); - -diff --git a/src/mainboard/tyan/s2880/romstage.c b/src/mainboard/tyan/s2880/romstage.c -index dba58f2..c632b62 100644 ---- a/src/mainboard/tyan/s2880/romstage.c -+++ b/src/mainboard/tyan/s2880/romstage.c -@@ -97,7 +97,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - - #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched -- start_other_cores(); -+ start_other_cores(bsp_apicid); - #endif - // automatically set that for you, but you might meet tight space - needs_reset |= ht_setup_chains_x(); -diff --git a/src/mainboard/tyan/s2881/romstage.c b/src/mainboard/tyan/s2881/romstage.c -index b97ba18..c134f2d 100644 ---- a/src/mainboard/tyan/s2881/romstage.c -+++ b/src/mainboard/tyan/s2881/romstage.c -@@ -91,7 +91,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - wait_all_core0_started(); - #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched -- start_other_cores(); -+ start_other_cores(bsp_apicid); - wait_all_other_cores_started(bsp_apicid); - #endif - -diff --git a/src/mainboard/tyan/s2882/romstage.c b/src/mainboard/tyan/s2882/romstage.c -index dba58f2..c632b62 100644 ---- a/src/mainboard/tyan/s2882/romstage.c -+++ b/src/mainboard/tyan/s2882/romstage.c -@@ -97,7 +97,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - - #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched -- start_other_cores(); -+ start_other_cores(bsp_apicid); - #endif - // automatically set that for you, but you might meet tight space - needs_reset |= ht_setup_chains_x(); -diff --git a/src/mainboard/tyan/s2885/romstage.c b/src/mainboard/tyan/s2885/romstage.c -index fdf9606..81e3817 100644 ---- a/src/mainboard/tyan/s2885/romstage.c -+++ b/src/mainboard/tyan/s2885/romstage.c -@@ -91,7 +91,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - wait_all_core0_started(); - #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched -- start_other_cores(); -+ start_other_cores(bsp_apicid); - wait_all_other_cores_started(bsp_apicid); - #endif - -diff --git a/src/mainboard/tyan/s2891/romstage.c b/src/mainboard/tyan/s2891/romstage.c -index 93189f1..7d170b5 100644 ---- a/src/mainboard/tyan/s2891/romstage.c -+++ b/src/mainboard/tyan/s2891/romstage.c -@@ -112,7 +112,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - wait_all_core0_started(); - #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched -- start_other_cores(); -+ start_other_cores(bsp_apicid); - wait_all_other_cores_started(bsp_apicid); - #endif - -diff --git a/src/mainboard/tyan/s2892/romstage.c b/src/mainboard/tyan/s2892/romstage.c -index 881972d..460c909 100644 ---- a/src/mainboard/tyan/s2892/romstage.c -+++ b/src/mainboard/tyan/s2892/romstage.c -@@ -103,7 +103,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - wait_all_core0_started(); - #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched -- start_other_cores(); -+ start_other_cores(bsp_apicid); - wait_all_other_cores_started(bsp_apicid); - #endif - -diff --git a/src/mainboard/tyan/s2895/romstage.c b/src/mainboard/tyan/s2895/romstage.c -index 086df63..5f3169a 100644 ---- a/src/mainboard/tyan/s2895/romstage.c -+++ b/src/mainboard/tyan/s2895/romstage.c -@@ -130,7 +130,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - wait_all_core0_started(); - - // It is said that we should start core1 after all core0 launched -- start_other_cores(); -+ start_other_cores(bsp_apicid); - wait_all_other_cores_started(bsp_apicid); - - needs_reset |= ht_setup_chains_x(); -diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c -index c608bb9..bbe2e43 100644 ---- a/src/mainboard/tyan/s2912/romstage.c -+++ b/src/mainboard/tyan/s2912/romstage.c -@@ -141,7 +141,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - * So here need to make sure last core0 is started, esp for two way system, - * (there may be apic id conflicts in that case) - */ -- start_other_cores(); -+ start_other_cores(bsp_apicid); - wait_all_other_cores_started(bsp_apicid); - #endif - -diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c -index cdf51b1..0fe004e 100644 ---- a/src/mainboard/tyan/s2912_fam10/romstage.c -+++ b/src/mainboard/tyan/s2912_fam10/romstage.c -@@ -173,7 +173,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - #if CONFIG_LOGICAL_CPUS - /* Core0 on each node is configured. Now setup any additional cores. */ - printk(BIOS_DEBUG, "start_other_cores()\n"); -- start_other_cores(); -+ start_other_cores(bsp_apicid); - post_code(0x37); - wait_all_other_cores_started(bsp_apicid); - #endif -diff --git a/src/mainboard/tyan/s4880/romstage.c b/src/mainboard/tyan/s4880/romstage.c -index 5c0b128..fcf9568 100644 ---- a/src/mainboard/tyan/s4880/romstage.c -+++ b/src/mainboard/tyan/s4880/romstage.c -@@ -132,7 +132,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - - #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched -- start_other_cores(); -+ start_other_cores(bsp_apicid); - #endif - // automatically set that for you, but you might meet tight space - needs_reset |= ht_setup_chains_x(); -diff --git a/src/mainboard/tyan/s4882/romstage.c b/src/mainboard/tyan/s4882/romstage.c -index ed84ab6..f2ea852 100644 ---- a/src/mainboard/tyan/s4882/romstage.c -+++ b/src/mainboard/tyan/s4882/romstage.c -@@ -108,7 +108,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - wait_all_core0_started(); - #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched -- start_other_cores(); -+ start_other_cores(bsp_apicid); - wait_all_other_cores_started(bsp_apicid); - #endif - -diff --git a/src/mainboard/winent/mb6047/romstage.c b/src/mainboard/winent/mb6047/romstage.c -index 20eb92e..76e6393 100644 ---- a/src/mainboard/winent/mb6047/romstage.c -+++ b/src/mainboard/winent/mb6047/romstage.c -@@ -99,7 +99,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) - - wait_all_core0_started(); - // It is said that we should start core1 after all core0 launched -- start_other_cores(); -+ start_other_cores(bsp_apicid); - wait_all_other_cores_started(bsp_apicid); - - #if CONFIG_SET_FIDVID -diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c -index 849f4a8..82bf885 100644 ---- a/src/northbridge/amd/amdht/h3finit.c -+++ b/src/northbridge/amd/amdht/h3finit.c -@@ -389,13 +389,49 @@ static u8 convertNodeToLink(u8 srcNode, u8 targetNode, sMainData *pDat) - */ - static void htDiscoveryFloodFill(sMainData *pDat) - { -- u8 currentNode = 0; -- u8 currentLink; -+ uint8_t currentNode = 0; -+ uint8_t currentLink; -+ uint8_t currentLinkID; -+ -+ /* NOTE -+ * Each node inside a dual node (socket G34) processor must share -+ * an adjacent node ID. Alter the link scan order such that the -+ * other internal node is always scanned first... -+ */ -+ uint8_t currentLinkScanOrder_Default[8] = {0, 1, 2, 3, 4, 5, 6, 7}; -+ uint8_t currentLinkScanOrder_G34_Fam10[8] = {1, 0, 2, 3, 4, 5, 6, 7}; -+ uint8_t currentLinkScanOrder_G34_Fam15[8] = {2, 0, 1, 3, 4, 5, 6, 7}; -+ -+ uint8_t fam15h = 0; -+ uint8_t rev_gte_d = 0; -+ uint8_t dual_node = 0; -+ uint32_t f3xe8; -+ uint32_t family; -+ uint32_t model; -+ -+ f3xe8 = pci_read_config32(NODE_PCI(0, 3), 0xe8); -+ -+ family = model = cpuid_eax(0x80000001); -+ model = ((model & 0xf0000) >> 12) | ((model & 0xf0) >> 4); -+ family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); -+ -+ if (family >= 0x6f) { -+ /* Family 15h or later */ -+ fam15h = 1; -+ } -+ -+ if ((model >= 0x8) || fam15h) -+ /* Revision D or later */ -+ rev_gte_d = 1; -+ -+ if (rev_gte_d) -+ /* Check for dual node capability */ -+ if (f3xe8 & 0x20000000) -+ dual_node = 1; - - /* Entries are always added in pairs, the even indices are the 'source' - * side closest to the BSP, the odd indices are the 'destination' side - */ -- - while (currentNode <= pDat->NodesDiscovered) - { - u32 temp; -@@ -423,11 +459,24 @@ static void htDiscoveryFloodFill(sMainData *pDat) - /* Enable routing tables on currentNode*/ - pDat->nb->enableRoutingTables(currentNode, pDat->nb); - -- for (currentLink = 0; currentLink < pDat->nb->maxLinks; currentLink++) -+ for (currentLinkID = 0; currentLinkID < pDat->nb->maxLinks; currentLinkID++) - { - BOOL linkfound; - u8 token; - -+ if (currentLinkID < 8) { -+ if (dual_node) { -+ if (fam15h) -+ currentLink = currentLinkScanOrder_G34_Fam15[currentLinkID]; -+ else -+ currentLink = currentLinkScanOrder_G34_Fam10[currentLinkID]; -+ } else { -+ currentLink = currentLinkScanOrder_Default[currentLinkID]; -+ } -+ } else { -+ currentLink = currentLinkID; -+ } -+ - if (pDat->HtBlock->AMD_CB_IgnoreLink && pDat->HtBlock->AMD_CB_IgnoreLink(currentNode, currentLink)) - continue; - -diff --git a/src/northbridge/amd/amdht/h3ncmn.c b/src/northbridge/amd/amdht/h3ncmn.c -index 8f9177f..1026d0e 100644 ---- a/src/northbridge/amd/amdht/h3ncmn.c -+++ b/src/northbridge/amd/amdht/h3ncmn.c -@@ -51,8 +51,9 @@ - #define REG_NODE_ID_0X60 0x60 - #define REG_UNIT_ID_0X64 0x64 - #define REG_LINK_TRANS_CONTROL_0X68 0x68 --#define REG_LINK_INIT_CONTROL_0X6C 0x6C -+#define REG_LINK_INIT_CONTROL_0X6C 0x6c - #define REG_HT_CAP_BASE_0X80 0x80 -+#define REG_NORTHBRIDGE_CFG_3X8C 0x8c - #define REG_HT_LINK_RETRY0_0X130 0x130 - #define REG_HT_TRAFFIC_DIST_0X164 0x164 - #define REG_HT_LINK_EXT_CONTROL0_0X170 0x170 -@@ -91,6 +92,21 @@ - *** FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS *** - ***************************************************************************/ - -+static inline uint8_t is_fam15h(void) -+{ -+ uint8_t fam15h = 0; -+ uint32_t family; -+ -+ family = cpuid_eax(0x80000001); -+ family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); -+ -+ if (family >= 0x6f) -+ /* Family 15h or later */ -+ fam15h = 1; -+ -+ return fam15h; -+} -+ - /***************************************************************************//** - * - * SBDFO -@@ -219,8 +235,18 @@ static void writeRoutingTable(u8 node, u8 target, u8 link, cNorthBridge *nb) - - static void writeNodeID(u8 node, u8 nodeID, cNorthBridge *nb) - { -- u32 temp = nodeID; -+ u32 temp; - ASSERT((node < nb->maxNodes) && (nodeID < nb->maxNodes)); -+ if (is_fam15h()) { -+ temp = 1; -+ AmdPCIWriteBits(MAKE_SBDFO(makePCISegmentFromNode(node), -+ makePCIBusFromNode(node), -+ makePCIDeviceFromNode(node), -+ CPU_NB_FUNC_03, -+ REG_NORTHBRIDGE_CFG_3X8C), -+ 22, 22, &temp); -+ } -+ temp = nodeID; - AmdPCIWriteBits(MAKE_SBDFO(makePCISegmentFromNode(node), - makePCIBusFromNode(node), - makePCIDeviceFromNode(node), -diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c -index c0ccc69..a4aaa12 100644 ---- a/src/northbridge/amd/amdht/ht_wrapper.c -+++ b/src/northbridge/amd/amdht/ht_wrapper.c -@@ -92,16 +92,132 @@ static u32 get_nodes(void) - */ - static void AMD_CB_EventNotify (u8 evtClass, u16 event, const u8 *pEventData0) - { -- u8 i; -+ uint8_t i; -+ uint8_t log_level; -+ uint8_t dump_event_detail; - -- printk(BIOS_DEBUG, "AMD_CB_EventNotify()\n"); -- printk(BIOS_DEBUG, " event class: %02x\n event: %04x\n data: ", evtClass, event); -+ printk(BIOS_DEBUG, "AMD_CB_EventNotify(): "); - -- for (i = 0; i < *pEventData0; i++) { -- printk(BIOS_DEBUG, " %02x ", *(pEventData0 + i)); -+ /* Decode event */ -+ dump_event_detail = 1; -+ switch (evtClass) { -+ case HT_EVENT_CLASS_CRITICAL: -+ log_level = BIOS_DEBUG; -+ printk(log_level, "CRITICAL"); -+ break; -+ case HT_EVENT_CLASS_ERROR: -+ log_level = BIOS_DEBUG; -+ printk(log_level, "ERROR"); -+ break; -+ case HT_EVENT_CLASS_HW_FAULT: -+ log_level = BIOS_DEBUG; -+ printk(log_level, "HARDWARE FAULT"); -+ break; -+ case HT_EVENT_CLASS_WARNING: -+ log_level = BIOS_DEBUG; -+ printk(log_level, "WARNING"); -+ break; -+ case HT_EVENT_CLASS_INFO: -+ log_level = BIOS_DEBUG; -+ printk(log_level, "INFO"); -+ break; -+ default: -+ log_level = BIOS_DEBUG; -+ printk(log_level, "UNKNOWN"); -+ break; - } -- printk(BIOS_DEBUG, "\n"); -+ printk(log_level, ": "); - -+ switch(event) { -+ case HT_EVENT_COH_EVENTS: -+ printk(log_level, "HT_EVENT_COH_EVENTS"); -+ break; -+ case HT_EVENT_COH_NO_TOPOLOGY: -+ printk(log_level, "HT_EVENT_COH_NO_TOPOLOGY"); -+ break; -+ case HT_EVENT_COH_LINK_EXCEED: -+ printk(log_level, "HT_EVENT_COH_LINK_EXCEED"); -+ break; -+ case HT_EVENT_COH_FAMILY_FEUD: -+ printk(log_level, "HT_EVENT_COH_FAMILY_FEUD"); -+ break; -+ case HT_EVENT_COH_NODE_DISCOVERED: -+ { -+ printk(log_level, "HT_EVENT_COH_NODE_DISCOVERED"); -+ sHtEventCohNodeDiscovered *evt = (sHtEventCohNodeDiscovered*)pEventData0; -+ printk(log_level, ": node %d link %d new node: %d", -+ evt->node, evt->link, evt->newNode); -+ dump_event_detail = 0; -+ break; -+ } -+ case HT_EVENT_COH_MPCAP_MISMATCH: -+ printk(log_level, "HT_EVENT_COH_MPCAP_MISMATCH"); -+ break; -+ case HT_EVENT_NCOH_EVENTS: -+ printk(log_level, "HT_EVENT_NCOH_EVENTS"); -+ break; -+ case HT_EVENT_NCOH_BUID_EXCEED: -+ printk(log_level, "HT_EVENT_NCOH_BUID_EXCEED"); -+ break; -+ case HT_EVENT_NCOH_LINK_EXCEED: -+ printk(log_level, "HT_EVENT_NCOH_LINK_EXCEED"); -+ break; -+ case HT_EVENT_NCOH_BUS_MAX_EXCEED: -+ printk(log_level, "HT_EVENT_NCOH_BUS_MAX_EXCEED"); -+ break; -+ case HT_EVENT_NCOH_CFG_MAP_EXCEED: -+ printk(log_level, "HT_EVENT_NCOH_CFG_MAP_EXCEED"); -+ break; -+ case HT_EVENT_NCOH_DEVICE_FAILED: -+ { -+ printk(log_level, "HT_EVENT_NCOH_DEVICE_FAILED"); -+ sHtEventNcohDeviceFailed *evt = (sHtEventNcohDeviceFailed*)pEventData0; -+ printk(log_level, ": node %d link %d depth: %d attemptedBUID: %d", -+ evt->node, evt->link, evt->depth, evt->attemptedBUID); -+ dump_event_detail = 0; -+ break; -+ } -+ case HT_EVENT_NCOH_AUTO_DEPTH: -+ { -+ printk(log_level, "HT_EVENT_NCOH_AUTO_DEPTH"); -+ sHtEventNcohAutoDepth *evt = (sHtEventNcohAutoDepth*)pEventData0; -+ printk(log_level, ": node %d link %d depth: %d", -+ evt->node, evt->link, evt->depth); -+ dump_event_detail = 0; -+ break; -+ } -+ case HT_EVENT_OPT_EVENTS: -+ printk(log_level, "HT_EVENT_OPT_EVENTS"); -+ break; -+ case HT_EVENT_OPT_REQUIRED_CAP_RETRY: -+ printk(log_level, "HT_EVENT_OPT_REQUIRED_CAP_RETRY"); -+ break; -+ case HT_EVENT_OPT_REQUIRED_CAP_GEN3: -+ printk(log_level, "HT_EVENT_OPT_REQUIRED_CAP_GEN3"); -+ break; -+ case HT_EVENT_HW_EVENTS: -+ printk(log_level, "HT_EVENT_HW_EVENTS"); -+ break; -+ case HT_EVENT_HW_SYNCHFLOOD: -+ printk(log_level, "HT_EVENT_HW_SYNCHFLOOD"); -+ break; -+ case HT_EVENT_HW_HTCRC: -+ printk(log_level, "HT_EVENT_HW_HTCRC"); -+ break; -+ default: -+ printk(log_level, "HT_EVENT_UNKNOWN"); -+ break; -+ } -+ printk(log_level, "\n"); -+ -+ if (dump_event_detail) { -+ printk(BIOS_DEBUG, " event class: %02x\n event: %04x\n data: ", evtClass, event); -+ -+ for (i = 0; i < *pEventData0; i++) { -+ printk(BIOS_DEBUG, " %02x ", *(pEventData0 + i)); -+ } -+ printk(BIOS_DEBUG, "\n"); -+ } - } - - /** -@@ -210,9 +326,10 @@ void amd_ht_fixup(struct sys_info *sysinfo) { - for (node = 0; node < node_count; node++) { - f3xe8 = pci_read_config32(NODE_PCI(node, 3), 0xe8); - uint8_t internal_node_number = ((f3xe8 & 0xc0000000) >> 30); -- printk(BIOS_DEBUG, "amd_ht_fixup(): node %d (internal node ID %d): disabling defective HT link\n", node, internal_node_number); -+ printk(BIOS_DEBUG, "amd_ht_fixup(): node %d (internal node ID %d): disabling defective HT link", node, internal_node_number); - if (internal_node_number == 0) { - uint8_t package_link_3_connected = pci_read_config32(NODE_PCI(node, 0), (fam15h)?0x98:0xd8) & 0x1; -+ printk(BIOS_DEBUG, " (L3 connected: %d)\n", package_link_3_connected); - if (package_link_3_connected) { - /* Set WidthIn and WidthOut to 0 */ - dword = pci_read_config32(NODE_PCI(node, 0), (fam15h)?0x84:0xc4); -@@ -234,15 +351,21 @@ void amd_ht_fixup(struct sys_info *sysinfo) { - } - } else if (internal_node_number == 1) { - uint8_t package_link_3_connected = pci_read_config32(NODE_PCI(node, 0), (fam15h)?0xf8:0xb8) & 0x1; -+ printk(BIOS_DEBUG, " (L3 connected: %d)\n", package_link_3_connected); - if (package_link_3_connected) { - /* Set WidthIn and WidthOut to 0 */ - dword = pci_read_config32(NODE_PCI(node, 0), (fam15h)?0xe4:0xa4); - dword &= ~0x77000000; - pci_write_config32(NODE_PCI(node, 0), (fam15h)?0xe4:0xa4, dword); - /* Set Ganged to 1 */ -- dword = pci_read_config32(NODE_PCI(node, 0), (fam15h)?0x18c:0x174); -+ /* WARNING -+ * The Family 15h BKDG states that 0x18c should be set, -+ * however this is in error. 0x17c is the correct control -+ * register (sublink 0) for these processors... -+ */ -+ dword = pci_read_config32(NODE_PCI(node, 0), (fam15h)?0x17c:0x174); - dword |= 0x00000001; -- pci_write_config32(NODE_PCI(node, 0), (fam15h)?0x18c:0x174, dword); -+ pci_write_config32(NODE_PCI(node, 0), (fam15h)?0x17c:0x174, dword); - } else { - /* Set ConnDly to 1 */ - dword = pci_read_config32(NODE_PCI(node, 0), 0x16c); -diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c -index 5a57dc0..0b61106 100644 ---- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c -+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c -@@ -5441,6 +5441,7 @@ static void mct_InitialMCT_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc - cpu_divisor = (0x1 << cpu_did); - pMCTstat->TSCFreq = (100 * (cpu_fid + 0x10)) / cpu_divisor; - -+ printk(BIOS_DEBUG, "mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15\n"); - mct_ForceNBPState0_En_Fam15(pMCTstat, pDCTstat); - } else { - /* K10 BKDG v3.62 section 2.8.9.2 */ --- -1.9.1 - diff --git a/resources/libreboot/patch/kgpe-d16/0087-northbridge-amd-amdmct-Reduce-maximum-number-of-DDR3.patch b/resources/libreboot/patch/kgpe-d16/0087-northbridge-amd-amdmct-Reduce-maximum-number-of-DDR3.patch new file mode 100644 index 0000000..08333f6 --- /dev/null +++ b/resources/libreboot/patch/kgpe-d16/0087-northbridge-amd-amdmct-Reduce-maximum-number-of-DDR3.patch @@ -0,0 +1,41 @@ +From e262fc3ee190bafb58adfab926cc24ff9cbd239c Mon Sep 17 00:00:00 2001 +From: Timothy Pearson +Date: Tue, 20 Oct 2015 21:32:09 -0500 +Subject: [PATCH 087/143] northbridge/amd/amdmct: Reduce maximum number of + DDR3 DIMMs + +CAR space on certain platforms is nearly full. This prevents the +addition of necessary RAM initialization features such as x4 DIMM +support. As the DIMM SPD cache uses a sizeable amount of CAR RAM, +reducing it would free up a significant amount of CAR RAM. + +DDR3-based AMD platforms only support up to 3 physical DIMMs on +each channel (6 per node). Reduce the maximum number of DIMMs +on a node from 8 to 6 accordingly. + +Change-Id: I38def86da76fc622785318c825670209b2ac9017 +Signed-off-by: Timothy Pearson +--- + src/northbridge/amd/amdmct/wrappers/mcti.h | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +diff --git a/src/northbridge/amd/amdmct/wrappers/mcti.h b/src/northbridge/amd/amdmct/wrappers/mcti.h +index 2aba377..ef6e3dc 100644 +--- a/src/northbridge/amd/amdmct/wrappers/mcti.h ++++ b/src/northbridge/amd/amdmct/wrappers/mcti.h +@@ -51,7 +51,11 @@ UPDATE AS NEEDED + #endif + + #ifndef MAX_DIMMS_SUPPORTED +-#define MAX_DIMMS_SUPPORTED 8 ++#if IS_ENABLED(CONFIG_DIMM_DDR3) ++ #define MAX_DIMMS_SUPPORTED 6 ++#else ++ #define MAX_DIMMS_SUPPORTED 8 ++#endif + #endif + + #ifndef MAX_CS_SUPPORTED +-- +1.7.9.5 + diff --git a/resources/libreboot/patch/kgpe-d16/0086-northbridge-amd-amdmct-mct_ddr3-Add-registered-and-x.patch b/resources/libreboot/patch/kgpe-d16/0088-northbridge-amd-amdmct-mct_ddr3-Add-registered-and-x.patch index 37cda08..3e708f5 100644 --- a/resources/libreboot/patch/kgpe-d16/0086-northbridge-amd-amdmct-mct_ddr3-Add-registered-and-x.patch +++ b/resources/libreboot/patch/kgpe-d16/0088-northbridge-amd-amdmct-mct_ddr3-Add-registered-and-x.patch @@ -1,26 +1,26 @@ -From 95e15fd07cd76057737c0b52a4ece6f73501ea1e Mon Sep 17 00:00:00 2001 +From f30d6c75652c95152eb0dbe6bf9da2198a780a84 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Tue, 28 Jul 2015 15:16:46 -0500 -Subject: [PATCH 086/139] northbridge/amd/amdmct/mct_ddr3: Add registered and +Subject: [PATCH 088/143] northbridge/amd/amdmct/mct_ddr3: Add registered and x4 DIMM support to Fam15h Change-Id: I9ee0bb7346aa35f564fe535cdd337ec7f6148f2b Signed-off-by: Timothy Pearson --- - src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 186 +++++++----- - src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 2 +- - src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 4 + - src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c | 17 +- - src/northbridge/amd/amdmct/mct_ddr3/mctrci.c | 191 ++++++++---- - src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c | 42 ++- - src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 253 +++++++++------- - src/northbridge/amd/amdmct/mct_ddr3/mctwl.c | 16 +- - src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c | 400 +++++++++++++++---------- - src/northbridge/amd/amdmct/mct_ddr3/mwlc_d.h | 13 +- + src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 186 ++++++----- + src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 2 +- + src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 4 + + src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c | 17 +- + src/northbridge/amd/amdmct/mct_ddr3/mctrci.c | 191 +++++++---- + src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c | 42 ++- + src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 253 ++++++++------- + src/northbridge/amd/amdmct/mct_ddr3/mctwl.c | 16 +- + src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c | 400 +++++++++++++++--------- + src/northbridge/amd/amdmct/mct_ddr3/mwlc_d.h | 13 +- 10 files changed, 698 insertions(+), 426 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c -index 8102f2a..5a57dc0 100644 +index b29ff3c..1c9c568 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -166,7 +166,7 @@ static void mct_EnDllShutdownSR(struct MCTStatStruc *pMCTstat, @@ -52,7 +52,7 @@ index 8102f2a..5a57dc0 100644 if (is_fam15h()) { uint8_t Node; -@@ -3357,7 +3361,7 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat, +@@ -3359,7 +3363,7 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat, } static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat, @@ -61,7 +61,7 @@ index 8102f2a..5a57dc0 100644 { /* Initialize DCT Timing registers as per DIMM SPD. * For primary timing (T, CL) use best case T value. -@@ -3461,7 +3465,7 @@ static void GetPresetmaxF_D(struct MCTStatStruc *pMCTstat, +@@ -3463,7 +3467,7 @@ static void GetPresetmaxF_D(struct MCTStatStruc *pMCTstat, } static void SPDGetTCL_D(struct MCTStatStruc *pMCTstat, @@ -70,7 +70,7 @@ index 8102f2a..5a57dc0 100644 { /* Find the best T and CL primary timing parameter pair, per Mfg., * for the given set of DIMMs, and store into DCTStatStruc -@@ -3740,10 +3744,15 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, +@@ -3742,10 +3746,15 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, dword++; } @@ -90,7 +90,7 @@ index 8102f2a..5a57dc0 100644 if (mctGet_NVbits(NV_ECC_CAP)) if (Status & (1 << SB_ECCDIMMs)) -@@ -3761,10 +3770,11 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, +@@ -3763,10 +3772,11 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, DramConfigHi |= dword - offset; /* get MemClk encoding */ DramConfigHi |= 1 << MemClkFreqVal; @@ -106,7 +106,7 @@ index 8102f2a..5a57dc0 100644 if (pDCTstat->LogicalCPUID & AMD_FAM15_ALL) { DramConfigLo |= 1 << 25; /* PendRefPaybackS3En = 1 */ -@@ -3776,14 +3786,16 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, +@@ -3778,14 +3788,16 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, DramConfigHi |= 1 << 16; } @@ -129,7 +129,7 @@ index 8102f2a..5a57dc0 100644 byte = mctGet_NVbits(NV_4RANKType); if (byte == 2) DramConfigHi |= 1 << 17; /* S4 (4-Rank SO-DIMMs) */ -@@ -4588,8 +4600,9 @@ static u8 mct_setMode(struct MCTStatStruc *pMCTstat, +@@ -4590,8 +4602,9 @@ static u8 mct_setMode(struct MCTStatStruc *pMCTstat, Set_NB32(pDCTstat->dev_dct, reg, val); } if (byte) /* NV_Unganged */ @@ -140,7 +140,7 @@ index 8102f2a..5a57dc0 100644 return pDCTstat->ErrCode; } -@@ -4650,6 +4663,8 @@ void Set_NB32_index_wait(u32 dev, u32 index_reg, u32 index, u32 data) +@@ -4652,6 +4665,8 @@ void Set_NB32_index_wait(u32 dev, u32 index_reg, u32 index, u32 data) static u8 mct_BeforePlatformSpec(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct) { @@ -149,7 +149,7 @@ index 8102f2a..5a57dc0 100644 /* mct_checkForCxDxSupport_D */ if (pDCTstat->LogicalCPUID & AMD_DR_GT_Bx) { /* Family 10h Errata 322: Address and Command Fine Delay Values May Be Incorrect */ -@@ -4664,6 +4679,9 @@ static u8 mct_BeforePlatformSpec(struct MCTStatStruc *pMCTstat, +@@ -4666,6 +4681,9 @@ static u8 mct_BeforePlatformSpec(struct MCTStatStruc *pMCTstat, else Set_NB32_index_wait_DCT(pDCTstat->dev_dct, dct, 0x98, 0x0D02E001, 0x90); } @@ -159,7 +159,7 @@ index 8102f2a..5a57dc0 100644 return pDCTstat->ErrCode; } -@@ -4674,6 +4692,8 @@ static u8 mct_PlatformSpec(struct MCTStatStruc *pMCTstat, +@@ -4676,6 +4694,8 @@ static u8 mct_PlatformSpec(struct MCTStatStruc *pMCTstat, * and program them into DCT. */ @@ -168,7 +168,7 @@ index 8102f2a..5a57dc0 100644 u32 dev = pDCTstat->dev_dct; u32 index_reg; u8 i, i_start, i_end; -@@ -4694,6 +4714,8 @@ static u8 mct_PlatformSpec(struct MCTStatStruc *pMCTstat, +@@ -4696,6 +4716,8 @@ static u8 mct_PlatformSpec(struct MCTStatStruc *pMCTstat, printk(BIOS_SPEW, "Programmed DCT %d timing/termination pattern %08x %08x\n", dct, pDCTstat->CH_ADDR_TMG[i], pDCTstat->CH_ODC_CTL[i]); } @@ -177,7 +177,7 @@ index 8102f2a..5a57dc0 100644 return pDCTstat->ErrCode; } -@@ -4705,7 +4727,8 @@ static void mct_SyncDCTsReady(struct DCTStatStruc *pDCTstat) +@@ -4707,7 +4729,8 @@ static void mct_SyncDCTsReady(struct DCTStatStruc *pDCTstat) if (pDCTstat->NodePresent) { dev = pDCTstat->dev_dct; @@ -187,7 +187,7 @@ index 8102f2a..5a57dc0 100644 do { val = Get_NB32(dev, 0x110); } while (!(val & (1 << DramEnabled))); -@@ -5653,57 +5676,56 @@ static void InitDDRPhy(struct MCTStatStruc *pMCTstat, +@@ -5655,57 +5678,56 @@ static void InitDDRPhy(struct MCTStatStruc *pMCTstat, /* Fam15h BKDG v3.14 section 2.10.5.3 * The remainder of the Phy Initialization algorithm picks up in phyAssistedMemFnceTraining */ @@ -294,7 +294,7 @@ index 8102f2a..5a57dc0 100644 printk(BIOS_DEBUG, "%s: Done\n", __func__); } -@@ -5719,18 +5741,24 @@ static void InitPhyCompensation(struct MCTStatStruc *pMCTstat, +@@ -5721,18 +5743,24 @@ static void InitPhyCompensation(struct MCTStatStruc *pMCTstat, uint32_t dword; const u8 *p; @@ -322,7 +322,7 @@ index 8102f2a..5a57dc0 100644 /* Determine TxPreP/TxPreN for data lanes (Stage 1) */ dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x00000000); drive_strength = (dword >> 20) & 0x7; /* DqsDrvStren */ -@@ -5876,12 +5904,14 @@ static void InitPhyCompensation(struct MCTStatStruc *pMCTstat, +@@ -5878,12 +5906,14 @@ static void InitPhyCompensation(struct MCTStatStruc *pMCTstat, Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0a, dword); } @@ -338,7 +338,7 @@ index 8102f2a..5a57dc0 100644 if (!is_fam15h()) { u32 reg; u32 val; -@@ -5903,6 +5933,8 @@ static void mct_EarlyArbEn_D(struct MCTStatStruc *pMCTstat, +@@ -5905,6 +5935,8 @@ static void mct_EarlyArbEn_D(struct MCTStatStruc *pMCTstat, Set_NB32_DCT(dev, dct, reg, val); } @@ -347,7 +347,7 @@ index 8102f2a..5a57dc0 100644 } static u8 CheckNBCOFEarlyArbEn(struct MCTStatStruc *pMCTstat, -@@ -6546,6 +6578,8 @@ void mct_SetDramConfigHi_D(struct MCTStatStruc *pMCTstat, +@@ -6548,6 +6580,8 @@ void mct_SetDramConfigHi_D(struct MCTStatStruc *pMCTstat, uint32_t dword; @@ -356,7 +356,7 @@ index 8102f2a..5a57dc0 100644 if (is_fam15h()) { /* Initial setup for frequency change * 9C_x0000_0004 must be configured before MemClkFreqVal is set -@@ -6578,6 +6612,8 @@ void mct_SetDramConfigHi_D(struct MCTStatStruc *pMCTstat, +@@ -6580,6 +6614,8 @@ void mct_SetDramConfigHi_D(struct MCTStatStruc *pMCTstat, mct_Wait(100); } @@ -365,7 +365,7 @@ index 8102f2a..5a57dc0 100644 /* Program the DRAM Configuration High register */ Set_NB32_DCT(dev, dct, 0x94, DramConfigHi); -@@ -6593,6 +6629,8 @@ void mct_SetDramConfigHi_D(struct MCTStatStruc *pMCTstat, +@@ -6595,6 +6631,8 @@ void mct_SetDramConfigHi_D(struct MCTStatStruc *pMCTstat, dword |= 0x0000000f; Set_NB32_index_wait_DCT(pDCTstat->dev_dct, dct, index_reg, 0x0d0fe006, dword); } @@ -1883,5 +1883,5 @@ index 12e7c4a..3337c14 100644 /* per byte Lane Per Logical DIMM*/ u8 WLFineDelayFirstPass[MAX_BYTE_LANES*MAX_LDIMMS]; /* First-Pass Write Levelization Fine Delay */ -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0089-cpu-amd-family_10h-family_15h-Fix-Family-15h-multipl.patch b/resources/libreboot/patch/kgpe-d16/0089-cpu-amd-family_10h-family_15h-Fix-Family-15h-multipl.patch new file mode 100644 index 0000000..4cda10f --- /dev/null +++ b/resources/libreboot/patch/kgpe-d16/0089-cpu-amd-family_10h-family_15h-Fix-Family-15h-multipl.patch @@ -0,0 +1,1244 @@ +From 14d498ea0d069418099c6c4a374d0de62e37dca0 Mon Sep 17 00:00:00 2001 +From: Timothy Pearson +Date: Thu, 30 Jul 2015 14:07:15 -0500 +Subject: [PATCH 089/143] cpu/amd/family_10h-family_15h: Fix Family 15h + multiple package support + +TEST: Booted ASUS KGPE-D16 with two Opteron 6328 processors +and several different RDIMM configurations. + +Change-Id: I171197c90f72d3496a385465937b7666cbf7e308 +Signed-off-by: Timothy Pearson +--- + src/cpu/amd/car/cache_as_ram.inc | 17 ++- + src/cpu/amd/family_10h-family_15h/defaults.h | 101 ++++++++++++-- + src/cpu/amd/family_10h-family_15h/fidvid.c | 81 +++++------ + src/cpu/amd/family_10h-family_15h/init_cpus.c | 66 ++++++++- + src/cpu/amd/quadcore/quadcore.c | 19 +-- + src/cpu/amd/quadcore/quadcore_id.c | 1 - + src/mainboard/advansus/a785e-i/romstage.c | 2 +- + src/mainboard/amd/bimini_fam10/romstage.c | 2 +- + src/mainboard/amd/mahogany_fam10/romstage.c | 2 +- + .../amd/serengeti_cheetah_fam10/romstage.c | 2 +- + src/mainboard/amd/tilapia_fam10/romstage.c | 2 +- + src/mainboard/asus/kfsn4-dre/romstage.c | 2 +- + src/mainboard/asus/kgpe-d16/romstage.c | 46 +++++-- + src/mainboard/asus/m4a78-em/romstage.c | 2 +- + src/mainboard/asus/m4a785-m/romstage.c | 2 +- + src/mainboard/asus/m5a88-v/romstage.c | 2 +- + src/mainboard/avalue/eax-785e/romstage.c | 2 +- + src/mainboard/gigabyte/ma785gm/romstage.c | 2 +- + src/mainboard/gigabyte/ma785gmt/romstage.c | 2 +- + src/mainboard/gigabyte/ma78gm/romstage.c | 2 +- + src/mainboard/hp/dl165_g6_fam10/romstage.c | 2 +- + src/mainboard/iei/kino-780am2-fam10/romstage.c | 2 +- + src/mainboard/jetway/pa78vm5/romstage.c | 2 +- + src/mainboard/msi/ms9652_fam10/romstage.c | 2 +- + src/mainboard/supermicro/h8dmr_fam10/romstage.c | 2 +- + src/mainboard/supermicro/h8qme_fam10/romstage.c | 2 +- + src/mainboard/supermicro/h8scm_fam10/romstage.c | 2 +- + src/mainboard/tyan/s2912_fam10/romstage.c | 2 +- + src/northbridge/amd/amdht/h3finit.c | 57 +++++++- + src/northbridge/amd/amdht/h3ncmn.c | 30 ++++- + src/northbridge/amd/amdht/ht_wrapper.c | 141 ++++++++++++++++++-- + src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 1 + + 32 files changed, 479 insertions(+), 123 deletions(-) + +diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc +index 5db9224..6bfb0e6 100644 +--- a/src/cpu/amd/car/cache_as_ram.inc ++++ b/src/cpu/amd/car/cache_as_ram.inc +@@ -525,8 +525,23 @@ CAR_FAM10_ap: + /* Fam10h NB config bit 54 was not set */ + rolb %cl, %bl + roll_cfg: ++ jmp_if_not_fam15h(ap_apicid_ready) ++ cmp $0x5, %ecx ++ jne ap_apicid_ready + +- /* Calculate stack pointer. */ ++ /* This is a multi-node CPU ++ * Adjust the maximum APIC ID to a more reasonable value ++ * given that no 32-core Family 15h processors exist ++ */ ++ movl %ebx, %ecx ++ and $0x0f, %ecx /* Get lower 4 bits of CPU number */ ++ and $0x60, %ebx /* Get node ID */ ++ shrl $0x1, %ebx /* Shift node ID part of APIC ID down by 1 */ ++ or %ecx, %ebx /* Recombine node ID and CPU number */ ++ ++ap_apicid_ready: ++ ++ /* Calculate stack pointer using adjusted APIC ID stored in ebx */ + movl $CacheSizeAPStack, %eax + mull %ebx + movl $(CacheBase + (CacheSize - (CacheSizeBSPStack + CacheSizeBSPSlush))), %esp +diff --git a/src/cpu/amd/family_10h-family_15h/defaults.h b/src/cpu/amd/family_10h-family_15h/defaults.h +index 24f87ba..513d169 100644 +--- a/src/cpu/amd/family_10h-family_15h/defaults.h ++++ b/src/cpu/amd/family_10h-family_15h/defaults.h +@@ -244,18 +244,50 @@ static const struct { + { 0, 0x68, (AMD_DR_B0 | AMD_DR_B1), + AMD_PTYPE_SVR, 0x00200000, 0x00600000 }, /* [22:21] DsNpReqLmt0 = 01b */ + +- { 0, 0x84, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, ++ { 0, 0x84, AMD_FAM10_ALL, AMD_PTYPE_ALL, + 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ + +- { 0, 0xA4, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, ++ { 0, 0xA4, AMD_FAM10_ALL, AMD_PTYPE_ALL, + 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ + +- { 0, 0xC4, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, ++ { 0, 0xC4, AMD_FAM10_ALL, AMD_PTYPE_ALL, + 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ + +- { 0, 0xE4, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, ++ { 0, 0xE4, AMD_FAM10_ALL, AMD_PTYPE_ALL, + 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ + ++ /* FIXME ++ * Non-C32 packages only ++ */ ++ { 0, 0x84, AMD_FAM15_ALL, AMD_PTYPE_ALL, ++ 0x00000000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ ++ ++ { 0, 0xA4, AMD_FAM15_ALL, AMD_PTYPE_ALL, ++ 0x00000000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ ++ ++ { 0, 0xC4, AMD_FAM15_ALL, AMD_PTYPE_ALL, ++ 0x00000000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ ++ ++ { 0, 0xE4, AMD_FAM15_ALL, AMD_PTYPE_ALL, ++ 0x00000000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ ++ ++ /* FIXME ++ * C32 package only ++ */ ++#if 0 ++ { 0, 0x84, AMD_FAM15_ALL, AMD_PTYPE_ALL, ++ 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ ++ ++ { 0, 0xA4, AMD_FAM15_ALL, AMD_PTYPE_ALL, ++ 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ ++ ++ { 0, 0xC4, AMD_FAM15_ALL, AMD_PTYPE_ALL, ++ 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ ++ ++ { 0, 0xE4, AMD_FAM15_ALL, AMD_PTYPE_ALL, ++ 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ ++#endif ++ + /* Link Global Retry Control Register */ + { 0, 0x150, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, + 0x00073900, 0x00073F00 }, +@@ -614,38 +646,79 @@ static const struct { + { 0x530A, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + 0x00004400, 0x00006400 }, /* HT_PHY_DLL_REG */ + +- { 0xCF, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, ++ { 0xCF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, ++ 0x00000000, 0x000000FF }, /* Provide clear setting for logical ++ completeness */ ++ ++ { 0xDF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, ++ 0x00000000, 0x000000FF }, /* Provide clear setting for logical ++ completeness */ ++ ++ { 0xCF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, ++ 0x0000006D, 0x000000FF }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */ ++ ++ { 0xDF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, ++ 0x0000006D, 0x000000FF }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */ ++ ++ /* Link Phy Receiver Loop Filter Registers */ ++ { 0xD1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, ++ 0x08040000, 0x3FFFC000 }, /* [29:22] LfcMax = 20h, ++ [21:14] LfcMin = 10h */ ++ ++ { 0xC1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, ++ 0x08040000, 0x3FFFC000 }, /* [29:22] LfcMax = 20h, ++ [21:14] LfcMin = 10h */ ++ ++ { 0xD1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, ++ 0x04020000, 0x3FFFC000 }, /* [29:22] LfcMax = 10h, ++ [21:14] LfcMin = 08h */ ++ ++ { 0xC1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, ++ 0x04020000, 0x3FFFC000 }, /* [29:22] LfcMax = 10h, ++ [21:14] LfcMin = 08h */ ++ ++ { 0xC0, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, ++ 0x40040000, 0xe01F0000 }, /* [31:29] RttCtl = 02h, ++ [20:16] RttIndex = 04h */ ++ ++/* FIXME ++ * Causes lockups for some reason when more than one package is installed ++ * Debug and reactivate! ++ */ ++// #if 0 ++ { 0xCF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, + 0x00000000, 0x000000FF }, /* Provide clear setting for logical + completeness */ + +- { 0xDF, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, ++ { 0xDF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, + 0x00000000, 0x000000FF }, /* Provide clear setting for logical + completeness */ + +- { 0xCF, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, ++ { 0xCF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, + 0x0000006D, 0x000000FF }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */ + +- { 0xDF, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, ++ { 0xDF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, + 0x0000006D, 0x000000FF }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */ + + /* Link Phy Receiver Loop Filter Registers */ +- { 0xD1, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, ++ { 0xD1, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, + 0x08040000, 0x3FFFC000 }, /* [29:22] LfcMax = 20h, + [21:14] LfcMin = 10h */ + +- { 0xC1, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, ++ { 0xC1, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, + 0x08040000, 0x3FFFC000 }, /* [29:22] LfcMax = 20h, + [21:14] LfcMin = 10h */ + +- { 0xD1, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, ++ { 0xD1, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, + 0x04020000, 0x3FFFC000 }, /* [29:22] LfcMax = 10h, + [21:14] LfcMin = 08h */ + +- { 0xC1, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, ++ { 0xC1, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, + 0x04020000, 0x3FFFC000 }, /* [29:22] LfcMax = 10h, + [21:14] LfcMin = 08h */ + +- { 0xC0, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, ++ { 0xC0, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + 0x40040000, 0xe01F0000 }, /* [31:29] RttCtl = 02h, +- [20:16] RttIndex = 04h */ ++ [20:16] RttIndex = 04h */ ++// #endif + }; +diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c +index 0e7d299..d99c37f 100644 +--- a/src/cpu/amd/family_10h-family_15h/fidvid.c ++++ b/src/cpu/amd/family_10h-family_15h/fidvid.c +@@ -633,44 +633,45 @@ static void prep_fid_change(void) + } + + static void waitCurrentPstate(u32 target_pstate) { +- msr_t initial_msr = rdmsr(TSC_MSR); +- msr_t pstate_msr = rdmsr(CUR_PSTATE_MSR); +- msr_t tsc_msr; +- u8 timedout ; +- +- /* paranoia ? I fear when we run fixPsNbVidBeforeWR we can enter a +- * P1 that is a copy of P0, therefore has the same NB DID but the +- * TSC will count twice per tick, so we have to wait for twice the +- * count to achieve the desired timeout. But I'm likely to +- * misunderstand this... +- */ +- u32 corrected_timeout = ( (pstate_msr.lo==1) +- && (!(rdmsr(0xC0010065).lo & NB_DID_M_ON)) ) ? +- WAIT_PSTATE_TIMEOUT*2 : WAIT_PSTATE_TIMEOUT ; +- msr_t timeout; +- +- timeout.lo = initial_msr.lo + corrected_timeout ; +- timeout.hi = initial_msr.hi; +- if ( (((u32)0xffffffff) - initial_msr.lo) < corrected_timeout ) { +- timeout.hi++; +- } +- +- // assuming TSC ticks at 1.25 ns per tick (800 MHz) +- do { +- pstate_msr = rdmsr(CUR_PSTATE_MSR); +- tsc_msr = rdmsr(TSC_MSR); +- timedout = (tsc_msr.hi > timeout.hi) +- || ((tsc_msr.hi == timeout.hi) && (tsc_msr.lo > timeout.lo )); +- } while ( (pstate_msr.lo != target_pstate) && (! timedout) ) ; +- +- if (pstate_msr.lo != target_pstate) { +- msr_t limit_msr = rdmsr(0xc0010061); +- printk(BIOS_ERR, "*** Time out waiting for P-state %01x. Current P-state %01x P-state current limit MSRC001_0061=%08x %08x\n", target_pstate, pstate_msr.lo, limit_msr.hi, limit_msr.lo); +- +- do { // should we just go on instead ? +- pstate_msr = rdmsr(CUR_PSTATE_MSR); +- } while ( pstate_msr.lo != target_pstate ) ; +- } ++ msr_t initial_msr = rdmsr(TSC_MSR); ++ msr_t pstate_msr = rdmsr(CUR_PSTATE_MSR); ++ msr_t tsc_msr; ++ u8 timedout ; ++ ++ /* paranoia ? I fear when we run fixPsNbVidBeforeWR we can enter a ++ * P1 that is a copy of P0, therefore has the same NB DID but the ++ * TSC will count twice per tick, so we have to wait for twice the ++ * count to achieve the desired timeout. But I'm likely to ++ * misunderstand this... ++ */ ++ u32 corrected_timeout = ((pstate_msr.lo==1) ++ && (!(rdmsr(0xC0010065).lo & NB_DID_M_ON)) ) ? ++ WAIT_PSTATE_TIMEOUT*2 : WAIT_PSTATE_TIMEOUT; ++ msr_t timeout; ++ ++ timeout.lo = initial_msr.lo + corrected_timeout ; ++ timeout.hi = initial_msr.hi; ++ if ( (((u32)0xffffffff) - initial_msr.lo) < corrected_timeout ) { ++ timeout.hi++; ++ } ++ ++ // assuming TSC ticks at 1.25 ns per tick (800 MHz) ++ do { ++ pstate_msr = rdmsr(CUR_PSTATE_MSR); ++ tsc_msr = rdmsr(TSC_MSR); ++ timedout = (tsc_msr.hi > timeout.hi) ++ || ((tsc_msr.hi == timeout.hi) && (tsc_msr.lo > timeout.lo )); ++ } while ( (pstate_msr.lo != target_pstate) && (! timedout) ) ; ++ ++ if (pstate_msr.lo != target_pstate) { ++ msr_t limit_msr = rdmsr(0xc0010061); ++ printk(BIOS_ERR, "*** APIC ID %02x: timed out waiting for P-state %01x. Current P-state %01x P-state current limit MSRC001_0061=%08x %08x\n", ++ cpuid_ebx(0x00000001) >> 24, target_pstate, pstate_msr.lo, limit_msr.hi, limit_msr.lo); ++ ++ do { // should we just go on instead ? ++ pstate_msr = rdmsr(CUR_PSTATE_MSR); ++ } while ( pstate_msr.lo != target_pstate ) ; ++ } + } + + static void set_pstate(u32 nonBoostedPState) { +@@ -1064,13 +1065,13 @@ static int init_fidvid_bsp(u32 bsp_apicid, u32 nodes) + APs and BSP */ + ap_apicidx.num = 0; + +- for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE_RANGE, store_ap_apicid, &ap_apicidx); ++ for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE_RANGE, -1, store_ap_apicid, &ap_apicidx); + + for (i = 0; i < ap_apicidx.num; i++) { + init_fidvid_bsp_stage1(ap_apicidx.apicid[i], &fv); + } + #else +- for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage1, &fv); ++ for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE0_ONLY, -1, init_fidvid_bsp_stage1, &fv); + #endif + + print_debug_fv("common_fid = ", fv.common_fid); +diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c +index d45671c..4e5098e 100644 +--- a/src/cpu/amd/family_10h-family_15h/init_cpus.c ++++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c +@@ -59,6 +59,8 @@ static void set_EnableCf8ExtCfg(void) + static void set_EnableCf8ExtCfg(void) { } + #endif + ++// #define DEBUG_HT_SETUP 1 ++// #define FAM10_AP_NODE_SEQUENTIAL_START 1 + + typedef void (*process_ap_t) (u32 apicid, void *gp); + +@@ -143,8 +145,8 @@ uint32_t get_boot_apic_id(uint8_t node, uint32_t core) { + //core range = 1 : core 0 only + //core range = 2 : cores other than core0 + +-static void for_each_ap(u32 bsp_apicid, u32 core_range, process_ap_t process_ap, +- void *gp) ++static void for_each_ap(uint32_t bsp_apicid, uint32_t core_range, int8_t node, ++ process_ap_t process_ap, void *gp) + { + // here assume the OS don't change our apicid + u32 ap_apicid; +@@ -165,6 +167,9 @@ static void for_each_ap(u32 bsp_apicid, u32 core_range, process_ap_t process_ap, + } + + for (i = 0; i < nodes; i++) { ++ if ((node >= 0) && (i != node)) ++ continue; ++ + cores_found = get_core_num_in_bsp(i); + + u32 jstart, jend; +@@ -280,7 +285,7 @@ void wait_all_other_cores_started(u32 bsp_apicid) + { + // all aps other than core0 + printk(BIOS_DEBUG, "started ap apicid: "); +- for_each_ap(bsp_apicid, 2, wait_ap_started, (void *)0); ++ for_each_ap(bsp_apicid, 2, -1, wait_ap_started, (void *)0); + printk(BIOS_DEBUG, "\n"); + } + +@@ -373,8 +378,10 @@ static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo) + /* NB_CFG MSR is shared between cores, so we need make sure + core0 is done at first --- use wait_all_core0_started */ + if (id.coreid == 0) { +- set_apicid_cpuid_lo(); /* only set it on core0 */ +- set_EnableCf8ExtCfg(); /* only set it on core0 */ ++ /* Set InitApicIdCpuIdLo / EnableCf8ExtCfg on core0 only */ ++ if (!is_fam15h()) ++ set_apicid_cpuid_lo(); ++ set_EnableCf8ExtCfg(); + #if CONFIG_ENABLE_APIC_EXT_ID + enable_apic_ext_id(id.nodeid); + #endif +@@ -427,6 +434,7 @@ static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo) + } + // Mark the core as started. + lapic_write(LAPIC_MSG_REG, (apicid << 24) | F10_APSTATE_STARTED); ++ printk(BIOS_DEBUG, "CPU APICID %02x start flag set\n", apicid); + + if (apicid != bsp_apicid) { + /* Setup each AP's cores MSRs. +@@ -588,6 +596,34 @@ static void setup_remote_node(u8 node) + } + #endif /* CONFIG_MAX_PHYSICAL_CPUS > 1 */ + ++//it is running on core0 of node0 ++static void start_other_cores(uint32_t bsp_apicid) ++{ ++ u32 nodes; ++ u32 nodeid; ++ ++ // disable multi_core ++ if (read_option(multi_core, 0) != 0) { ++ printk(BIOS_DEBUG, "Skip additional core init\n"); ++ return; ++ } ++ ++ nodes = get_nodes(); ++ ++ for (nodeid = 0; nodeid < nodes; nodeid++) { ++ u32 cores = get_core_num_in_bsp(nodeid); ++ printk(BIOS_DEBUG, "init node: %02x cores: %02x pass 1\n", nodeid, cores); ++ if (cores > 0) { ++ real_start_other_core(nodeid, cores); ++#ifdef FAM10_AP_NODE_SEQUENTIAL_START ++ printk(BIOS_DEBUG, "waiting for core start on node %d...\n", nodeid); ++ for_each_ap(bsp_apicid, 2, nodeid, wait_ap_started, (void *)0); ++ printk(BIOS_DEBUG, "...started\n"); ++#endif ++ } ++ } ++} ++ + static void AMD_Errata281(u8 node, uint64_t revision, u32 platform) + { + /* Workaround for Transaction Scheduling Conflict in +@@ -847,6 +883,10 @@ static void AMD_SetHtPhyRegister(u8 node, u8 link, u8 entry) + + phyBase = ((u32) link << 3) | 0x180; + ++ /* Determine if link is connected and abort if not */ ++ if (!(pci_read_config32(NODE_PCI(node, 0), 0x98 + (link * 0x20)) & 0x1)) ++ return; ++ + /* Get the portal control register's initial value + * and update it to access the desired phy register + */ +@@ -1009,10 +1049,11 @@ static void cpuSetAMDPCI(u8 node) + * Hypertransport initialization has taken place. Also note + * that it is run for the first core on each node + */ +- u8 i, j; ++ uint8_t i; ++ uint8_t j; + u32 platform; + u32 val; +- u8 offset; ++ uint8_t offset; + uint32_t dword; + uint64_t revision; + +@@ -1039,6 +1080,17 @@ static void cpuSetAMDPCI(u8 node) + } + } + ++#ifdef DEBUG_HT_SETUP ++ /* Dump link settings */ ++ for (i = 0; i < 4; i++) { ++ for (j = 0; j < 4; j++) { ++ printk(BIOS_DEBUG, "Node %d link %d: type register: %08x control register: %08x extended control sublink 0: %08x 1: %08x\n", i, j, ++ pci_read_config32(NODE_PCI(i, 0), 0x98 + (j * 0x20)), pci_read_config32(NODE_PCI(i, 0), 0x84 + (j * 0x20)), ++ pci_read_config32(NODE_PCI(i, 0), 0x170 + (j * 0x4)), pci_read_config32(NODE_PCI(i, 0), 0x180 + (j * 0x4))); ++ } ++ } ++#endif ++ + for (i = 0; i < ARRAY_SIZE(fam10_htphy_default); i++) { + if ((fam10_htphy_default[i].revision & revision) && + (fam10_htphy_default[i].platform & platform)) { +diff --git a/src/cpu/amd/quadcore/quadcore.c b/src/cpu/amd/quadcore/quadcore.c +index 8a9b5ed..9c31eac 100644 +--- a/src/cpu/amd/quadcore/quadcore.c ++++ b/src/cpu/amd/quadcore/quadcore.c +@@ -31,21 +31,6 @@ + uint32_t get_boot_apic_id(uint8_t node, uint32_t core); + uint32_t wait_cpu_state(uint32_t apicid, uint32_t state, uint32_t state2); + +-static inline uint8_t is_fam15h(void) +-{ +- uint8_t fam15h = 0; +- uint32_t family; +- +- family = cpuid_eax(0x80000001); +- family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); +- +- if (family >= 0x6f) +- /* Family 15h or later */ +- fam15h = 1; +- +- return fam15h; +-} +- + static u32 get_core_num_in_bsp(u32 nodeid) + { + u32 dword; +@@ -141,6 +126,7 @@ static void real_start_other_core(uint32_t nodeid, uint32_t cores) + } + } + ++#if (!IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX)) + //it is running on core0 of node0 + static void start_other_cores(void) + { +@@ -157,9 +143,10 @@ static void start_other_cores(void) + + for (nodeid = 0; nodeid < nodes; nodeid++) { + u32 cores = get_core_num_in_bsp(nodeid); +- printk(BIOS_DEBUG, "init node: %02x cores: %02x pass 1 \n", nodeid, cores); ++ printk(BIOS_DEBUG, "init node: %02x cores: %02x pass 1\n", nodeid, cores); + if (cores > 0) { + real_start_other_core(nodeid, cores); + } + } + } ++#endif +diff --git a/src/cpu/amd/quadcore/quadcore_id.c b/src/cpu/amd/quadcore/quadcore_id.c +index c0537b3..1f5cbd8 100644 +--- a/src/cpu/amd/quadcore/quadcore_id.c ++++ b/src/cpu/amd/quadcore/quadcore_id.c +@@ -108,7 +108,6 @@ struct node_core_id get_node_core_id(u32 nb_cfg_54) + id.nodeid = apicid & 0x7; + } + } +- + if (fam15h && dual_node) { + /* Coreboot expects each separate processor die to be on a different nodeid. + * Since the code above returns nodeid 0 even on internal node 1 some fixup is needed... +diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c +index ab717fd..591faab 100644 +--- a/src/mainboard/advansus/a785e-i/romstage.c ++++ b/src/mainboard/advansus/a785e-i/romstage.c +@@ -155,7 +155,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) + #if CONFIG_LOGICAL_CPUS + /* Core0 on each node is configured. Now setup any additional cores. */ + printk(BIOS_DEBUG, "start_other_cores()\n"); +- start_other_cores(); ++ start_other_cores(bsp_apicid); + post_code(0x37); + wait_all_other_cores_started(bsp_apicid); + #endif +diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c +index 5e2cf82..95384ac 100644 +--- a/src/mainboard/amd/bimini_fam10/romstage.c ++++ b/src/mainboard/amd/bimini_fam10/romstage.c +@@ -147,7 +147,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) + #if CONFIG_LOGICAL_CPUS + /* Core0 on each node is configured. Now setup any additional cores. */ + printk(BIOS_DEBUG, "start_other_cores()\n"); +- start_other_cores(); ++ start_other_cores(bsp_apicid); + post_code(0x37); + wait_all_other_cores_started(bsp_apicid); + #endif +diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c +index 025a8bb..aac6b4e 100644 +--- a/src/mainboard/amd/mahogany_fam10/romstage.c ++++ b/src/mainboard/amd/mahogany_fam10/romstage.c +@@ -149,7 +149,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) + #if CONFIG_LOGICAL_CPUS + /* Core0 on each node is configured. Now setup any additional cores. */ + printk(BIOS_DEBUG, "start_other_cores()\n"); +- start_other_cores(); ++ start_other_cores(bsp_apicid); + post_code(0x37); + wait_all_other_cores_started(bsp_apicid); + #endif +diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +index 5063439..6d36575 100644 +--- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c ++++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +@@ -255,7 +255,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) + #if CONFIG_LOGICAL_CPUS + /* Core0 on each node is configured. Now setup any additional cores. */ + printk(BIOS_DEBUG, "start_other_cores()\n"); +- start_other_cores(); ++ start_other_cores(bsp_apicid); + post_code(0x37); + wait_all_other_cores_started(bsp_apicid); + #endif +diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c +index e37bc08..c9a9928 100644 +--- a/src/mainboard/amd/tilapia_fam10/romstage.c ++++ b/src/mainboard/amd/tilapia_fam10/romstage.c +@@ -149,7 +149,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) + #if CONFIG_LOGICAL_CPUS + /* Core0 on each node is configured. Now setup any additional cores. */ + printk(BIOS_DEBUG, "start_other_cores()\n"); +- start_other_cores(); ++ start_other_cores(bsp_apicid); + post_code(0x37); + wait_all_other_cores_started(bsp_apicid); + #endif +diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c +index dd5c7dc..1307e57 100644 +--- a/src/mainboard/asus/kfsn4-dre/romstage.c ++++ b/src/mainboard/asus/kfsn4-dre/romstage.c +@@ -288,7 +288,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) + if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) { + /* Core0 on each node is configured. Now setup any additional cores. */ + printk(BIOS_DEBUG, "start_other_cores()\n"); +- start_other_cores(); ++ start_other_cores(bsp_apicid); + post_code(0x37); + wait_all_other_cores_started(bsp_apicid); + } +diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c +index 4b4e305..f80fb8c 100644 +--- a/src/mainboard/asus/kgpe-d16/romstage.c ++++ b/src/mainboard/asus/kgpe-d16/romstage.c +@@ -97,7 +97,18 @@ static void switch_spd_mux(uint8_t channel) + pci_write_config8(PCI_DEV(0, 0x14, 0), 0x54, byte); + } + +-static const uint8_t spd_addr[] = { ++static const uint8_t spd_addr_fam15[] = { ++ // Socket 0 Node 0 ("Node 0") ++ RC00, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0, ++ // Socket 0 Node 1 ("Node 1") ++ RC00, DIMM4, DIMM5, 0, 0, DIMM6, DIMM7, 0, 0, ++ // Socket 1 Node 0 ("Node 2") ++ RC01, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0, ++ // Socket 1 Node 1 ("Node 3") ++ RC01, DIMM4, DIMM5, 0, 0, DIMM6, DIMM7, 0, 0, ++}; ++ ++static const uint8_t spd_addr_fam10[] = { + // Socket 0 Node 0 ("Node 0") + RC00, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0, + // Socket 0 Node 1 ("Node 1") +@@ -117,10 +128,10 @@ static void activate_spd_rom(const struct mem_controller *ctrl) { + switch_spd_mux(0x2); + } else if (ctrl->node_id == 1) { + printk(BIOS_DEBUG, "enable_spd_node1()\n"); +- switch_spd_mux((sysinfo->nodes <= 2)?0x2:0x3); ++ switch_spd_mux((is_fam15h() || (sysinfo->nodes <= 2))?0x2:0x3); + } else if (ctrl->node_id == 2) { + printk(BIOS_DEBUG, "enable_spd_node2()\n"); +- switch_spd_mux((sysinfo->nodes <= 2)?0x3:0x2); ++ switch_spd_mux((is_fam15h() || (sysinfo->nodes <= 2))?0x3:0x2); + } else if (ctrl->node_id == 3) { + printk(BIOS_DEBUG, "enable_spd_node3()\n"); + switch_spd_mux(0x3); +@@ -306,18 +317,25 @@ void initialize_romstage_console_lock(void) + + void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) + { ++ uint32_t esp; ++ __asm__ volatile ( ++ "movl %%esp, %0" ++ : "=r" (esp) ++ ); ++ + struct sys_info *sysinfo = &sysinfo_car; + + uint32_t bsp_apicid = 0, val; + uint8_t byte; + msr_t msr; + +- timestamp_init(timestamp_get()); +- timestamp_add_now(TS_START_ROMSTAGE); +- + int s3resume = acpi_is_wakeup_s3(); + + if (!cpu_init_detectedx && boot_cpu()) { ++ /* Initial timestamp */ ++ timestamp_init(timestamp_get()); ++ timestamp_add_now(TS_START_ROMSTAGE); ++ + /* Initialize the printk spinlock */ + initialize_romstage_console_lock(); + +@@ -344,6 +362,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) + pci_write_config8(PCI_DEV(0, 0x14, 3), 0x78, byte); + } + ++ printk(BIOS_SPEW, "Initial stack pointer: %08x\n", esp); ++ + post_code(0x30); + + if (bist == 0) +@@ -397,7 +417,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) + if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) { + /* Core0 on each node is configured. Now setup any additional cores. */ + printk(BIOS_DEBUG, "start_other_cores()\n"); +- start_other_cores(); ++ start_other_cores(bsp_apicid); + post_code(0x37); + wait_all_other_cores_started(bsp_apicid); + } +@@ -455,7 +475,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) + + /* It's the time to set ctrl in sysinfo now; */ + printk(BIOS_DEBUG, "fill_mem_ctrl() detected %d nodes\n", sysinfo->nodes); +- fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); ++ if (is_fam15h()) ++ fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr_fam15); ++ else ++ fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr_fam10); + post_code(0x3D); + + #if 0 +@@ -527,5 +550,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) + */ + BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) + { ++ /* Force BUID to 0 */ ++ static const u8 swaplist[] = {0, 0, 0xFF, 0, 0xFF}; ++ if ((node == 0) && (link == 1)) { /* BSP SB link */ ++ *List = swaplist; ++ return 1; ++ } ++ + return 0; + } +diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c +index 82b96bf..75894d8 100644 +--- a/src/mainboard/asus/m4a78-em/romstage.c ++++ b/src/mainboard/asus/m4a78-em/romstage.c +@@ -151,7 +151,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) + #if CONFIG_LOGICAL_CPUS + /* Core0 on each node is configured. Now setup any additional cores. */ + printk(BIOS_DEBUG, "start_other_cores()\n"); +- start_other_cores(); ++ start_other_cores(bsp_apicid); + post_code(0x37); + wait_all_other_cores_started(bsp_apicid); + #endif +diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c +index 30975fa..f81cb95 100644 +--- a/src/mainboard/asus/m4a785-m/romstage.c ++++ b/src/mainboard/asus/m4a785-m/romstage.c +@@ -151,7 +151,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) + #if CONFIG_LOGICAL_CPUS + /* Core0 on each node is configured. Now setup any additional cores. */ + printk(BIOS_DEBUG, "start_other_cores()\n"); +- start_other_cores(); ++ start_other_cores(bsp_apicid); + post_code(0x37); + wait_all_other_cores_started(bsp_apicid); + #endif +diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c +index 4edaba2..9914025 100644 +--- a/src/mainboard/asus/m5a88-v/romstage.c ++++ b/src/mainboard/asus/m5a88-v/romstage.c +@@ -152,7 +152,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) + #if CONFIG_LOGICAL_CPUS + /* Core0 on each node is configured. Now setup any additional cores. */ + printk(BIOS_DEBUG, "start_other_cores()\n"); +- start_other_cores(); ++ start_other_cores(bsp_apicid); + post_code(0x37); + wait_all_other_cores_started(bsp_apicid); + #endif +diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c +index 447012b..c57454d 100644 +--- a/src/mainboard/avalue/eax-785e/romstage.c ++++ b/src/mainboard/avalue/eax-785e/romstage.c +@@ -156,7 +156,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) + #if CONFIG_LOGICAL_CPUS + /* Core0 on each node is configured. Now setup any additional cores. */ + printk(BIOS_DEBUG, "start_other_cores()\n"); +- start_other_cores(); ++ start_other_cores(bsp_apicid); + post_code(0x37); + wait_all_other_cores_started(bsp_apicid); + #endif +diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c +index 444e59d..ae661e8 100644 +--- a/src/mainboard/gigabyte/ma785gm/romstage.c ++++ b/src/mainboard/gigabyte/ma785gm/romstage.c +@@ -146,7 +146,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) + #if CONFIG_LOGICAL_CPUS + /* Core0 on each node is configured. Now setup any additional cores. */ + printk(BIOS_DEBUG, "start_other_cores()\n"); +- start_other_cores(); ++ start_other_cores(bsp_apicid); + post_code(0x37); + wait_all_other_cores_started(bsp_apicid); + #endif +diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c +index 705d7c5..968aa8f 100644 +--- a/src/mainboard/gigabyte/ma785gmt/romstage.c ++++ b/src/mainboard/gigabyte/ma785gmt/romstage.c +@@ -146,7 +146,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) + #if CONFIG_LOGICAL_CPUS + /* Core0 on each node is configured. Now setup any additional cores. */ + printk(BIOS_DEBUG, "start_other_cores()\n"); +- start_other_cores(); ++ start_other_cores(bsp_apicid); + post_code(0x37); + wait_all_other_cores_started(bsp_apicid); + #endif +diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c +index 5d21801..7e18724 100644 +--- a/src/mainboard/gigabyte/ma78gm/romstage.c ++++ b/src/mainboard/gigabyte/ma78gm/romstage.c +@@ -149,7 +149,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) + #if CONFIG_LOGICAL_CPUS + /* Core0 on each node is configured. Now setup any additional cores. */ + printk(BIOS_DEBUG, "start_other_cores()\n"); +- start_other_cores(); ++ start_other_cores(bsp_apicid); + post_code(0x37); + wait_all_other_cores_started(bsp_apicid); + #endif +diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c +index 26c0bb9..e70d274 100644 +--- a/src/mainboard/hp/dl165_g6_fam10/romstage.c ++++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c +@@ -160,7 +160,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) + #if CONFIG_LOGICAL_CPUS + /* Core0 on each node is configured. Now setup any additional cores. */ + printk(BIOS_DEBUG, "start_other_cores()\n"); +- start_other_cores(); ++ start_other_cores(bsp_apicid); + post_code(0x37); + wait_all_other_cores_started(bsp_apicid); + #endif +diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c +index 321eea6..89cfe83 100644 +--- a/src/mainboard/iei/kino-780am2-fam10/romstage.c ++++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c +@@ -149,7 +149,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) + #if CONFIG_LOGICAL_CPUS + /* Core0 on each node is configured. Now setup any additional cores. */ + printk(BIOS_DEBUG, "start_other_cores()\n"); +- start_other_cores(); ++ start_other_cores(bsp_apicid); + post_code(0x37); + wait_all_other_cores_started(bsp_apicid); + #endif +diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c +index 93dd2ce..6106b66 100644 +--- a/src/mainboard/jetway/pa78vm5/romstage.c ++++ b/src/mainboard/jetway/pa78vm5/romstage.c +@@ -154,7 +154,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) + #if CONFIG_LOGICAL_CPUS + /* Core0 on each node is configured. Now setup any additional cores. */ + printk(BIOS_DEBUG, "start_other_cores()\n"); +- start_other_cores(); ++ start_other_cores(bsp_apicid); + post_code(0x37); + wait_all_other_cores_started(bsp_apicid); + #endif +diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c +index 5da971f..f552db5 100644 +--- a/src/mainboard/msi/ms9652_fam10/romstage.c ++++ b/src/mainboard/msi/ms9652_fam10/romstage.c +@@ -177,7 +177,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) + #if CONFIG_LOGICAL_CPUS + /* Core0 on each node is configured. Now setup any additional cores. */ + printk(BIOS_DEBUG, "start_other_cores()\n"); +- start_other_cores(); ++ start_other_cores(bsp_apicid); + post_code(0x37); + printk(BIOS_DEBUG, "wait_all_other_cores_started()\n"); + wait_all_other_cores_started(bsp_apicid); +diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c +index 1425546..333a213 100644 +--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c ++++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c +@@ -171,7 +171,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) + #if CONFIG_LOGICAL_CPUS + /* Core0 on each node is configured. Now setup any additional cores. */ + printk(BIOS_DEBUG, "start_other_cores()\n"); +- start_other_cores(); ++ start_other_cores(bsp_apicid); + post_code(0x37); + wait_all_other_cores_started(bsp_apicid); + #endif +diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c +index 4721eba..8caf615 100644 +--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c ++++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c +@@ -238,7 +238,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) + #if CONFIG_LOGICAL_CPUS + /* Core0 on each node is configured. Now setup any additional cores. */ + printk(BIOS_DEBUG, "start_other_cores()\n"); +- start_other_cores(); ++ start_other_cores(bsp_apicid); + post_code(0x37); + wait_all_other_cores_started(bsp_apicid); + #endif +diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c +index 858aca0..0e5adcd 100644 +--- a/src/mainboard/supermicro/h8scm_fam10/romstage.c ++++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c +@@ -162,7 +162,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) + #if CONFIG_LOGICAL_CPUS + /* Core0 on each node is configured. Now setup any additional cores. */ + printk(BIOS_DEBUG, "start_other_cores()\n"); +- start_other_cores(); ++ start_other_cores(bsp_apicid); + post_code(0x37); + wait_all_other_cores_started(bsp_apicid); + #endif +diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c +index cdf51b1..0fe004e 100644 +--- a/src/mainboard/tyan/s2912_fam10/romstage.c ++++ b/src/mainboard/tyan/s2912_fam10/romstage.c +@@ -173,7 +173,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) + #if CONFIG_LOGICAL_CPUS + /* Core0 on each node is configured. Now setup any additional cores. */ + printk(BIOS_DEBUG, "start_other_cores()\n"); +- start_other_cores(); ++ start_other_cores(bsp_apicid); + post_code(0x37); + wait_all_other_cores_started(bsp_apicid); + #endif +diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c +index 849f4a8..82bf885 100644 +--- a/src/northbridge/amd/amdht/h3finit.c ++++ b/src/northbridge/amd/amdht/h3finit.c +@@ -389,13 +389,49 @@ static u8 convertNodeToLink(u8 srcNode, u8 targetNode, sMainData *pDat) + */ + static void htDiscoveryFloodFill(sMainData *pDat) + { +- u8 currentNode = 0; +- u8 currentLink; ++ uint8_t currentNode = 0; ++ uint8_t currentLink; ++ uint8_t currentLinkID; ++ ++ /* NOTE ++ * Each node inside a dual node (socket G34) processor must share ++ * an adjacent node ID. Alter the link scan order such that the ++ * other internal node is always scanned first... ++ */ ++ uint8_t currentLinkScanOrder_Default[8] = {0, 1, 2, 3, 4, 5, 6, 7}; ++ uint8_t currentLinkScanOrder_G34_Fam10[8] = {1, 0, 2, 3, 4, 5, 6, 7}; ++ uint8_t currentLinkScanOrder_G34_Fam15[8] = {2, 0, 1, 3, 4, 5, 6, 7}; ++ ++ uint8_t fam15h = 0; ++ uint8_t rev_gte_d = 0; ++ uint8_t dual_node = 0; ++ uint32_t f3xe8; ++ uint32_t family; ++ uint32_t model; ++ ++ f3xe8 = pci_read_config32(NODE_PCI(0, 3), 0xe8); ++ ++ family = model = cpuid_eax(0x80000001); ++ model = ((model & 0xf0000) >> 12) | ((model & 0xf0) >> 4); ++ family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); ++ ++ if (family >= 0x6f) { ++ /* Family 15h or later */ ++ fam15h = 1; ++ } ++ ++ if ((model >= 0x8) || fam15h) ++ /* Revision D or later */ ++ rev_gte_d = 1; ++ ++ if (rev_gte_d) ++ /* Check for dual node capability */ ++ if (f3xe8 & 0x20000000) ++ dual_node = 1; + + /* Entries are always added in pairs, the even indices are the 'source' + * side closest to the BSP, the odd indices are the 'destination' side + */ +- + while (currentNode <= pDat->NodesDiscovered) + { + u32 temp; +@@ -423,11 +459,24 @@ static void htDiscoveryFloodFill(sMainData *pDat) + /* Enable routing tables on currentNode*/ + pDat->nb->enableRoutingTables(currentNode, pDat->nb); + +- for (currentLink = 0; currentLink < pDat->nb->maxLinks; currentLink++) ++ for (currentLinkID = 0; currentLinkID < pDat->nb->maxLinks; currentLinkID++) + { + BOOL linkfound; + u8 token; + ++ if (currentLinkID < 8) { ++ if (dual_node) { ++ if (fam15h) ++ currentLink = currentLinkScanOrder_G34_Fam15[currentLinkID]; ++ else ++ currentLink = currentLinkScanOrder_G34_Fam10[currentLinkID]; ++ } else { ++ currentLink = currentLinkScanOrder_Default[currentLinkID]; ++ } ++ } else { ++ currentLink = currentLinkID; ++ } ++ + if (pDat->HtBlock->AMD_CB_IgnoreLink && pDat->HtBlock->AMD_CB_IgnoreLink(currentNode, currentLink)) + continue; + +diff --git a/src/northbridge/amd/amdht/h3ncmn.c b/src/northbridge/amd/amdht/h3ncmn.c +index 8f9177f..1026d0e 100644 +--- a/src/northbridge/amd/amdht/h3ncmn.c ++++ b/src/northbridge/amd/amdht/h3ncmn.c +@@ -51,8 +51,9 @@ + #define REG_NODE_ID_0X60 0x60 + #define REG_UNIT_ID_0X64 0x64 + #define REG_LINK_TRANS_CONTROL_0X68 0x68 +-#define REG_LINK_INIT_CONTROL_0X6C 0x6C ++#define REG_LINK_INIT_CONTROL_0X6C 0x6c + #define REG_HT_CAP_BASE_0X80 0x80 ++#define REG_NORTHBRIDGE_CFG_3X8C 0x8c + #define REG_HT_LINK_RETRY0_0X130 0x130 + #define REG_HT_TRAFFIC_DIST_0X164 0x164 + #define REG_HT_LINK_EXT_CONTROL0_0X170 0x170 +@@ -91,6 +92,21 @@ + *** FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS *** + ***************************************************************************/ + ++static inline uint8_t is_fam15h(void) ++{ ++ uint8_t fam15h = 0; ++ uint32_t family; ++ ++ family = cpuid_eax(0x80000001); ++ family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); ++ ++ if (family >= 0x6f) ++ /* Family 15h or later */ ++ fam15h = 1; ++ ++ return fam15h; ++} ++ + /***************************************************************************//** + * + * SBDFO +@@ -219,8 +235,18 @@ static void writeRoutingTable(u8 node, u8 target, u8 link, cNorthBridge *nb) + + static void writeNodeID(u8 node, u8 nodeID, cNorthBridge *nb) + { +- u32 temp = nodeID; ++ u32 temp; + ASSERT((node < nb->maxNodes) && (nodeID < nb->maxNodes)); ++ if (is_fam15h()) { ++ temp = 1; ++ AmdPCIWriteBits(MAKE_SBDFO(makePCISegmentFromNode(node), ++ makePCIBusFromNode(node), ++ makePCIDeviceFromNode(node), ++ CPU_NB_FUNC_03, ++ REG_NORTHBRIDGE_CFG_3X8C), ++ 22, 22, &temp); ++ } ++ temp = nodeID; + AmdPCIWriteBits(MAKE_SBDFO(makePCISegmentFromNode(node), + makePCIBusFromNode(node), + makePCIDeviceFromNode(node), +diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c +index c0ccc69..a4aaa12 100644 +--- a/src/northbridge/amd/amdht/ht_wrapper.c ++++ b/src/northbridge/amd/amdht/ht_wrapper.c +@@ -92,16 +92,132 @@ static u32 get_nodes(void) + */ + static void AMD_CB_EventNotify (u8 evtClass, u16 event, const u8 *pEventData0) + { +- u8 i; ++ uint8_t i; ++ uint8_t log_level; ++ uint8_t dump_event_detail; + +- printk(BIOS_DEBUG, "AMD_CB_EventNotify()\n"); +- printk(BIOS_DEBUG, " event class: %02x\n event: %04x\n data: ", evtClass, event); ++ printk(BIOS_DEBUG, "AMD_CB_EventNotify(): "); + +- for (i = 0; i < *pEventData0; i++) { +- printk(BIOS_DEBUG, " %02x ", *(pEventData0 + i)); ++ /* Decode event */ ++ dump_event_detail = 1; ++ switch (evtClass) { ++ case HT_EVENT_CLASS_CRITICAL: ++ log_level = BIOS_DEBUG; ++ printk(log_level, "CRITICAL"); ++ break; ++ case HT_EVENT_CLASS_ERROR: ++ log_level = BIOS_DEBUG; ++ printk(log_level, "ERROR"); ++ break; ++ case HT_EVENT_CLASS_HW_FAULT: ++ log_level = BIOS_DEBUG; ++ printk(log_level, "HARDWARE FAULT"); ++ break; ++ case HT_EVENT_CLASS_WARNING: ++ log_level = BIOS_DEBUG; ++ printk(log_level, "WARNING"); ++ break; ++ case HT_EVENT_CLASS_INFO: ++ log_level = BIOS_DEBUG; ++ printk(log_level, "INFO"); ++ break; ++ default: ++ log_level = BIOS_DEBUG; ++ printk(log_level, "UNKNOWN"); ++ break; + } +- printk(BIOS_DEBUG, "\n"); ++ printk(log_level, ": "); + ++ switch(event) { ++ case HT_EVENT_COH_EVENTS: ++ printk(log_level, "HT_EVENT_COH_EVENTS"); ++ break; ++ case HT_EVENT_COH_NO_TOPOLOGY: ++ printk(log_level, "HT_EVENT_COH_NO_TOPOLOGY"); ++ break; ++ case HT_EVENT_COH_LINK_EXCEED: ++ printk(log_level, "HT_EVENT_COH_LINK_EXCEED"); ++ break; ++ case HT_EVENT_COH_FAMILY_FEUD: ++ printk(log_level, "HT_EVENT_COH_FAMILY_FEUD"); ++ break; ++ case HT_EVENT_COH_NODE_DISCOVERED: ++ { ++ printk(log_level, "HT_EVENT_COH_NODE_DISCOVERED"); ++ sHtEventCohNodeDiscovered *evt = (sHtEventCohNodeDiscovered*)pEventData0; ++ printk(log_level, ": node %d link %d new node: %d", ++ evt->node, evt->link, evt->newNode); ++ dump_event_detail = 0; ++ break; ++ } ++ case HT_EVENT_COH_MPCAP_MISMATCH: ++ printk(log_level, "HT_EVENT_COH_MPCAP_MISMATCH"); ++ break; ++ case HT_EVENT_NCOH_EVENTS: ++ printk(log_level, "HT_EVENT_NCOH_EVENTS"); ++ break; ++ case HT_EVENT_NCOH_BUID_EXCEED: ++ printk(log_level, "HT_EVENT_NCOH_BUID_EXCEED"); ++ break; ++ case HT_EVENT_NCOH_LINK_EXCEED: ++ printk(log_level, "HT_EVENT_NCOH_LINK_EXCEED"); ++ break; ++ case HT_EVENT_NCOH_BUS_MAX_EXCEED: ++ printk(log_level, "HT_EVENT_NCOH_BUS_MAX_EXCEED"); ++ break; ++ case HT_EVENT_NCOH_CFG_MAP_EXCEED: ++ printk(log_level, "HT_EVENT_NCOH_CFG_MAP_EXCEED"); ++ break; ++ case HT_EVENT_NCOH_DEVICE_FAILED: ++ { ++ printk(log_level, "HT_EVENT_NCOH_DEVICE_FAILED"); ++ sHtEventNcohDeviceFailed *evt = (sHtEventNcohDeviceFailed*)pEventData0; ++ printk(log_level, ": node %d link %d depth: %d attemptedBUID: %d", ++ evt->node, evt->link, evt->depth, evt->attemptedBUID); ++ dump_event_detail = 0; ++ break; ++ } ++ case HT_EVENT_NCOH_AUTO_DEPTH: ++ { ++ printk(log_level, "HT_EVENT_NCOH_AUTO_DEPTH"); ++ sHtEventNcohAutoDepth *evt = (sHtEventNcohAutoDepth*)pEventData0; ++ printk(log_level, ": node %d link %d depth: %d", ++ evt->node, evt->link, evt->depth); ++ dump_event_detail = 0; ++ break; ++ } ++ case HT_EVENT_OPT_EVENTS: ++ printk(log_level, "HT_EVENT_OPT_EVENTS"); ++ break; ++ case HT_EVENT_OPT_REQUIRED_CAP_RETRY: ++ printk(log_level, "HT_EVENT_OPT_REQUIRED_CAP_RETRY"); ++ break; ++ case HT_EVENT_OPT_REQUIRED_CAP_GEN3: ++ printk(log_level, "HT_EVENT_OPT_REQUIRED_CAP_GEN3"); ++ break; ++ case HT_EVENT_HW_EVENTS: ++ printk(log_level, "HT_EVENT_HW_EVENTS"); ++ break; ++ case HT_EVENT_HW_SYNCHFLOOD: ++ printk(log_level, "HT_EVENT_HW_SYNCHFLOOD"); ++ break; ++ case HT_EVENT_HW_HTCRC: ++ printk(log_level, "HT_EVENT_HW_HTCRC"); ++ break; ++ default: ++ printk(log_level, "HT_EVENT_UNKNOWN"); ++ break; ++ } ++ printk(log_level, "\n"); ++ ++ if (dump_event_detail) { ++ printk(BIOS_DEBUG, " event class: %02x\n event: %04x\n data: ", evtClass, event); ++ ++ for (i = 0; i < *pEventData0; i++) { ++ printk(BIOS_DEBUG, " %02x ", *(pEventData0 + i)); ++ } ++ printk(BIOS_DEBUG, "\n"); ++ } + } + + /** +@@ -210,9 +326,10 @@ void amd_ht_fixup(struct sys_info *sysinfo) { + for (node = 0; node < node_count; node++) { + f3xe8 = pci_read_config32(NODE_PCI(node, 3), 0xe8); + uint8_t internal_node_number = ((f3xe8 & 0xc0000000) >> 30); +- printk(BIOS_DEBUG, "amd_ht_fixup(): node %d (internal node ID %d): disabling defective HT link\n", node, internal_node_number); ++ printk(BIOS_DEBUG, "amd_ht_fixup(): node %d (internal node ID %d): disabling defective HT link", node, internal_node_number); + if (internal_node_number == 0) { + uint8_t package_link_3_connected = pci_read_config32(NODE_PCI(node, 0), (fam15h)?0x98:0xd8) & 0x1; ++ printk(BIOS_DEBUG, " (L3 connected: %d)\n", package_link_3_connected); + if (package_link_3_connected) { + /* Set WidthIn and WidthOut to 0 */ + dword = pci_read_config32(NODE_PCI(node, 0), (fam15h)?0x84:0xc4); +@@ -234,15 +351,21 @@ void amd_ht_fixup(struct sys_info *sysinfo) { + } + } else if (internal_node_number == 1) { + uint8_t package_link_3_connected = pci_read_config32(NODE_PCI(node, 0), (fam15h)?0xf8:0xb8) & 0x1; ++ printk(BIOS_DEBUG, " (L3 connected: %d)\n", package_link_3_connected); + if (package_link_3_connected) { + /* Set WidthIn and WidthOut to 0 */ + dword = pci_read_config32(NODE_PCI(node, 0), (fam15h)?0xe4:0xa4); + dword &= ~0x77000000; + pci_write_config32(NODE_PCI(node, 0), (fam15h)?0xe4:0xa4, dword); + /* Set Ganged to 1 */ +- dword = pci_read_config32(NODE_PCI(node, 0), (fam15h)?0x18c:0x174); ++ /* WARNING ++ * The Family 15h BKDG states that 0x18c should be set, ++ * however this is in error. 0x17c is the correct control ++ * register (sublink 0) for these processors... ++ */ ++ dword = pci_read_config32(NODE_PCI(node, 0), (fam15h)?0x17c:0x174); + dword |= 0x00000001; +- pci_write_config32(NODE_PCI(node, 0), (fam15h)?0x18c:0x174, dword); ++ pci_write_config32(NODE_PCI(node, 0), (fam15h)?0x17c:0x174, dword); + } else { + /* Set ConnDly to 1 */ + dword = pci_read_config32(NODE_PCI(node, 0), 0x16c); +diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +index 1c9c568..ccdd0df 100644 +--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c ++++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +@@ -5443,6 +5443,7 @@ static void mct_InitialMCT_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc + cpu_divisor = (0x1 << cpu_did); + pMCTstat->TSCFreq = (100 * (cpu_fid + 0x10)) / cpu_divisor; + ++ printk(BIOS_DEBUG, "mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15\n"); + mct_ForceNBPState0_En_Fam15(pMCTstat, pDCTstat); + } else { + /* K10 BKDG v3.62 section 2.8.9.2 */ +-- +1.7.9.5 + diff --git a/resources/libreboot/patch/kgpe-d16/0088-northbridge-amd-amdfam10-Add-probe-filter-support.patch b/resources/libreboot/patch/kgpe-d16/0090-northbridge-amd-amdfam10-Add-probe-filter-support.patch index 09531d0..1a684e2 100644 --- a/resources/libreboot/patch/kgpe-d16/0088-northbridge-amd-amdfam10-Add-probe-filter-support.patch +++ b/resources/libreboot/patch/kgpe-d16/0090-northbridge-amd-amdfam10-Add-probe-filter-support.patch @@ -1,17 +1,19 @@ -From c2436d732bdb97abdc4b4784598bc6c5d467a61f Mon Sep 17 00:00:00 2001 +From 7aca5c828dde51868dcf4c46ba19f5dc34aaf7d3 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sun, 2 Aug 2015 21:06:39 -0500 -Subject: [PATCH 088/139] northbridge/amd/amdfam10: Add probe filter support +Subject: [PATCH 090/143] northbridge/amd/amdfam10: Add probe filter support Change-Id: I00a27a828260be8685ae622cfa5a4995add95a8e Signed-off-by: Timothy Pearson --- - src/cpu/amd/family_10h-family_15h/init_cpus.c | 13 +++ - src/northbridge/amd/amdfam10/northbridge.c | 144 +++++++++++++++++++++++++- - 2 files changed, 156 insertions(+), 1 deletion(-) + src/cpu/amd/family_10h-family_15h/init_cpus.c | 13 ++ + .../amd/family_10h-family_15h/model_10xxx_init.c | 22 +++ + src/northbridge/amd/amdfam10/northbridge.c | 144 +++++++++++++++++++- + src/northbridge/amd/amdht/h3ncmn.c | 22 +++ + 4 files changed, 200 insertions(+), 1 deletion(-) diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c -index 986c024..2bc54dc 100644 +index 4e5098e..7d303e0 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -445,6 +445,19 @@ static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo) @@ -34,8 +36,41 @@ index 986c024..2bc54dc 100644 #if CONFIG_SET_FIDVID #if CONFIG_LOGICAL_CPUS && CONFIG_SET_FIDVID_CORE0_ONLY // Run on all AP for proper FID/VID setup. +diff --git a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c +index 8a61f13..5c590b8 100644 +--- a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c ++++ b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c +@@ -54,6 +54,28 @@ static inline uint8_t is_fam15h(void) + return fam15h; + } + ++static inline uint8_t is_gt_rev_d(void) ++{ ++ uint8_t fam15h = 0; ++ uint8_t rev_gte_d = 0; ++ uint32_t family; ++ uint32_t model; ++ ++ family = model = cpuid_eax(0x80000001); ++ model = ((model & 0xf0000) >> 12) | ((model & 0xf0) >> 4); ++ family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); ++ ++ if (family >= 0x6f) ++ /* Family 15h or later */ ++ fam15h = 1; ++ ++ if ((model >= 0x8) || fam15h) ++ /* Revision D or later */ ++ rev_gte_d = 1; ++ ++ return rev_gte_d; ++} ++ + static volatile uint8_t fam15h_startup_flags[MAX_NODES_SUPPORTED][MAX_CORES_SUPPORTED] = {{ 0 }}; + + static void model_10xxx_init(device_t dev) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c -index 95e902d..cdb8afa 100644 +index 52b5ffb..808cd3a 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -30,10 +30,13 @@ @@ -209,6 +244,39 @@ index 95e902d..cdb8afa 100644 initialize_cpus(dev->link_list); #if CONFIG_AMD_SB_CIMX sb_After_Pci_Init(); +diff --git a/src/northbridge/amd/amdht/h3ncmn.c b/src/northbridge/amd/amdht/h3ncmn.c +index 1026d0e..a27ee5b 100644 +--- a/src/northbridge/amd/amdht/h3ncmn.c ++++ b/src/northbridge/amd/amdht/h3ncmn.c +@@ -107,6 +107,28 @@ static inline uint8_t is_fam15h(void) + return fam15h; + } + ++static inline uint8_t is_gt_rev_d(void) ++{ ++ uint8_t fam15h = 0; ++ uint8_t rev_gte_d = 0; ++ uint32_t family; ++ uint32_t model; ++ ++ family = model = cpuid_eax(0x80000001); ++ model = ((model & 0xf0000) >> 12) | ((model & 0xf0) >> 4); ++ family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); ++ ++ if (family >= 0x6f) ++ /* Family 15h or later */ ++ fam15h = 1; ++ ++ if ((model >= 0x8) || fam15h) ++ /* Revision D or later */ ++ rev_gte_d = 1; ++ ++ return rev_gte_d; ++} ++ + /***************************************************************************//** + * + * SBDFO -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0089-cpu-amd-family_10h-family_15h-Bring-initial-HT-regis.patch b/resources/libreboot/patch/kgpe-d16/0091-cpu-amd-family_10h-family_15h-Bring-initial-HT-regis.patch index 4b5845b..a6bf101 100644 --- a/resources/libreboot/patch/kgpe-d16/0089-cpu-amd-family_10h-family_15h-Bring-initial-HT-regis.patch +++ b/resources/libreboot/patch/kgpe-d16/0091-cpu-amd-family_10h-family_15h-Bring-initial-HT-regis.patch @@ -1,13 +1,13 @@ -From 5fb316c1ccf4427fbd86458e85c3bda2076f6fa0 Mon Sep 17 00:00:00 2001 +From 6e43fcda4e95ee0daa72f35fb46d10789da1fe7e Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sun, 2 Aug 2015 21:18:29 -0500 -Subject: [PATCH 089/139] cpu/amd/family_10h-family_15h: Bring initial HT +Subject: [PATCH 091/143] cpu/amd/family_10h-family_15h: Bring initial HT register configuration in line with BKDG Change-Id: I009b6f478340e2dbfcda2b4534473d4397f9ecef Signed-off-by: Timothy Pearson --- - src/cpu/amd/family_10h-family_15h/defaults.h | 168 +++++++++++++++++++++------ + src/cpu/amd/family_10h-family_15h/defaults.h | 168 ++++++++++++++++++++------ 1 file changed, 133 insertions(+), 35 deletions(-) diff --git a/src/cpu/amd/family_10h-family_15h/defaults.h b/src/cpu/amd/family_10h-family_15h/defaults.h @@ -244,5 +244,5 @@ index 513d169..1080cfc 100644 + [20:16] RttIndex = 04h */ }; -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0090-northbridge-amd-amdmct-mct_ddr3-Move-K10D-configurat.patch b/resources/libreboot/patch/kgpe-d16/0092-northbridge-amd-amdmct-mct_ddr3-Move-K10D-configurat.patch index c43e297..9343916 100644 --- a/resources/libreboot/patch/kgpe-d16/0090-northbridge-amd-amdmct-mct_ddr3-Move-K10D-configurat.patch +++ b/resources/libreboot/patch/kgpe-d16/0092-northbridge-amd-amdmct-mct_ddr3-Move-K10D-configurat.patch @@ -1,18 +1,18 @@ -From 65404b72da34b2f786af5fa1901531e50f59d0d7 Mon Sep 17 00:00:00 2001 +From 3971a27fdb1e98badb9a4368c241e7820ae7ba45 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sun, 2 Aug 2015 21:23:02 -0500 -Subject: [PATCH 090/139] northbridge/amd/amdmct/mct_ddr3: Move K10D +Subject: [PATCH 092/143] northbridge/amd/amdmct/mct_ddr3: Move K10D configuration into separate file Change-Id: Id45888f266fac7810a63fef43b8d7a0ee40cbf70 Signed-off-by: Timothy Pearson --- - src/northbridge/amd/amdfam10/raminit_amdmct.c | 1 + - src/northbridge/amd/amdmct/amddefs.h | 5 +- - src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 133 ++++++++++++------------- - src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c | 4 +- - src/northbridge/amd/amdmct/mct_ddr3/mctprod.c | 65 ++++++++++++ - 5 files changed, 132 insertions(+), 76 deletions(-) + src/northbridge/amd/amdfam10/raminit_amdmct.c | 1 + + src/northbridge/amd/amdmct/amddefs.h | 5 +- + src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 131 +++++++++++------------- + src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c | 4 +- + src/northbridge/amd/amdmct/mct_ddr3/mctprod.c | 65 ++++++++++++ + 5 files changed, 130 insertions(+), 76 deletions(-) create mode 100644 src/northbridge/amd/amdmct/mct_ddr3/mctprod.c diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c @@ -56,7 +56,7 @@ index 7aa4698..60d3c16 100644 \ No newline at end of file +#define AMD_PKGTYPE_C32 5 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c -index 0b61106..1167976 100644 +index ccdd0df..1167976 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -182,6 +182,7 @@ static void SyncSetting(struct DCTStatStruc *pDCTstat); @@ -67,10 +67,10 @@ index 0b61106..1167976 100644 static void read_dqs_receiver_enable_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg); -@@ -2677,13 +2678,13 @@ static void MCTMemClr_D(struct MCTStatStruc *pMCTstat, - } - +@@ -2679,13 +2680,11 @@ static void MCTMemClr_D(struct MCTStatStruc *pMCTstat, for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { + pDCTstat = pDCTstatA + Node; + - /* Configure and enable prefetchers */ - if (is_fam15h()) - dword = 0x0ce00f41; /* BKDG recommended */ @@ -78,8 +78,6 @@ index 0b61106..1167976 100644 - dword = 0x0fe40fc0; /* BKDG recommended */ - dword |= MCCH_FlushWrOnStpGnt; /* Set for S3 */ - Set_NB32(pDCTstat->dev_dct, 0x11c, dword); -+ pDCTstat = pDCTstatA + Node; -+ + /* Enable prefetchers */ + dword = Get_NB32(pDCTstat->dev_dct, 0x11c); /* Memory Controller Configuration High */ + dword &= ~(0x1 << 13); /* PrefIoDis = 0 */ @@ -88,7 +86,7 @@ index 0b61106..1167976 100644 } } -@@ -4925,31 +4926,33 @@ static void Set_OtherTiming(struct MCTStatStruc *pMCTstat, +@@ -4927,31 +4926,33 @@ static void Set_OtherTiming(struct MCTStatStruc *pMCTstat, Get_TrwtTO(pMCTstat, pDCTstat, dct); Get_TrwtWB(pMCTstat, pDCTstat); @@ -147,7 +145,7 @@ index 0b61106..1167976 100644 } static void Get_Trdrd(struct MCTStatStruc *pMCTstat, -@@ -4960,6 +4963,8 @@ static void Get_Trdrd(struct MCTStatStruc *pMCTstat, +@@ -4962,6 +4963,8 @@ static void Get_Trdrd(struct MCTStatStruc *pMCTstat, Trdrd = ((int8_t)(pDCTstat->DqsRcvEnGrossMax - pDCTstat->DqsRcvEnGrossMin) >> 1) + 1; if (Trdrd > 8) Trdrd = 8; @@ -156,7 +154,7 @@ index 0b61106..1167976 100644 pDCTstat->Trdrd = Trdrd; } -@@ -5270,47 +5275,31 @@ static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat, +@@ -5272,47 +5275,31 @@ static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat, if (pDCTstat->NodePresent) { mct_PhyController_Config(pMCTstat, pDCTstat, 0); mct_PhyController_Config(pMCTstat, pDCTstat, 1); @@ -226,7 +224,7 @@ index 0b61106..1167976 100644 uint8_t wm1; uint8_t wm2; -@@ -5341,11 +5330,11 @@ static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat, +@@ -5343,11 +5330,11 @@ static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat, break; } @@ -334,5 +332,5 @@ index 0000000..2b62d4c + } +} -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0091-mainboard-asus-kgpe-d16-Fix-I-O-link-detection.patch b/resources/libreboot/patch/kgpe-d16/0093-mainboard-asus-kgpe-d16-Fix-I-O-link-detection.patch index 82d8664..9c9ae8f 100644 --- a/resources/libreboot/patch/kgpe-d16/0091-mainboard-asus-kgpe-d16-Fix-I-O-link-detection.patch +++ b/resources/libreboot/patch/kgpe-d16/0093-mainboard-asus-kgpe-d16-Fix-I-O-link-detection.patch @@ -1,16 +1,16 @@ -From 201dd98f77ab10c305a0a165494f3e10cc105d5d Mon Sep 17 00:00:00 2001 +From 0f5bc1acfc0274968095f9fc7c68299632788f1d Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sun, 2 Aug 2015 21:28:31 -0500 -Subject: [PATCH 091/139] mainboard/asus/kgpe-d16: Fix I/O link detection +Subject: [PATCH 093/143] mainboard/asus/kgpe-d16: Fix I/O link detection Change-Id: Ibefc9dc2e1e0267389eb8d716408bae6026ce084 Signed-off-by: Timothy Pearson --- - src/mainboard/asus/kgpe-d16/romstage.c | 3 ++- + src/mainboard/asus/kgpe-d16/romstage.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c -index 3504126..2b222f5 100644 +index f80fb8c..5d4005d 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -552,7 +552,8 @@ BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) @@ -24,5 +24,5 @@ index 3504126..2b222f5 100644 return 1; } -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0092-cpu-amd-family_10h-family_15h-Set-northbridge-thrott.patch b/resources/libreboot/patch/kgpe-d16/0094-cpu-amd-family_10h-family_15h-Set-northbridge-thrott.patch index 2f8039b..ac80918 100644 --- a/resources/libreboot/patch/kgpe-d16/0092-cpu-amd-family_10h-family_15h-Set-northbridge-thrott.patch +++ b/resources/libreboot/patch/kgpe-d16/0094-cpu-amd-family_10h-family_15h-Set-northbridge-thrott.patch @@ -1,18 +1,18 @@ -From 0e421105b63947e3a3dcbf7bf970e17af4519e6c Mon Sep 17 00:00:00 2001 +From 518f3db1ecce1fe883074b133eb19e3575098f3a Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sun, 2 Aug 2015 21:31:17 -0500 -Subject: [PATCH 092/139] cpu/amd/family_10h-family_15h: Set northbridge +Subject: [PATCH 094/143] cpu/amd/family_10h-family_15h: Set northbridge throttle values Change-Id: I6304b63708c65fedb9c2d46b8c862b7f0adf1102 Signed-off-by: Timothy Pearson --- - src/cpu/amd/family_10h-family_15h/init_cpus.c | 21 +------ - .../amd/family_10h-family_15h/model_10xxx_init.c | 66 ++++++++++++++++++++++ - 2 files changed, 67 insertions(+), 20 deletions(-) + src/cpu/amd/family_10h-family_15h/init_cpus.c | 21 +--------- + .../amd/family_10h-family_15h/model_10xxx_init.c | 44 ++++++++++++++++++++ + 2 files changed, 45 insertions(+), 20 deletions(-) diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c -index 2bc54dc..9aadbcf 100644 +index 7d303e0..d770f38 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -877,6 +877,7 @@ static u32 AMD_checkLinkType(u8 node, u8 link, u8 regoff) @@ -23,7 +23,7 @@ index 2bc54dc..9aadbcf 100644 return linktype; } -@@ -972,26 +973,6 @@ void cpuSetAMDMSR(uint8_t node_id) +@@ -971,26 +972,6 @@ void cpuSetAMDMSR(uint8_t node_id) } AMD_Errata298(); @@ -51,39 +51,10 @@ index 2bc54dc..9aadbcf 100644 if (revision & AMD_OR_C0) { uint32_t f3x1fc = pci_read_config32(NODE_PCI(node_id, 3), 0x1fc); diff --git a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c -index 8a61f13..7319539 100644 +index 5c590b8..7319539 100644 --- a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c +++ b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c -@@ -54,6 +54,28 @@ static inline uint8_t is_fam15h(void) - return fam15h; - } - -+static inline uint8_t is_gt_rev_d(void) -+{ -+ uint8_t fam15h = 0; -+ uint8_t rev_gte_d = 0; -+ uint32_t family; -+ uint32_t model; -+ -+ family = model = cpuid_eax(0x80000001); -+ model = ((model & 0xf0000) >> 12) | ((model & 0xf0) >> 4); -+ family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); -+ -+ if (family >= 0x6f) -+ /* Family 15h or later */ -+ fam15h = 1; -+ -+ if ((model >= 0x8) || fam15h) -+ /* Revision D or later */ -+ rev_gte_d = 1; -+ -+ return rev_gte_d; -+} -+ - static volatile uint8_t fam15h_startup_flags[MAX_NODES_SUPPORTED][MAX_CORES_SUPPORTED] = {{ 0 }}; - - static void model_10xxx_init(device_t dev) -@@ -136,6 +158,50 @@ static void model_10xxx_init(device_t dev) +@@ -158,6 +158,50 @@ static void model_10xxx_init(device_t dev) printk(BIOS_DEBUG, "siblings = %02d, ", siblings); #endif @@ -135,5 +106,5 @@ index 8a61f13..7319539 100644 msr = rdmsr(NB_CFG_MSR); msr.hi &= ~(1 << (46 - 32)); -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0093-cpu-amd-family_10h-family_15h-Fix-incorrect-revision.patch b/resources/libreboot/patch/kgpe-d16/0095-cpu-amd-family_10h-family_15h-Fix-incorrect-revision.patch index b446e30..90c5132 100644 --- a/resources/libreboot/patch/kgpe-d16/0093-cpu-amd-family_10h-family_15h-Fix-incorrect-revision.patch +++ b/resources/libreboot/patch/kgpe-d16/0095-cpu-amd-family_10h-family_15h-Fix-incorrect-revision.patch @@ -1,17 +1,17 @@ -From a50e4e220003702aaa83f8b852aa819975e07788 Mon Sep 17 00:00:00 2001 +From ba93fcaf7408e3e00c01056f9257c94b82302382 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sun, 2 Aug 2015 21:31:48 -0500 -Subject: [PATCH 093/139] cpu/amd/family_10h-family_15h: Fix incorrect revision - detection +Subject: [PATCH 095/143] cpu/amd/family_10h-family_15h: Fix incorrect + revision detection Change-Id: I7a881a94d62ed455415f9dfc887fd698ac919429 Signed-off-by: Timothy Pearson --- - src/cpu/amd/family_10h-family_15h/fidvid.c | 10 +++++----- + src/cpu/amd/family_10h-family_15h/fidvid.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c -index 471456a..ed8cafa 100644 +index d99c37f..7453ad4 100644 --- a/src/cpu/amd/family_10h-family_15h/fidvid.c +++ b/src/cpu/amd/family_10h-family_15h/fidvid.c @@ -375,7 +375,7 @@ static void recalculateVsSlamTimeSettingOnCorePre(device_t dev) @@ -60,5 +60,5 @@ index 471456a..ed8cafa 100644 /* Family 15h BKDG Rev. 3.14 D18F3x80 recommended settings */ pci_write_config32(dev, 0x80, 0xe20be281); -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0094-northbridge-amd-amdht-Add-support-for-HT3-2.8GHz-and.patch b/resources/libreboot/patch/kgpe-d16/0096-northbridge-amd-amdht-Add-support-for-HT3-2.8GHz-and.patch index 55957a1..579b106 100644 --- a/resources/libreboot/patch/kgpe-d16/0094-northbridge-amd-amdht-Add-support-for-HT3-2.8GHz-and.patch +++ b/resources/libreboot/patch/kgpe-d16/0096-northbridge-amd-amdht-Add-support-for-HT3-2.8GHz-and.patch @@ -1,20 +1,20 @@ -From 60d2c9d712e8d53b871961ca50d1a9d06a65051f Mon Sep 17 00:00:00 2001 +From e6a4225860ce1c83c5489fc2169fb7dc22225462 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sun, 2 Aug 2015 21:36:24 -0500 -Subject: [PATCH 094/139] northbridge/amd/amdht: Add support for HT3 2.8GHz and - up link frequencies +Subject: [PATCH 096/143] northbridge/amd/amdht: Add support for HT3 2.8GHz + and up link frequencies Change-Id: Ifa1592d26ba7deb034046fd3f2a15149117d9a76 Signed-off-by: Timothy Pearson --- - src/cpu/amd/family_10h-family_15h/defaults.h | 8 ++- - src/mainboard/asus/kgpe-d16/cmos.layout | 30 ++++---- - src/northbridge/amd/amdht/h3ffeat.h | 6 +- - src/northbridge/amd/amdht/h3finit.c | 93 ++++++++++++++---------- - src/northbridge/amd/amdht/h3finit.h | 18 +++-- - src/northbridge/amd/amdht/h3ncmn.c | 104 ++++++++++++++++++++------- - src/northbridge/amd/amdht/h3ncmn.h | 3 +- - 7 files changed, 177 insertions(+), 85 deletions(-) + src/cpu/amd/family_10h-family_15h/defaults.h | 8 ++- + src/mainboard/asus/kgpe-d16/cmos.layout | 30 ++++----- + src/northbridge/amd/amdht/h3ffeat.h | 6 +- + src/northbridge/amd/amdht/h3finit.c | 93 ++++++++++++++++---------- + src/northbridge/amd/amdht/h3finit.h | 18 +++-- + src/northbridge/amd/amdht/h3ncmn.c | 82 ++++++++++++++++------- + src/northbridge/amd/amdht/h3ncmn.h | 3 +- + 7 files changed, 155 insertions(+), 85 deletions(-) diff --git a/src/cpu/amd/family_10h-family_15h/defaults.h b/src/cpu/amd/family_10h-family_15h/defaults.h index 1080cfc..bff2efd 100644 @@ -347,39 +347,10 @@ index 58065b3..462f3e3 100644 /**---------------------------------------------------------------------------------------- diff --git a/src/northbridge/amd/amdht/h3ncmn.c b/src/northbridge/amd/amdht/h3ncmn.c -index 1026d0e..e03e5eb 100644 +index a27ee5b..e03e5eb 100644 --- a/src/northbridge/amd/amdht/h3ncmn.c +++ b/src/northbridge/amd/amdht/h3ncmn.c -@@ -107,6 +107,28 @@ static inline uint8_t is_fam15h(void) - return fam15h; - } - -+static inline uint8_t is_gt_rev_d(void) -+{ -+ uint8_t fam15h = 0; -+ uint8_t rev_gte_d = 0; -+ uint32_t family; -+ uint32_t model; -+ -+ family = model = cpuid_eax(0x80000001); -+ model = ((model & 0xf0000) >> 12) | ((model & 0xf0) >> 4); -+ family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); -+ -+ if (family >= 0x6f) -+ /* Family 15h or later */ -+ fam15h = 1; -+ -+ if ((model >= 0x8) || fam15h) -+ /* Revision D or later */ -+ rev_gte_d = 1; -+ -+ return rev_gte_d; -+} -+ - /***************************************************************************//** - * - * SBDFO -@@ -1292,7 +1314,7 @@ static u8 convertWidthToBits(u8 value, cNorthBridge *nb) +@@ -1314,7 +1314,7 @@ static u8 convertWidthToBits(u8 value, cNorthBridge *nb) * @return Frequency mask * ******************************************************************************/ @@ -388,7 +359,7 @@ index 1026d0e..e03e5eb 100644 { /* only up to HT1 speeds */ return (HT_FREQUENCY_LIMIT_HT1_ONLY); -@@ -1313,26 +1335,43 @@ static u16 ht1NorthBridgeFreqMask(u8 node, cNorthBridge *nb) +@@ -1335,26 +1335,43 @@ static u16 ht1NorthBridgeFreqMask(u8 node, cNorthBridge *nb) * @return = Frequency mask * ******************************************************************************/ @@ -438,7 +409,7 @@ index 1026d0e..e03e5eb 100644 } /* unlikely cases, but include as a defensive measure, also avoid trick above */ else if (nbCOF == 4) -@@ -1387,8 +1426,13 @@ static void gatherLinkData(sMainData *pDat, cNorthBridge *nb) +@@ -1409,8 +1426,13 @@ static void gatherLinkData(sMainData *pDat, cNorthBridge *nb) pDat->PortList[i].PrvWidthInCap = convertBitsToWidth((u8)temp, pDat->nb); AmdPCIReadBits(linkBase + HTHOST_FREQ_REV_REG, 31, 16, &temp); @@ -454,7 +425,7 @@ index 1026d0e..e03e5eb 100644 } else { -@@ -1445,7 +1489,7 @@ static void setLinkData(sMainData *pDat, cNorthBridge *nb) +@@ -1467,7 +1489,7 @@ static void setLinkData(sMainData *pDat, cNorthBridge *nb) { u8 i; SBDFO linkBase; @@ -463,7 +434,7 @@ index 1026d0e..e03e5eb 100644 for (i = 0; i < pDat->TotalLinks*2; i++) { -@@ -1506,10 +1550,19 @@ static void setLinkData(sMainData *pDat, cNorthBridge *nb) +@@ -1528,10 +1550,19 @@ static void setLinkData(sMainData *pDat, cNorthBridge *nb) temp = pDat->PortList[i].SelFrequency; if (pDat->PortList[i].Type == PORTLIST_TYPE_CPU) { @@ -485,7 +456,7 @@ index 1026d0e..e03e5eb 100644 { /* Enable for Gen3 frequencies */ temp = 1; -@@ -1519,27 +1572,27 @@ static void setLinkData(sMainData *pDat, cNorthBridge *nb) +@@ -1541,27 +1572,27 @@ static void setLinkData(sMainData *pDat, cNorthBridge *nb) /* Disable for Gen1 frequencies */ temp = 0; } @@ -525,7 +496,7 @@ index 1026d0e..e03e5eb 100644 /* Write the frequency setting */ AmdPCIWriteBits(linkBase + HTSLAVE_FREQ_REV_0_REG, 11, 8, &temp); -@@ -1700,6 +1753,9 @@ static void fam0fWriteHTLinkCmdBufferAlloc(u8 node, u8 link, u8 req, u8 preq, u8 +@@ -1722,6 +1753,9 @@ static void fam0fWriteHTLinkCmdBufferAlloc(u8 node, u8 link, u8 req, u8 preq, u8 /* Probe Command Buffers */ temp = prb; AmdPCIWriteBits(currentPtr, 15, 12, &temp); @@ -557,5 +528,5 @@ index 7f8f4d1..5795e9a 100644 void (*setLinkData)(sMainData *pDat, cNorthBridge *nb); -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0095-amd-family_10h-family_15h-Fix-poor-performance-on-Fa.patch b/resources/libreboot/patch/kgpe-d16/0097-amd-family_10h-family_15h-Fix-poor-performance-on-Fa.patch index 2cb270a..2afd17d 100644 --- a/resources/libreboot/patch/kgpe-d16/0095-amd-family_10h-family_15h-Fix-poor-performance-on-Fa.patch +++ b/resources/libreboot/patch/kgpe-d16/0097-amd-family_10h-family_15h-Fix-poor-performance-on-Fa.patch @@ -1,14 +1,14 @@ -From 7a203388d1cc86037723fb307efa37cfb9dd87ea Mon Sep 17 00:00:00 2001 +From 92145a02934f4e8d3044f734b001af21bdf50962 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Fri, 7 Aug 2015 19:04:49 -0500 -Subject: [PATCH 095/139] amd/family_10h-family_15h: Fix poor performance on +Subject: [PATCH 097/143] amd/family_10h-family_15h: Fix poor performance on Family 15h CPUs Change-Id: Ieb1f1fb5653651c98764de79636669802578d5f9 Signed-off-by: Timothy Pearson --- - src/cpu/amd/family_10h-family_15h/defaults.h | 13 ++++++-- - src/cpu/amd/family_10h-family_15h/init_cpus.c | 45 +++++++++++++++++++++++++-- + src/cpu/amd/family_10h-family_15h/defaults.h | 13 +++++-- + src/cpu/amd/family_10h-family_15h/init_cpus.c | 45 +++++++++++++++++++++++-- 2 files changed, 52 insertions(+), 6 deletions(-) diff --git a/src/cpu/amd/family_10h-family_15h/defaults.h b/src/cpu/amd/family_10h-family_15h/defaults.h @@ -49,7 +49,7 @@ index bff2efd..4868c5c 100644 { 3, 0x80, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0xE6002200, 0xFFFFFFFF }, diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c -index 9aadbcf..d1a93e7 100644 +index d770f38..67893ca1 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -847,8 +847,9 @@ static BOOL AMD_CpuFindCapability(u8 node, u8 cap_count, u8 * offset) @@ -79,7 +79,7 @@ index 9aadbcf..d1a93e7 100644 linktype |= HTPHY_LINKTYPE_HT3; else linktype |= HTPHY_LINKTYPE_HT1; -@@ -1150,6 +1156,39 @@ static void cpuSetAMDPCI(u8 node) +@@ -1151,6 +1157,39 @@ static void cpuSetAMDPCI(u8 node) pci_write_config32(NODE_PCI(node, 3), 0xd4, dword); } @@ -120,5 +120,5 @@ index 9aadbcf..d1a93e7 100644 } -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0096-amd-amdmct-mct_ddr3-Fix-poor-performance-on-Family-1.patch b/resources/libreboot/patch/kgpe-d16/0098-amd-amdmct-mct_ddr3-Fix-poor-performance-on-Family-1.patch index 0688150..e2b5340 100644 --- a/resources/libreboot/patch/kgpe-d16/0096-amd-amdmct-mct_ddr3-Fix-poor-performance-on-Family-1.patch +++ b/resources/libreboot/patch/kgpe-d16/0098-amd-amdmct-mct_ddr3-Fix-poor-performance-on-Family-1.patch @@ -1,18 +1,18 @@ -From 144073db29e770d85d01cbd6b093793aa951862f Mon Sep 17 00:00:00 2001 +From 4899f50dac5ae0c4bb9b4fa67e223f245085920c Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Fri, 7 Aug 2015 19:05:29 -0500 -Subject: [PATCH 096/139] amd/amdmct/mct_ddr3: Fix poor performance on Family +Subject: [PATCH 098/143] amd/amdmct/mct_ddr3: Fix poor performance on Family 15h CPUs Change-Id: Ib6bc197e43e40ba2b923b1eb1229bacafc8be360 Signed-off-by: Timothy Pearson --- - src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 370 +++++++++++++++++++++---- - src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 1 + - src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 65 ++++- - src/northbridge/amd/amdmct/mct_ddr3/mctproc.c | 49 +++- - src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 195 ++++++++++++- - src/northbridge/amd/amdmct/mct_ddr3/mctwl.c | 4 + + src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 370 ++++++++++++++++++++---- + src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 1 + + src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 65 ++++- + src/northbridge/amd/amdmct/mct_ddr3/mctproc.c | 49 +++- + src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 195 ++++++++++++- + src/northbridge/amd/amdmct/mct_ddr3/mctwl.c | 4 + 6 files changed, 604 insertions(+), 80 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -1085,5 +1085,5 @@ index 3153e46..28cc8f6 100644 /* -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0097-northbridge-amd-amdht-Fix-poor-performance-on-Family.patch b/resources/libreboot/patch/kgpe-d16/0099-northbridge-amd-amdht-Fix-poor-performance-on-Family.patch index 57d5ede..be85fe7 100644 --- a/resources/libreboot/patch/kgpe-d16/0097-northbridge-amd-amdht-Fix-poor-performance-on-Family.patch +++ b/resources/libreboot/patch/kgpe-d16/0099-northbridge-amd-amdht-Fix-poor-performance-on-Family.patch @@ -1,13 +1,13 @@ -From b9bcbf70cef87afd830e156d5081839fc066b89c Mon Sep 17 00:00:00 2001 +From e17ac6e74b96102528fa4915d6cebcb55f8e5db0 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Fri, 7 Aug 2015 19:05:45 -0500 -Subject: [PATCH 097/139] northbridge/amd/amdht: Fix poor performance on Family - 15h CPUs +Subject: [PATCH 099/143] northbridge/amd/amdht: Fix poor performance on + Family 15h CPUs Change-Id: I37db191c144c81aba5d4a1e6291db5669a35a31a Signed-off-by: Timothy Pearson --- - src/northbridge/amd/amdht/h3ncmn.c | 4 ++++ + src/northbridge/amd/amdht/h3ncmn.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/northbridge/amd/amdht/h3ncmn.c b/src/northbridge/amd/amdht/h3ncmn.c @@ -26,5 +26,5 @@ index e03e5eb..e377ff2 100644 AmdPCIWriteBits(linkBase + HTHOST_FREQ_REV_REG_2, 0, 0, &temp2); AmdPCIWriteBits(linkBase + HTHOST_FREQ_REV_REG, 11, 8, &temp); -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0098-northbridge-amd-amdfam10-Fix-poor-performance-on-Fam.patch b/resources/libreboot/patch/kgpe-d16/0100-northbridge-amd-amdfam10-Fix-poor-performance-on-Fam.patch index f107a68..cca5d53 100644 --- a/resources/libreboot/patch/kgpe-d16/0098-northbridge-amd-amdfam10-Fix-poor-performance-on-Fam.patch +++ b/resources/libreboot/patch/kgpe-d16/0100-northbridge-amd-amdfam10-Fix-poor-performance-on-Fam.patch @@ -1,14 +1,14 @@ -From 4d494c630bc75c675cae9cae68d6d0b44fcd1e22 Mon Sep 17 00:00:00 2001 +From 718c44eb4a990acd5aedd7a57bacf43ebb7c76a6 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Fri, 7 Aug 2015 19:06:09 -0500 -Subject: [PATCH 098/139] northbridge/amd/amdfam10: Fix poor performance on +Subject: [PATCH 100/143] northbridge/amd/amdfam10: Fix poor performance on Family 15h CPUs Change-Id: I193749bc767b7c1139de7cd67622a7b03298009b Signed-off-by: Timothy Pearson --- - src/northbridge/amd/amdfam10/nb_control.c | 4 ++-- - src/northbridge/amd/amdfam10/northbridge.c | 21 +++++++++++++++++++++ + src/northbridge/amd/amdfam10/nb_control.c | 4 ++-- + src/northbridge/amd/amdfam10/northbridge.c | 21 +++++++++++++++++++++ 2 files changed, 23 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/amdfam10/nb_control.c b/src/northbridge/amd/amdfam10/nb_control.c @@ -29,7 +29,7 @@ index f95b6f8..8e8dd57 100644 printk(BIOS_DEBUG, "done.\n"); } diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c -index cdb8afa..9f132c7 100644 +index 808cd3a..3a899c8 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -1759,6 +1759,8 @@ static void detect_and_enable_probe_filter(device_t dev) @@ -68,5 +68,5 @@ index cdb8afa..9f132c7 100644 /* Reenable L3 and DRAM scrubbers */ -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0099-cpu-amd-family_10h-family_15h-Configure-NB-register-.patch b/resources/libreboot/patch/kgpe-d16/0101-cpu-amd-family_10h-family_15h-Configure-NB-register-.patch index 2cbd57e..4dfb898 100644 --- a/resources/libreboot/patch/kgpe-d16/0099-cpu-amd-family_10h-family_15h-Configure-NB-register-.patch +++ b/resources/libreboot/patch/kgpe-d16/0101-cpu-amd-family_10h-family_15h-Configure-NB-register-.patch @@ -1,13 +1,13 @@ -From fd637f3c6c5a176a18cf44bbd163dd61cabd8fb1 Mon Sep 17 00:00:00 2001 +From 4d83ab44b211bd6c7e0c96e23de9f413f0927875 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Fri, 7 Aug 2015 23:58:28 -0500 -Subject: [PATCH 099/139] cpu/amd/family_10h-family_15h: Configure NB register +Subject: [PATCH 101/143] cpu/amd/family_10h-family_15h: Configure NB register 2 Change-Id: I55cfc96a197514212b2a4c344d3513396ebc2ad4 Signed-off-by: Timothy Pearson --- - src/cpu/amd/family_10h-family_15h/defaults.h | 8 ++++++++ + src/cpu/amd/family_10h-family_15h/defaults.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/cpu/amd/family_10h-family_15h/defaults.h b/src/cpu/amd/family_10h-family_15h/defaults.h @@ -30,5 +30,5 @@ index 4868c5c..5ab4335 100644 * System software should set F3x188[22] to 1b. */ { 3, 0x188, AMD_DR_Cx, AMD_PTYPE_ALL, -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0100-cpu-amd-family_10h-family_15h-Set-up-link-XCS-token-.patch b/resources/libreboot/patch/kgpe-d16/0102-cpu-amd-family_10h-family_15h-Set-up-link-XCS-token-.patch index d37c376..086b9e4 100644 --- a/resources/libreboot/patch/kgpe-d16/0100-cpu-amd-family_10h-family_15h-Set-up-link-XCS-token-.patch +++ b/resources/libreboot/patch/kgpe-d16/0102-cpu-amd-family_10h-family_15h-Set-up-link-XCS-token-.patch @@ -1,20 +1,20 @@ -From e1db05e5568333c634db8052d4dc37d60b61121f Mon Sep 17 00:00:00 2001 +From 89f102b6b680c94a31ff812bba7be5016e15580a Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Fri, 7 Aug 2015 23:59:17 -0500 -Subject: [PATCH 100/139] cpu/amd/family_10h-family_15h: Set up link XCS token +Subject: [PATCH 102/143] cpu/amd/family_10h-family_15h: Set up link XCS token counts on Family 15h Change-Id: I4cf6549234041c395a18a89332d95f20a596fc3e Signed-off-by: Timothy Pearson --- - src/cpu/amd/family_10h-family_15h/init_cpus.c | 304 ++++++++++++++++++++++++++ + src/cpu/amd/family_10h-family_15h/init_cpus.c | 304 +++++++++++++++++++++++++ 1 file changed, 304 insertions(+) diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c -index d1a93e7..10c676f 100644 +index 67893ca1..e93c15b 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c -@@ -1056,6 +1056,12 @@ static void cpuSetAMDPCI(u8 node) +@@ -1057,6 +1057,12 @@ static void cpuSetAMDPCI(u8 node) uint32_t dword; uint64_t revision; @@ -27,7 +27,7 @@ index d1a93e7..10c676f 100644 printk(BIOS_DEBUG, "cpuSetAMDPCI %02d", node); revision = mctGetLogicalCPUID(node); -@@ -1162,6 +1168,15 @@ static void cpuSetAMDPCI(u8 node) +@@ -1163,6 +1169,15 @@ static void cpuSetAMDPCI(u8 node) uint8_t compute_unit_count = 0; uint8_t compute_unit_buffer_count; @@ -43,7 +43,7 @@ index d1a93e7..10c676f 100644 /* Determine the number of active compute units on this node */ f5x80 = pci_read_config32(NODE_PCI(node, 5), 0x80); cu_enabled = f5x80 & 0xf; -@@ -1187,6 +1202,295 @@ static void cpuSetAMDPCI(u8 node) +@@ -1188,6 +1203,295 @@ static void cpuSetAMDPCI(u8 node) dword &= ~(0x1f << 4); /* L3FreeListCBC = compute_unit_buffer_count */ dword |= (compute_unit_buffer_count << 4); pci_write_config32(NODE_PCI(node, 3), 0x1a0, dword); @@ -340,5 +340,5 @@ index d1a93e7..10c676f 100644 printk(BIOS_DEBUG, " done\n"); -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0101-northbridge-amd-amdmct-mct_ddr3-Force-retraining-on-.patch b/resources/libreboot/patch/kgpe-d16/0103-northbridge-amd-amdmct-mct_ddr3-Force-retraining-on-.patch index ef1533d..16413ff 100644 --- a/resources/libreboot/patch/kgpe-d16/0101-northbridge-amd-amdmct-mct_ddr3-Force-retraining-on-.patch +++ b/resources/libreboot/patch/kgpe-d16/0103-northbridge-amd-amdmct-mct_ddr3-Force-retraining-on-.patch @@ -1,13 +1,13 @@ -From bb67f00d05bf8ff2d9643100878e3743302d43c1 Mon Sep 17 00:00:00 2001 +From d43547a64111da6fb4cba322c8675176bddf8622 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Fri, 7 Aug 2015 23:59:33 -0500 -Subject: [PATCH 101/139] northbridge/amd/amdmct/mct_ddr3: Force retraining on +Subject: [PATCH 103/143] northbridge/amd/amdmct/mct_ddr3: Force retraining on every boot Change-Id: I017e0dd5120110124d5b5d5276befef6f7740614 Signed-off-by: Timothy Pearson --- - src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 10 ++++++++++ + src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -32,5 +32,5 @@ index 2ca65ca..330f37f 100644 struct DCTStatStruc *pDCTstat; pDCTstat = pDCTstatA + Node; -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0102-northbridge-amd-amdfam10-Fix-invalid-NUMA-table.patch b/resources/libreboot/patch/kgpe-d16/0104-northbridge-amd-amdfam10-Fix-invalid-NUMA-table.patch index a1d226e..273fe30 100644 --- a/resources/libreboot/patch/kgpe-d16/0102-northbridge-amd-amdfam10-Fix-invalid-NUMA-table.patch +++ b/resources/libreboot/patch/kgpe-d16/0104-northbridge-amd-amdfam10-Fix-invalid-NUMA-table.patch @@ -1,12 +1,12 @@ -From 26dce9855e0edd8faae94f12d81ed59322d318ae Mon Sep 17 00:00:00 2001 +From 9b2c0953c5b51968d3ec9a41585196adb743a177 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sat, 8 Aug 2015 02:40:58 -0500 -Subject: [PATCH 102/139] northbridge/amd/amdfam10: Fix invalid NUMA table +Subject: [PATCH 104/143] northbridge/amd/amdfam10: Fix invalid NUMA table Change-Id: I99c200382b52a99687daf266a84873d9ae2df025 Signed-off-by: Timothy Pearson --- - src/northbridge/amd/amdfam10/acpi.c | 3 ++- + src/northbridge/amd/amdfam10/acpi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/northbridge/amd/amdfam10/acpi.c b/src/northbridge/amd/amdfam10/acpi.c @@ -24,5 +24,5 @@ index 92433bb..23cf086 100644 static unsigned long acpi_fill_srat(unsigned long current) -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0103-northbridge-amd-amdfam10-Add-Family-15h-cache-partit.patch b/resources/libreboot/patch/kgpe-d16/0105-northbridge-amd-amdfam10-Add-Family-15h-cache-partit.patch index 15836d4..c75a505 100644 --- a/resources/libreboot/patch/kgpe-d16/0103-northbridge-amd-amdfam10-Add-Family-15h-cache-partit.patch +++ b/resources/libreboot/patch/kgpe-d16/0105-northbridge-amd-amdfam10-Add-Family-15h-cache-partit.patch @@ -1,17 +1,17 @@ -From 1f667d55b99e81e636572d9f3ac9498ef782536c Mon Sep 17 00:00:00 2001 +From 87e62122ea2d2ee8c540be8694d90e182b71ea01 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sat, 8 Aug 2015 20:29:27 -0500 -Subject: [PATCH 103/139] northbridge/amd/amdfam10: Add Family 15h cache +Subject: [PATCH 105/143] northbridge/amd/amdfam10: Add Family 15h cache partitioning support Change-Id: Ie4e28dd886aaa1c586b0919c5fe87ef1696f47e9 Signed-off-by: Timothy Pearson --- - src/northbridge/amd/amdfam10/northbridge.c | 94 ++++++++++++++++++++++++++++++ + src/northbridge/amd/amdfam10/northbridge.c | 94 ++++++++++++++++++++++++++++ 1 file changed, 94 insertions(+) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c -index 9f132c7..8ad5200 100644 +index 3a899c8..4826ea4 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -1809,9 +1809,103 @@ static void detect_and_enable_probe_filter(device_t dev) @@ -119,5 +119,5 @@ index 9f132c7..8ad5200 100644 #if CONFIG_AMD_SB_CIMX sb_After_Pci_Init(); -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0104-amd-amdmct-mct_ddr3-Set-prefetch-double-stride-to-im.patch b/resources/libreboot/patch/kgpe-d16/0106-amd-amdmct-mct_ddr3-Set-prefetch-double-stride-to-im.patch index 829e470..2cf8048 100644 --- a/resources/libreboot/patch/kgpe-d16/0104-amd-amdmct-mct_ddr3-Set-prefetch-double-stride-to-im.patch +++ b/resources/libreboot/patch/kgpe-d16/0106-amd-amdmct-mct_ddr3-Set-prefetch-double-stride-to-im.patch @@ -1,13 +1,13 @@ -From bcdb6fab80939ee9b9d599343460edcb31fd386f Mon Sep 17 00:00:00 2001 +From ea9a0276634c0d2ddfdcbe75e350416568453dae Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sat, 8 Aug 2015 20:29:55 -0500 -Subject: [PATCH 104/139] amd/amdmct/mct_ddr3: Set prefetch double stride to +Subject: [PATCH 106/143] amd/amdmct/mct_ddr3: Set prefetch double stride to improve performance Change-Id: I34ad85388c6b71f0d44bee13afd663e0b84545cd Signed-off-by: Timothy Pearson --- - src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 1 + + src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -23,5 +23,5 @@ index 330f37f..de6c79c 100644 val |= (0x7 << 25); /* PrefFiveConf = 0x7 */ val &= ~(0xf << 28); /* DcqBwThrotWm = 0x0 */ -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0105-cpu-amd-family_10h-family_15h-Set-up-Family-15h-Link.patch b/resources/libreboot/patch/kgpe-d16/0107-cpu-amd-family_10h-family_15h-Set-up-Family-15h-Link.patch index bcf7c48..e11a27d 100644 --- a/resources/libreboot/patch/kgpe-d16/0105-cpu-amd-family_10h-family_15h-Set-up-Family-15h-Link.patch +++ b/resources/libreboot/patch/kgpe-d16/0107-cpu-amd-family_10h-family_15h-Set-up-Family-15h-Link.patch @@ -1,20 +1,20 @@ -From 442969b0213becab817ad626597c1c7eeaf15ebc Mon Sep 17 00:00:00 2001 +From 9e1d2f70fb0e1d50c2314072b7fb019ed7cd283e Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sat, 8 Aug 2015 20:30:36 -0500 -Subject: [PATCH 105/139] cpu/amd/family_10h-family_15h: Set up Family 15h Link - Base Channel Buffer Count registers +Subject: [PATCH 107/143] cpu/amd/family_10h-family_15h: Set up Family 15h + Link Base Channel Buffer Count registers Change-Id: I8d616a64a5a9cf0b51288535f5050c6866d0996b Signed-off-by: Timothy Pearson --- - src/cpu/amd/family_10h-family_15h/init_cpus.c | 159 +++++++++++++++++++++++++- + src/cpu/amd/family_10h-family_15h/init_cpus.c | 159 ++++++++++++++++++++++++- 1 file changed, 155 insertions(+), 4 deletions(-) diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c -index 10c676f..63ad346 100644 +index e93c15b..59d745d 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c -@@ -1203,6 +1203,161 @@ static void cpuSetAMDPCI(u8 node) +@@ -1204,6 +1204,161 @@ static void cpuSetAMDPCI(u8 node) dword |= (compute_unit_buffer_count << 4); pci_write_config32(NODE_PCI(node, 3), 0x1a0, dword); @@ -176,7 +176,7 @@ index 10c676f..63ad346 100644 /* Set up the Link to XCS Token Counts */ uint8_t isoc_rsp_tok_1; uint8_t isoc_preq_tok_1; -@@ -1220,10 +1375,6 @@ static void cpuSetAMDPCI(u8 node) +@@ -1221,10 +1376,6 @@ static void cpuSetAMDPCI(u8 node) uint8_t preq_tok_0; uint8_t req_tok_0; @@ -188,5 +188,5 @@ index 10c676f..63ad346 100644 if (AMD_CpuFindCapability(node, link, &offset)) { ganged = !!(pci_read_config32(NODE_PCI(node, 0), (link << 2) + 0x170) & 0x1); -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0106-cpu-amd-family_10h-family_15h-Set-up-cache-controls-.patch b/resources/libreboot/patch/kgpe-d16/0108-cpu-amd-family_10h-family_15h-Set-up-cache-controls-.patch index 8cfb82c..5573e0e 100644 --- a/resources/libreboot/patch/kgpe-d16/0106-cpu-amd-family_10h-family_15h-Set-up-cache-controls-.patch +++ b/resources/libreboot/patch/kgpe-d16/0108-cpu-amd-family_10h-family_15h-Set-up-cache-controls-.patch @@ -1,13 +1,13 @@ -From c4c97a2bf72bf0547a6c587a7096620a0e28773d Mon Sep 17 00:00:00 2001 +From acf2af4d866e51afce92092adf240c72d7193757 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sat, 8 Aug 2015 20:31:03 -0500 -Subject: [PATCH 106/139] cpu/amd/family_10h-family_15h: Set up cache controls +Subject: [PATCH 108/143] cpu/amd/family_10h-family_15h: Set up cache controls on Family 15h to improve performance Change-Id: I3df571d8091c07ac1ee29bf16b5a68585fa9eed4 Signed-off-by: Timothy Pearson --- - src/cpu/amd/family_10h-family_15h/defaults.h | 10 ++++++++-- + src/cpu/amd/family_10h-family_15h/defaults.h | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/src/cpu/amd/family_10h-family_15h/defaults.h b/src/cpu/amd/family_10h-family_15h/defaults.h @@ -39,5 +39,5 @@ index 5ab4335..ce25b25 100644 -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0107-cpu-amd-family_10h-family_15h-Set-up-SRI-to-XCS-Toke.patch b/resources/libreboot/patch/kgpe-d16/0109-cpu-amd-family_10h-family_15h-Set-up-SRI-to-XCS-Toke.patch index 6d2c7e6..79e297e 100644 --- a/resources/libreboot/patch/kgpe-d16/0107-cpu-amd-family_10h-family_15h-Set-up-SRI-to-XCS-Toke.patch +++ b/resources/libreboot/patch/kgpe-d16/0109-cpu-amd-family_10h-family_15h-Set-up-SRI-to-XCS-Toke.patch @@ -1,20 +1,20 @@ -From abac0edc90bff68cf30b60096c0db5214d8ef7f9 Mon Sep 17 00:00:00 2001 +From 6e4bf582d1d1cf515f1dec738e02bb7e123ac227 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sat, 8 Aug 2015 22:14:59 -0500 -Subject: [PATCH 107/139] cpu/amd/family_10h-family_15h: Set up SRI to XCS +Subject: [PATCH 109/143] cpu/amd/family_10h-family_15h: Set up SRI to XCS Token Count registers on Family 15h Change-Id: Ic992efad11d8e231ec85c793cf1e478bea0b9d3e Signed-off-by: Timothy Pearson --- - src/cpu/amd/family_10h-family_15h/init_cpus.c | 40 +++++++++++++++++++++++++++ + src/cpu/amd/family_10h-family_15h/init_cpus.c | 40 +++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c -index 63ad346..115338e 100644 +index 59d745d..f4254f0 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c -@@ -1642,6 +1642,46 @@ static void cpuSetAMDPCI(u8 node) +@@ -1643,6 +1643,46 @@ static void cpuSetAMDPCI(u8 node) pci_write_config32(NODE_PCI(node, 3), (link << 2) + 0x148, dword); } } @@ -62,5 +62,5 @@ index 63ad346..115338e 100644 printk(BIOS_DEBUG, " done\n"); -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0108-amd-amdfam10-Control-Family-15h-cache-partitioning-a.patch b/resources/libreboot/patch/kgpe-d16/0110-amd-amdfam10-Control-Family-15h-cache-partitioning-a.patch index b160d2b..b35a0c5 100644 --- a/resources/libreboot/patch/kgpe-d16/0108-amd-amdfam10-Control-Family-15h-cache-partitioning-a.patch +++ b/resources/libreboot/patch/kgpe-d16/0110-amd-amdfam10-Control-Family-15h-cache-partitioning-a.patch @@ -1,19 +1,19 @@ -From 4e4d10b69d13a3b15065bb2ee8f8c9b6a7d9ac89 Mon Sep 17 00:00:00 2001 +From ce44752d64232ea61ffa8747ffe0883229bd7df6 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sun, 9 Aug 2015 02:47:51 -0500 -Subject: [PATCH 108/139] amd/amdfam10: Control Family 15h cache partitioning +Subject: [PATCH 110/143] amd/amdfam10: Control Family 15h cache partitioning and memory performance via nvram Change-Id: I3dd5d7f3640aee0395a68645c0242307605d3ce7 Signed-off-by: Timothy Pearson --- - src/cpu/amd/family_10h-family_15h/defaults.h | 5 ++--- - src/cpu/amd/family_10h-family_15h/init_cpus.c | 13 +++++++++++++ - src/mainboard/asus/kgpe-d16/cmos.default | 3 +++ - src/mainboard/asus/kgpe-d16/cmos.layout | 9 +++++++-- - src/northbridge/amd/amdfam10/northbridge.c | 22 ++++++++++++++++++++++ - src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 11 ++++++++++- - 6 files changed, 57 insertions(+), 6 deletions(-) + src/cpu/amd/family_10h-family_15h/defaults.h | 5 ++--- + src/cpu/amd/family_10h-family_15h/init_cpus.c | 16 ++++++++++++++-- + src/mainboard/asus/kgpe-d16/cmos.default | 3 +++ + src/mainboard/asus/kgpe-d16/cmos.layout | 9 +++++++-- + src/northbridge/amd/amdfam10/northbridge.c | 22 ++++++++++++++++++++++ + src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 11 ++++++++++- + 6 files changed, 58 insertions(+), 8 deletions(-) diff --git a/src/cpu/amd/family_10h-family_15h/defaults.h b/src/cpu/amd/family_10h-family_15h/defaults.h index ce25b25..af59120 100644 @@ -32,10 +32,18 @@ index ce25b25..af59120 100644 { EX_CFG, AMD_OR_C0, AMD_PTYPE_ALL, 0x00000000, 1 << (54-32), diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c -index 115338e..2234197 100644 +index f4254f0..7dffcc0 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c -@@ -981,6 +981,13 @@ void cpuSetAMDMSR(uint8_t node_id) +@@ -956,6 +956,7 @@ void cpuSetAMDMSR(uint8_t node_id) + */ + msr_t msr; + u8 i; ++ uint8_t nvram; + u32 platform; + uint64_t revision; + uint8_t enable_c_states; +@@ -980,6 +981,13 @@ void cpuSetAMDMSR(uint8_t node_id) /* Revision C0 and above */ if (revision & AMD_OR_C0) { @@ -49,7 +57,7 @@ index 115338e..2234197 100644 uint32_t f3x1fc = pci_read_config32(NODE_PCI(node_id, 3), 0x1fc); msr = rdmsr(FP_CFG); msr.hi &= ~(0x7 << (42-32)); /* DiDtCfg4 */ -@@ -1000,6 +1007,12 @@ void cpuSetAMDMSR(uint8_t node_id) +@@ -999,11 +1007,15 @@ void cpuSetAMDMSR(uint8_t node_id) msr.lo &= ~(0x1 << 16); /* DiDtMode */ msr.lo |= ((f3x1fc & 0x1) << 16); wrmsr(FP_CFG, msr); @@ -62,6 +70,11 @@ index 115338e..2234197 100644 } #if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB800) +- uint8_t nvram; +- + if (revision & (AMD_DR_GT_D0 | AMD_FAM15_ALL)) { + /* Set up message triggered C1E */ + msr = rdmsr(0xc0010055); diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default index 9b30b00..0a898bd 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.default @@ -104,7 +117,7 @@ index ec803b6..010d4db 100644 checksums diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c -index 8ad5200..58b0079 100644 +index 4826ea4..740fd79 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -1654,6 +1654,17 @@ static void detect_and_enable_probe_filter(device_t dev) @@ -173,5 +186,5 @@ index de6c79c..42630b9 100644 val |= (0x7 << 25); /* PrefFiveConf = 0x7 */ val &= ~(0xf << 28); /* DcqBwThrotWm = 0x0 */ -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0109-northbridge-amd-amdht-Add-isochronous-setup-support-.patch b/resources/libreboot/patch/kgpe-d16/0111-northbridge-amd-amdht-Add-isochronous-setup-support-.patch index f4d5b49..f57dbdf 100644 --- a/resources/libreboot/patch/kgpe-d16/0109-northbridge-amd-amdht-Add-isochronous-setup-support-.patch +++ b/resources/libreboot/patch/kgpe-d16/0111-northbridge-amd-amdht-Add-isochronous-setup-support-.patch @@ -1,24 +1,24 @@ -From e94372dfb597ff2d28047e5d63d22ee33e1db0c7 Mon Sep 17 00:00:00 2001 +From c6a6d7b4fc613a18511d8aeb0040a350d61920e7 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Tue, 11 Aug 2015 17:47:48 -0500 -Subject: [PATCH 109/139] northbridge/amd/amdht: Add isochronous setup support +Subject: [PATCH 111/143] northbridge/amd/amdht: Add isochronous setup support for coherent fabric Change-Id: Idd7c9b94a65f856b0059e1d45f8719d9475771b6 Signed-off-by: Timothy Pearson --- - src/cpu/amd/family_10h-family_15h/init_cpus.c | 59 +++++++++++++++++++++++++++ - src/northbridge/amd/amdht/h3ffeat.h | 3 ++ - src/northbridge/amd/amdht/h3finit.c | 34 ++++++++++++++- - src/northbridge/amd/amdht/h3finit.h | 4 +- - src/northbridge/amd/amdht/h3ncmn.c | 26 +++++++++++- - 5 files changed, 122 insertions(+), 4 deletions(-) + src/cpu/amd/family_10h-family_15h/init_cpus.c | 61 +++++++++++++++++++++++++ + src/northbridge/amd/amdht/h3ffeat.h | 3 ++ + src/northbridge/amd/amdht/h3finit.c | 35 +++++++++++++- + src/northbridge/amd/amdht/h3finit.h | 4 +- + src/northbridge/amd/amdht/h3ncmn.c | 30 +++++++++++- + 5 files changed, 129 insertions(+), 4 deletions(-) diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c -index 2234197..7a0701c 100644 +index 7dffcc0..da6424f 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c -@@ -1697,6 +1697,65 @@ static void cpuSetAMDPCI(u8 node) +@@ -1697,6 +1697,67 @@ static void cpuSetAMDPCI(u8 node) pci_write_config32(NODE_PCI(node, 3), 0x140, dword); } @@ -28,12 +28,14 @@ index 2234197..7a0701c 100644 + + /* Set up isochronous buffers if needed */ + isochronous_link_present = 0; -+ for (link = 0; link < 4; link++) { -+ if (AMD_CpuFindCapability(node, link, &offset)) { -+ isochronous = (pci_read_config32(NODE_PCI(node, 0), (link * 0x20) + 0x84) >> 12) & 0x1; ++ if (revision & AMD_FAM15_ALL) { ++ for (link = 0; link < 4; link++) { ++ if (AMD_CpuFindCapability(node, link, &offset)) { ++ isochronous = (pci_read_config32(NODE_PCI(node, 0), (link * 0x20) + 0x84) >> 12) & 0x1; + -+ if (isochronous) -+ isochronous_link_present = 1; ++ if (isochronous) ++ isochronous_link_present = 1; ++ } + } + } + @@ -110,7 +112,7 @@ index 5dc9916..c523b12 100644 u8 PrvWidthOutCap; uint32_t CompositeFrequencyCap; diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c -index 14f348f..9d1e7d7 100644 +index 14f348f..6b53d34 100644 --- a/src/northbridge/amd/amdht/h3finit.c +++ b/src/northbridge/amd/amdht/h3finit.c @@ -1419,6 +1419,38 @@ static void regangLinks(sMainData *pDat) @@ -160,11 +162,12 @@ index 14f348f..9d1e7d7 100644 } } -@@ -1701,6 +1732,7 @@ static void linkOptimization(sMainData *pDat) +@@ -1701,6 +1732,8 @@ static void linkOptimization(sMainData *pDat) { pDat->nb->gatherLinkData(pDat, pDat->nb); regangLinks(pDat); -+ detectIoLinkIsochronousCapable(pDat); ++ if (is_fam15h()) ++ detectIoLinkIsochronousCapable(pDat); selectOptimalWidthAndFrequency(pDat); hammerSublinkFixup(pDat); pDat->nb->setLinkData(pDat, pDat->nb); @@ -191,7 +194,7 @@ index 462f3e3..eef8fe7 100644 /**---------------------------------------------------------------------------------------- diff --git a/src/northbridge/amd/amdht/h3ncmn.c b/src/northbridge/amd/amdht/h3ncmn.c -index e377ff2..841fc0c 100644 +index e377ff2..369ce3e 100644 --- a/src/northbridge/amd/amdht/h3ncmn.c +++ b/src/northbridge/amd/amdht/h3ncmn.c @@ -1433,12 +1433,15 @@ static void gatherLinkData(sMainData *pDat, cNorthBridge *nb) @@ -231,22 +234,24 @@ index e377ff2..841fc0c 100644 } } } -@@ -1566,6 +1573,14 @@ static void setLinkData(sMainData *pDat, cNorthBridge *nb) +@@ -1566,6 +1573,16 @@ static void setLinkData(sMainData *pDat, cNorthBridge *nb) if (is_gt_rev_d()) AmdPCIWriteBits(linkBase + HTHOST_FREQ_REV_REG_2, 0, 0, &temp2); AmdPCIWriteBits(linkBase + HTHOST_FREQ_REV_REG, 11, 8, &temp); + + /* Enable isochronous flow control mode if supported by chipset */ -+ if (pDat->PortList[i].enable_isochronous_mode) -+ temp = 1; -+ else -+ temp = 0; -+ setHtControlRegisterBits(linkBase + HTHOST_LINK_CONTROL_REG, 12, 12, &temp); ++ if (is_fam15h()) { ++ if (pDat->PortList[i].enable_isochronous_mode) ++ temp = 1; ++ else ++ temp = 0; ++ setHtControlRegisterBits(linkBase + HTHOST_LINK_CONTROL_REG, 12, 12, &temp); ++ } + if (frequency_index > HT_FREQUENCY_1000M) /* Gen1 = 200MHz -> 1000MHz, Gen3 = 1200MHz -> 3200MHz */ { /* Enable for Gen3 frequencies */ -@@ -1583,6 +1598,7 @@ static void setLinkData(sMainData *pDat, cNorthBridge *nb) +@@ -1583,6 +1600,7 @@ static void setLinkData(sMainData *pDat, cNorthBridge *nb) CPU_HTNB_FUNC_00, REG_HT_LINK_RETRY0_0X130 + 4*pDat->PortList[i].Link), 0, 0, &temp); @@ -254,19 +259,21 @@ index e377ff2..841fc0c 100644 /* and Scrambling enable / disable */ AmdPCIWriteBits(MAKE_SBDFO(makePCISegmentFromNode(pDat->PortList[i].NodeID), makePCIBusFromNode(pDat->PortList[i].NodeID), -@@ -1621,6 +1637,12 @@ static void setLinkData(sMainData *pDat, cNorthBridge *nb) +@@ -1621,6 +1639,14 @@ static void setLinkData(sMainData *pDat, cNorthBridge *nb) bits = 0; } + /* Enable isochronous flow control mode if supported by chipset */ -+ if (pDat->PortList[i].enable_isochronous_mode) -+ temp = 1; -+ else -+ temp = 0; ++ if (is_fam15h()) { ++ if (pDat->PortList[i].enable_isochronous_mode) ++ temp = 1; ++ else ++ temp = 0; ++ } + /* Retry Enable */ isFound = FALSE; currentPtr = linkBase & (u32)0xFFFFF000; /* Set PCI Offset to 0 */ -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0110-arch-x86-acpi-Add-IVRS-table-generation-routines.patch b/resources/libreboot/patch/kgpe-d16/0112-arch-x86-acpi-Add-IVRS-table-generation-routines.patch index ea7cd3a..dd83072 100644 --- a/resources/libreboot/patch/kgpe-d16/0110-arch-x86-acpi-Add-IVRS-table-generation-routines.patch +++ b/resources/libreboot/patch/kgpe-d16/0112-arch-x86-acpi-Add-IVRS-table-generation-routines.patch @@ -1,13 +1,13 @@ -From f84ae61b0b82097f318c96ee5c198cf9495568e2 Mon Sep 17 00:00:00 2001 +From 5152908b5fd0983ed36b2a5e35ebcf510cd31727 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Tue, 11 Aug 2015 17:48:32 -0500 -Subject: [PATCH 110/139] arch/x86/acpi: Add IVRS table generation routines +Subject: [PATCH 112/143] arch/x86/acpi: Add IVRS table generation routines Change-Id: Ia5d97d01dc9ddc45f81d998d126d592a915b4a75 Signed-off-by: Timothy Pearson --- - src/arch/x86/acpi.c | 25 +++++++++++++++++++++++++ - src/arch/x86/include/arch/acpi.h | 31 +++++++++++++++++++++++++++++++ + src/arch/x86/acpi.c | 25 +++++++++++++++++++++++++ + src/arch/x86/include/arch/acpi.h | 31 +++++++++++++++++++++++++++++++ 2 files changed, 56 insertions(+) diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c @@ -117,5 +117,5 @@ index 28f650c..7d583b8 100644 void acpi_create_hpet(acpi_hpet_t *hpet); unsigned long acpi_write_hpet(device_t device, unsigned long start, acpi_rsdp_t *rsdp); -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0111-southbridge-amd-sr5650-Add-IOMMU-support.patch b/resources/libreboot/patch/kgpe-d16/0113-southbridge-amd-sr5650-Add-IOMMU-support.patch index 54f04d0..959e57f 100644 --- a/resources/libreboot/patch/kgpe-d16/0111-southbridge-amd-sr5650-Add-IOMMU-support.patch +++ b/resources/libreboot/patch/kgpe-d16/0113-southbridge-amd-sr5650-Add-IOMMU-support.patch @@ -1,17 +1,19 @@ -From 274c926921dc0f24e15e09beed752f4927220fc6 Mon Sep 17 00:00:00 2001 +From f44168ba86f534ca12566ba7d38ff5f99c6c7e9c Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Tue, 11 Aug 2015 17:49:06 -0500 -Subject: [PATCH 111/139] southbridge/amd/sr5650: Add IOMMU support +Subject: [PATCH 113/143] southbridge/amd/sr5650: Add IOMMU support Change-Id: I2083d0c5653515c27d4626c62a6499b850f7547b Signed-off-by: Timothy Pearson --- - src/include/device/pci_ids.h | 1 + - src/southbridge/amd/sr5650/cmn.h | 3 + - src/southbridge/amd/sr5650/early_setup.c | 50 +++- - src/southbridge/amd/sr5650/sr5650.c | 479 ++++++++++++++++++++++++++++++- - src/southbridge/amd/sr5650/sr5650.h | 14 + - 5 files changed, 537 insertions(+), 10 deletions(-) + src/include/device/pci_ids.h | 1 + + src/mainboard/asus/kgpe-d16/acpi_tables.c | 37 ++ + src/mainboard/supermicro/h8scm_fam10/acpi_tables.c | 37 ++ + src/southbridge/amd/sr5650/cmn.h | 3 + + src/southbridge/amd/sr5650/early_setup.c | 50 +- + src/southbridge/amd/sr5650/sr5650.c | 479 +++++++++++++++++++- + src/southbridge/amd/sr5650/sr5650.h | 14 + + 7 files changed, 611 insertions(+), 10 deletions(-) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 664ac49..72f1ece 100644 @@ -25,6 +27,97 @@ index 664ac49..72f1ece 100644 #define PCI_DEVICE_ID_AMD_CZ_HDA 0x157A #define PCI_DEVICE_ID_AMD_CZ_LPC 0x790E +diff --git a/src/mainboard/asus/kgpe-d16/acpi_tables.c b/src/mainboard/asus/kgpe-d16/acpi_tables.c +index 4e98dfe..3f8650b 100644 +--- a/src/mainboard/asus/kgpe-d16/acpi_tables.c ++++ b/src/mainboard/asus/kgpe-d16/acpi_tables.c +@@ -73,3 +73,40 @@ unsigned long acpi_fill_madt(unsigned long current) + + return current; + } ++ ++unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t* ivrs, unsigned long current) ++{ ++ uint8_t *p; ++ ++ uint32_t apicid_sp5100; ++ uint32_t apicid_sr5650; ++ ++ apicid_sp5100 = 0x20; ++ apicid_sr5650 = apicid_sp5100 + 1; ++ ++ /* Describe NB IOAPIC */ ++ p = (uint8_t *)current; ++ p[0] = 0x48; /* Entry type */ ++ p[1] = 0; /* Device */ ++ p[2] = 0; /* Bus */ ++ p[3] = 0x0; /* Data */ ++ p[4] = apicid_sr5650; /* IOAPIC ID */ ++ p[5] = 0x1; /* Device 0 Function 1 */ ++ p[6] = 0x0; /* Northbridge bus */ ++ p[7] = 0x1; /* Variety */ ++ current += 8; ++ ++ /* Describe SB IOAPIC */ ++ p = (uint8_t *)current; ++ p[0] = 0x48; /* Entry type */ ++ p[1] = 0; /* Device */ ++ p[2] = 0; /* Bus */ ++ p[3] = 0xd7; /* Data */ ++ p[4] = apicid_sp5100; /* IOAPIC ID */ ++ p[5] = 0x14 << 3; /* Device 0x14 Function 0 */ ++ p[6] = 0x0; /* Southbridge bus */ ++ p[7] = 0x1; /* Variety */ ++ current += 8; ++ ++ return current; ++} +\ No newline at end of file +diff --git a/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c b/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c +index 61d16d7..14bd9ed 100644 +--- a/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c ++++ b/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c +@@ -66,3 +66,40 @@ unsigned long acpi_fill_madt(unsigned long current) + + return current; + } ++ ++unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t* ivrs, unsigned long current) ++{ ++ uint8_t *p; ++ ++ uint32_t apicid_sp5100; ++ uint32_t apicid_sr5650; ++ ++ apicid_sp5100 = 0x20; ++ apicid_sr5650 = apicid_sp5100 + 1; ++ ++ /* Describe NB IOAPIC */ ++ p = (uint8_t *)current; ++ p[0] = 0x48; /* Entry type */ ++ p[1] = 0; /* Device */ ++ p[2] = 0; /* Bus */ ++ p[3] = 0x0; /* Data */ ++ p[4] = apicid_sr5650; /* IOAPIC ID */ ++ p[5] = 0x1; /* Device 0 Function 1 */ ++ p[6] = 0x0; /* Northbridge bus */ ++ p[7] = 0x1; /* Variety */ ++ current += 8; ++ ++ /* Describe SB IOAPIC */ ++ p = (uint8_t *)current; ++ p[0] = 0x48; /* Entry type */ ++ p[1] = 0; /* Device */ ++ p[2] = 0; /* Bus */ ++ p[3] = 0xd7; /* Data */ ++ p[4] = apicid_sp5100; /* IOAPIC ID */ ++ p[5] = 0x14 << 3; /* Device 0x14 Function 0 */ ++ p[6] = 0x0; /* Southbridge bus */ ++ p[7] = 0x1; /* Variety */ ++ current += 8; ++ ++ return current; ++} diff --git a/src/southbridge/amd/sr5650/cmn.h b/src/southbridge/amd/sr5650/cmn.h index 23d25d5..a54bdc5 100644 --- a/src/southbridge/amd/sr5650/cmn.h @@ -707,5 +800,5 @@ index ebbde41..a3518fb 100644 void init_gen2(device_t nb_dev, device_t dev, u8 port); void sr56x0_lock_hwinitreg(void); -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0112-southbridge-amd-sr5650-Hide-clock-configuration-devi.patch b/resources/libreboot/patch/kgpe-d16/0114-southbridge-amd-sr5650-Hide-clock-configuration-devi.patch index a20b748..42cebaf 100644 --- a/resources/libreboot/patch/kgpe-d16/0112-southbridge-amd-sr5650-Hide-clock-configuration-devi.patch +++ b/resources/libreboot/patch/kgpe-d16/0114-southbridge-amd-sr5650-Hide-clock-configuration-devi.patch @@ -1,14 +1,14 @@ -From 95976a8660ad2acc7f4aca0665b195e53c53840c Mon Sep 17 00:00:00 2001 +From 2976a30c045a1c525095d8a954f26174fbdc532c Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Thu, 13 Aug 2015 17:45:12 -0500 -Subject: [PATCH 112/139] southbridge/amd/sr5650: Hide clock configuration +Subject: [PATCH 114/143] southbridge/amd/sr5650: Hide clock configuration device after setup is complete Change-Id: I043f2eb0993660d0a9351867eca1e73e0b2c37f1 Signed-off-by: Timothy Pearson --- - src/southbridge/amd/sr5650/early_setup.c | 16 ++++++++-------- - src/southbridge/amd/sr5650/pcie.c | 3 +++ + src/southbridge/amd/sr5650/early_setup.c | 16 ++++++++-------- + src/southbridge/amd/sr5650/pcie.c | 3 +++ 2 files changed, 11 insertions(+), 8 deletions(-) diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c @@ -53,5 +53,5 @@ index 09ce217..360e9cb 100644 /***************************************** -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0113-northbridge-amd-amdfam10-Rename-mislabeled-iommu-nvr.patch b/resources/libreboot/patch/kgpe-d16/0115-northbridge-amd-amdfam10-Rename-mislabeled-iommu-nvr.patch index 9e1a042..165f6b3 100644 --- a/resources/libreboot/patch/kgpe-d16/0113-northbridge-amd-amdfam10-Rename-mislabeled-iommu-nvr.patch +++ b/resources/libreboot/patch/kgpe-d16/0115-northbridge-amd-amdfam10-Rename-mislabeled-iommu-nvr.patch @@ -1,13 +1,13 @@ -From 6fc24c6bf44b8ea2ad3ca43856500500aa0ffee7 Mon Sep 17 00:00:00 2001 +From da60f9b49a5323832cad7cb33d97f29776aaf9e8 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Tue, 11 Aug 2015 17:52:03 -0500 -Subject: [PATCH 113/139] northbridge/amd/amdfam10: Rename mislabeled iommu +Subject: [PATCH 115/143] northbridge/amd/amdfam10: Rename mislabeled iommu nvram option to gart Change-Id: Ia24102e164eb5753ade3f9b5ab21eba2fa60836b Signed-off-by: Timothy Pearson --- - src/northbridge/amd/amdfam10/misc_control.c | 12 ++++++------ + src/northbridge/amd/amdfam10/misc_control.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c @@ -51,5 +51,5 @@ index 703ae51..1df570c 100644 resource->gran = log2(resource->size); resource->limit = 0xffffffff; /* 4G */ -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0114-northbridge-amd-amdfam10-Fix-gart-setup-not-working-.patch b/resources/libreboot/patch/kgpe-d16/0116-northbridge-amd-amdfam10-Fix-gart-setup-not-working-.patch index e7f0b9e..9650d95 100644 --- a/resources/libreboot/patch/kgpe-d16/0114-northbridge-amd-amdfam10-Fix-gart-setup-not-working-.patch +++ b/resources/libreboot/patch/kgpe-d16/0116-northbridge-amd-amdfam10-Fix-gart-setup-not-working-.patch @@ -1,13 +1,13 @@ -From 215348b2c83c3f1464b0c4d318e5ff6318d82a02 Mon Sep 17 00:00:00 2001 +From 251ec37bd76462397fbda9d644c665720e5c4a2d Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Tue, 11 Aug 2015 17:52:31 -0500 -Subject: [PATCH 114/139] northbridge/amd/amdfam10: Fix gart setup not working +Subject: [PATCH 116/143] northbridge/amd/amdfam10: Fix gart setup not working on Family 15h processors Change-Id: Ib78620c30502df6add9cc2ea1dbd4fb6dc89203e Signed-off-by: Timothy Pearson --- - src/northbridge/amd/amdfam10/misc_control.c | 34 ++++++++++++++++++++++------- + src/northbridge/amd/amdfam10/misc_control.c | 34 ++++++++++++++++++++------- 1 file changed, 26 insertions(+), 8 deletions(-) diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c @@ -92,5 +92,5 @@ index 1df570c..4b62c69 100644 .device = 0x1603, }; -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0115-mainboard-asus-kgpe-d16-Add-several-nvram-configurat.patch b/resources/libreboot/patch/kgpe-d16/0117-mainboard-asus-kgpe-d16-Add-several-nvram-configurat.patch index ba0f218..e652fbd 100644 --- a/resources/libreboot/patch/kgpe-d16/0115-mainboard-asus-kgpe-d16-Add-several-nvram-configurat.patch +++ b/resources/libreboot/patch/kgpe-d16/0117-mainboard-asus-kgpe-d16-Add-several-nvram-configurat.patch @@ -1,65 +1,18 @@ -From 7b3c144695ecc58a7bfc35215fd2933aea0051e1 Mon Sep 17 00:00:00 2001 +From f5f3af0a03970b6d96a0a83985ae20e242379278 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Tue, 11 Aug 2015 17:53:45 -0500 -Subject: [PATCH 115/139] mainboard/asus/kgpe-d16: Add several nvram +Subject: [PATCH 117/143] mainboard/asus/kgpe-d16: Add several nvram configuration options Change-Id: I45b04e8fbdfc65603e1057f7b0e5a13d073fe348 Signed-off-by: Timothy Pearson --- - src/mainboard/asus/kgpe-d16/acpi_tables.c | 37 +++++++++++++++++++++++++++++++ - src/mainboard/asus/kgpe-d16/cmos.default | 3 ++- - src/mainboard/asus/kgpe-d16/cmos.layout | 7 +++--- - src/mainboard/asus/kgpe-d16/devicetree.cb | 1 + - src/mainboard/asus/kgpe-d16/romstage.c | 2 ++ - 5 files changed, 46 insertions(+), 4 deletions(-) + src/mainboard/asus/kgpe-d16/cmos.default | 3 ++- + src/mainboard/asus/kgpe-d16/cmos.layout | 7 ++++--- + src/mainboard/asus/kgpe-d16/devicetree.cb | 1 + + src/mainboard/asus/kgpe-d16/romstage.c | 2 ++ + 4 files changed, 9 insertions(+), 4 deletions(-) -diff --git a/src/mainboard/asus/kgpe-d16/acpi_tables.c b/src/mainboard/asus/kgpe-d16/acpi_tables.c -index 4e98dfe..3f8650b 100644 ---- a/src/mainboard/asus/kgpe-d16/acpi_tables.c -+++ b/src/mainboard/asus/kgpe-d16/acpi_tables.c -@@ -73,3 +73,40 @@ unsigned long acpi_fill_madt(unsigned long current) - - return current; - } -+ -+unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t* ivrs, unsigned long current) -+{ -+ uint8_t *p; -+ -+ uint32_t apicid_sp5100; -+ uint32_t apicid_sr5650; -+ -+ apicid_sp5100 = 0x20; -+ apicid_sr5650 = apicid_sp5100 + 1; -+ -+ /* Describe NB IOAPIC */ -+ p = (uint8_t *)current; -+ p[0] = 0x48; /* Entry type */ -+ p[1] = 0; /* Device */ -+ p[2] = 0; /* Bus */ -+ p[3] = 0x0; /* Data */ -+ p[4] = apicid_sr5650; /* IOAPIC ID */ -+ p[5] = 0x1; /* Device 0 Function 1 */ -+ p[6] = 0x0; /* Northbridge bus */ -+ p[7] = 0x1; /* Variety */ -+ current += 8; -+ -+ /* Describe SB IOAPIC */ -+ p = (uint8_t *)current; -+ p[0] = 0x48; /* Entry type */ -+ p[1] = 0; /* Device */ -+ p[2] = 0; /* Bus */ -+ p[3] = 0xd7; /* Data */ -+ p[4] = apicid_sp5100; /* IOAPIC ID */ -+ p[5] = 0x14 << 3; /* Device 0x14 Function 0 */ -+ p[6] = 0x0; /* Southbridge bus */ -+ p[7] = 0x1; /* Variety */ -+ current += 8; -+ -+ return current; -+} -\ No newline at end of file diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default index 0a898bd..83c1fe8 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.default @@ -100,7 +53,7 @@ index 010d4db..310b7b1 100644 984 16 h 0 check_sum # Reserve the extended AMD configuration registers diff --git a/src/mainboard/asus/kgpe-d16/devicetree.cb b/src/mainboard/asus/kgpe-d16/devicetree.cb -index ada268b..f87efc6 100644 +index 8eeb33e..8b35201 100644 --- a/src/mainboard/asus/kgpe-d16/devicetree.cb +++ b/src/mainboard/asus/kgpe-d16/devicetree.cb @@ -15,6 +15,7 @@ chip northbridge/amd/amdfam10/root_complex # Root complex @@ -112,7 +65,7 @@ index ada268b..f87efc6 100644 # Slot # PCI E 1 / PCI E 2 end diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c -index 2b222f5..fa61f63 100644 +index 5d4005d..cbda9ca 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -459,6 +459,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) @@ -125,5 +78,5 @@ index 2b222f5..fa61f63 100644 * This will be overridden later during RAM initialization */ -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0116-southbridge-amd-sr5650-Use-correct-PCI-configuration.patch b/resources/libreboot/patch/kgpe-d16/0118-southbridge-amd-sr5650-Use-correct-PCI-configuration.patch index 0e10cc9..27fd1c2 100644 --- a/resources/libreboot/patch/kgpe-d16/0116-southbridge-amd-sr5650-Use-correct-PCI-configuration.patch +++ b/resources/libreboot/patch/kgpe-d16/0118-southbridge-amd-sr5650-Use-correct-PCI-configuration.patch @@ -1,13 +1,13 @@ -From 5428b15fb1aef85b47fbbb117d943d2525a84692 Mon Sep 17 00:00:00 2001 +From f5d5d25583a6aee7f725a6de8cc0a51753502666 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Fri, 14 Aug 2015 02:50:44 -0500 -Subject: [PATCH 116/139] southbridge/amd/sr5650: Use correct PCI configuration - block offset +Subject: [PATCH 118/143] southbridge/amd/sr5650: Use correct PCI + configuration block offset Change-Id: I4277d1788d8f9a501399218544aa6d4d11349ccc Signed-off-by: Timothy Pearson --- - src/southbridge/amd/sr5650/acpi/sr5650.asl | 4 ++-- + src/southbridge/amd/sr5650/acpi/sr5650.asl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/southbridge/amd/sr5650/acpi/sr5650.asl b/src/southbridge/amd/sr5650/acpi/sr5650.asl @@ -26,5 +26,5 @@ index a6ab114..1e0d5b0 100644 /* PIC IRQ mapping registers, C00h-C01h */ OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0117-southbridge-amd-sr5650-Add-MCFG-ACPI-table-support.patch b/resources/libreboot/patch/kgpe-d16/0119-southbridge-amd-sr5650-Add-MCFG-ACPI-table-support.patch index d4a1b9e..9ae30ac 100644 --- a/resources/libreboot/patch/kgpe-d16/0117-southbridge-amd-sr5650-Add-MCFG-ACPI-table-support.patch +++ b/resources/libreboot/patch/kgpe-d16/0119-southbridge-amd-sr5650-Add-MCFG-ACPI-table-support.patch @@ -1,26 +1,27 @@ -From 2062da830bac8ed759d18e3b06df0a97fd852ac9 Mon Sep 17 00:00:00 2001 +From 5bffd9941711ac36bf2828f0df355ff4acc1afd5 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Fri, 14 Aug 2015 15:20:42 -0500 -Subject: [PATCH 117/139] southbridge/amd/sr5650: Add MCFG ACPI table support +Subject: [PATCH 119/143] southbridge/amd/sr5650: Add MCFG ACPI table support Change-Id: I0c4ba74ddcc727cd92b848d5d3240e6f9f392101 Signed-off-by: Timothy Pearson --- - src/southbridge/amd/rs780/rs780.c | 9 +++++++++ - src/southbridge/amd/rs780/rs780.h | 1 + - src/southbridge/amd/sb700/lpc.c | 6 ------ - src/southbridge/amd/sb800/lpc.c | 7 +------ - src/southbridge/amd/sr5650/sr5650.c | 16 ++++++++++++++++ - 5 files changed, 27 insertions(+), 12 deletions(-) + src/southbridge/amd/rs780/rs780.c | 11 +++++++++++ + src/southbridge/amd/rs780/rs780.h | 1 + + src/southbridge/amd/sb700/lpc.c | 6 ------ + src/southbridge/amd/sb800/lpc.c | 7 +------ + src/southbridge/amd/sr5650/sr5650.c | 16 ++++++++++++++++ + 5 files changed, 29 insertions(+), 12 deletions(-) diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c -index c7003c7..6d5e6c7 100644 +index c7003c7..3b2c4f4 100644 --- a/src/southbridge/amd/rs780/rs780.c +++ b/src/southbridge/amd/rs780/rs780.c -@@ -353,6 +353,15 @@ void rs780_enable(device_t dev) +@@ -353,6 +353,17 @@ void rs780_enable(device_t dev) } } ++#if !IS_ENABLED(CONFIG_AMD_SB_CIMX) +unsigned long acpi_fill_mcfg(unsigned long current) +{ + /* FIXME @@ -29,6 +30,7 @@ index c7003c7..6d5e6c7 100644 + */ + return current; +} ++#endif + struct chip_operations southbridge_amd_rs780_ops = { CHIP_NAME("ATI RS780") @@ -115,5 +117,5 @@ index b296c47..4622f36 100644 { uint8_t *p; -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0118-southbridge-amd-sb700-Fix-mismatched-FADT-entries.patch b/resources/libreboot/patch/kgpe-d16/0120-southbridge-amd-sb700-Fix-mismatched-FADT-entries.patch index a1a2049..21743a0 100644 --- a/resources/libreboot/patch/kgpe-d16/0118-southbridge-amd-sb700-Fix-mismatched-FADT-entries.patch +++ b/resources/libreboot/patch/kgpe-d16/0120-southbridge-amd-sb700-Fix-mismatched-FADT-entries.patch @@ -1,16 +1,16 @@ -From cd71955dea67d3bea66627c6e40b8a569af60391 Mon Sep 17 00:00:00 2001 +From 26689886278806df6859ca47cc7bb632daf8f3c0 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Tue, 18 Aug 2015 17:45:48 -0500 -Subject: [PATCH 118/139] southbridge/amd/sb700: Fix mismatched FADT entries +Subject: [PATCH 120/143] southbridge/amd/sb700: Fix mismatched FADT entries Change-Id: Ifa0b61678fe362481891fc015cebe08485b66fc1 Signed-off-by: Timothy Pearson --- - src/southbridge/amd/sb700/fadt.c | 4 ++-- + src/southbridge/amd/sb700/fadt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/southbridge/amd/sb700/fadt.c b/src/southbridge/amd/sb700/fadt.c -index 6b1924f..209e9aa 100644 +index e860016..ec5d9bf 100644 --- a/src/southbridge/amd/sb700/fadt.c +++ b/src/southbridge/amd/sb700/fadt.c @@ -131,7 +131,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) @@ -32,5 +32,5 @@ index 6b1924f..209e9aa 100644 fadt->x_gpe0_blk.resv = 0; fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK; -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0119-southbridge-amd-sb700-Fix-drifting-system-clock.patch b/resources/libreboot/patch/kgpe-d16/0121-southbridge-amd-sb700-Fix-drifting-system-clock.patch index 7a15867..75a11f6 100644 --- a/resources/libreboot/patch/kgpe-d16/0119-southbridge-amd-sb700-Fix-drifting-system-clock.patch +++ b/resources/libreboot/patch/kgpe-d16/0121-southbridge-amd-sb700-Fix-drifting-system-clock.patch @@ -1,12 +1,12 @@ -From d0f4a06a86fbb28d9a6829fec10e7959eb845ab9 Mon Sep 17 00:00:00 2001 +From 49e08c434dc1b0a608496f0187c18d2ce83a59e0 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Fri, 28 Aug 2015 15:31:31 -0500 -Subject: [PATCH 119/139] southbridge/amd/sb700: Fix drifting system clock +Subject: [PATCH 121/143] southbridge/amd/sb700: Fix drifting system clock Change-Id: I1698c9b9b1840d254115821f3c0e76b7211e9056 Signed-off-by: Timothy Pearson --- - src/southbridge/amd/sb700/early_setup.c | 14 +++++++++++--- + src/southbridge/amd/sb700/early_setup.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c @@ -43,5 +43,5 @@ index da03961..fe8824f 100644 /* -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0120-northbridge-amd-amdmct-mct_ddr3-Add-cc6-setup-inform.patch b/resources/libreboot/patch/kgpe-d16/0122-northbridge-amd-amdmct-mct_ddr3-Add-cc6-setup-inform.patch index 39a7a9f..d0a9375 100644 --- a/resources/libreboot/patch/kgpe-d16/0120-northbridge-amd-amdmct-mct_ddr3-Add-cc6-setup-inform.patch +++ b/resources/libreboot/patch/kgpe-d16/0122-northbridge-amd-amdmct-mct_ddr3-Add-cc6-setup-inform.patch @@ -1,13 +1,13 @@ -From 473fa0658e73ccdc92d376b8855d3e38e2592d3a Mon Sep 17 00:00:00 2001 +From d5949a4d3b9b555b1e2a86d2dcb62b23c71cce6f Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Thu, 20 Aug 2015 12:49:49 -0500 -Subject: [PATCH 120/139] northbridge/amd/amdmct/mct_ddr3: Add cc6 setup +Subject: [PATCH 122/143] northbridge/amd/amdmct/mct_ddr3: Add cc6 setup information messages Change-Id: I17660ce5429431e08476b7bba15e381636b64c7d Signed-off-by: Timothy Pearson --- - src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 11 +++++++++++ + src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -54,5 +54,5 @@ index 42630b9..1c3f5a3 100644 static void lock_dram_config(struct MCTStatStruc *pMCTstat, -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0121-northbridge-amd-amdfam10-Work-around-sporadic-lockup.patch b/resources/libreboot/patch/kgpe-d16/0123-northbridge-amd-amdfam10-Work-around-sporadic-lockup.patch index 2d12303..44cde38 100644 --- a/resources/libreboot/patch/kgpe-d16/0121-northbridge-amd-amdfam10-Work-around-sporadic-lockup.patch +++ b/resources/libreboot/patch/kgpe-d16/0123-northbridge-amd-amdfam10-Work-around-sporadic-lockup.patch @@ -1,17 +1,17 @@ -From b26909b4b537b7e3b1e5a5b1379ae7745c1e36b3 Mon Sep 17 00:00:00 2001 +From b398fb43bb4ebc4d8d8c77e07e14b747971c39b4 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Thu, 20 Aug 2015 15:53:25 -0500 -Subject: [PATCH 121/139] northbridge/amd/amdfam10: Work around sporadic +Subject: [PATCH 123/143] northbridge/amd/amdfam10: Work around sporadic lockups when CC6 enabled Change-Id: If31140651f25f9c524a824b2da552ce3690eae18 Signed-off-by: Timothy Pearson --- - src/northbridge/amd/amdfam10/northbridge.c | 14 ++++++++++++++ + src/northbridge/amd/amdfam10/northbridge.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c -index 58b0079..8bd664d 100644 +index 740fd79..433a21c 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -814,6 +814,20 @@ static void amdfam10_domain_read_resources(device_t dev) @@ -36,5 +36,5 @@ index 58b0079..8bd664d 100644 reserved_ram_resource(dev, 8, (max_range_limit + 1) >> 10, qword >> 10); } -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0122-northbridge-amd-amdmct-mct_ddr3-Ensure-channel-clock.patch b/resources/libreboot/patch/kgpe-d16/0124-northbridge-amd-amdmct-mct_ddr3-Ensure-channel-clock.patch index 121e37f..69cfbc8 100644 --- a/resources/libreboot/patch/kgpe-d16/0122-northbridge-amd-amdmct-mct_ddr3-Ensure-channel-clock.patch +++ b/resources/libreboot/patch/kgpe-d16/0124-northbridge-amd-amdmct-mct_ddr3-Ensure-channel-clock.patch @@ -1,13 +1,13 @@ -From c16062b7739a77b084d139468f40f43d66ee26e0 Mon Sep 17 00:00:00 2001 +From 0f7089296606d80dd2b51a8ca9c4178f06aec7d5 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Thu, 27 Aug 2015 13:17:14 -0500 -Subject: [PATCH 122/139] northbridge/amd/amdmct/mct_ddr3: Ensure channel clock - skew is properly set up +Subject: [PATCH 124/143] northbridge/amd/amdmct/mct_ddr3: Ensure channel + clock skew is properly set up Change-Id: Iafc233984ae1d44fe6a1cb5b109d36397cbd991a Signed-off-by: Timothy Pearson --- - src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 46 ++++++++++++++++------------- + src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 46 +++++++++++++++------------ 1 file changed, 25 insertions(+), 21 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -111,5 +111,5 @@ index 1c3f5a3..a11b227 100644 dword &= ~(0x07070707); dword |= (pDCTstat->Trfc[3] & 0x7) << 24; /* Trfc3 */ -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0123-northbridge-amd-amdmct-mct_ddr3-Add-DDR3-termination.patch b/resources/libreboot/patch/kgpe-d16/0125-northbridge-amd-amdmct-mct_ddr3-Add-DDR3-termination.patch index 8c307a4..dcf3115 100644 --- a/resources/libreboot/patch/kgpe-d16/0123-northbridge-amd-amdmct-mct_ddr3-Add-DDR3-termination.patch +++ b/resources/libreboot/patch/kgpe-d16/0125-northbridge-amd-amdmct-mct_ddr3-Add-DDR3-termination.patch @@ -1,13 +1,13 @@ -From 0a77e6cc316cd7dd5f68fb3511b6fdc31153872f Mon Sep 17 00:00:00 2001 +From c3e283e8dca7df7f87d7198267ab421e2be19828 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Thu, 27 Aug 2015 13:18:06 -0500 -Subject: [PATCH 123/139] northbridge/amd/amdmct/mct_ddr3: Add DDR3 termination - debug output +Subject: [PATCH 125/143] northbridge/amd/amdmct/mct_ddr3: Add DDR3 + termination debug output Change-Id: Iabd2e3e20b0e9719080f6bd7be2032c1749994dc Signed-off-by: Timothy Pearson --- - src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c | 3 +++ + src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c @@ -32,5 +32,5 @@ index 09a5f68..7804a38 100644 } -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0124-northbridge-amd-amdmct-mct_ddr3-Fix-a-minor-RDIMM-CS.patch b/resources/libreboot/patch/kgpe-d16/0126-northbridge-amd-amdmct-mct_ddr3-Fix-a-minor-RDIMM-CS.patch index 7040927..85f519d 100644 --- a/resources/libreboot/patch/kgpe-d16/0124-northbridge-amd-amdmct-mct_ddr3-Fix-a-minor-RDIMM-CS.patch +++ b/resources/libreboot/patch/kgpe-d16/0126-northbridge-amd-amdmct-mct_ddr3-Fix-a-minor-RDIMM-CS.patch @@ -1,13 +1,13 @@ -From 352de00766d75d9b88a6021bfe5558a36923cc40 Mon Sep 17 00:00:00 2001 +From da95ad3fda51ddabb5b5799f459828008f841b4c Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Thu, 27 Aug 2015 13:18:53 -0500 -Subject: [PATCH 124/139] northbridge/amd/amdmct/mct_ddr3: Fix a minor RDIMM CS - select error +Subject: [PATCH 126/143] northbridge/amd/amdmct/mct_ddr3: Fix a minor RDIMM + CS select error Change-Id: I4cdfeec887813c17edcdee8858222414fb19b72c Signed-off-by: Timothy Pearson --- - src/northbridge/amd/amdmct/mct_ddr3/mctrci.c | 4 ++-- + src/northbridge/amd/amdmct/mct_ddr3/mctrci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c b/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c @@ -33,5 +33,5 @@ index 624a543..8fd2523 100644 /* Resend control word 10 */ -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0125-northbridge-amd-amdmct-mct_ddr3-Fix-odd-rank-data-co.patch b/resources/libreboot/patch/kgpe-d16/0127-northbridge-amd-amdmct-mct_ddr3-Fix-odd-rank-data-co.patch index 39148d3..285d836 100644 --- a/resources/libreboot/patch/kgpe-d16/0125-northbridge-amd-amdmct-mct_ddr3-Fix-odd-rank-data-co.patch +++ b/resources/libreboot/patch/kgpe-d16/0127-northbridge-amd-amdmct-mct_ddr3-Fix-odd-rank-data-co.patch @@ -1,13 +1,13 @@ -From 30d692e573ecf0a315b564895cf44e78d1b6daa9 Mon Sep 17 00:00:00 2001 +From e1da6392d60e4735e8b972fd20e009c2686ab638 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Thu, 27 Aug 2015 13:19:34 -0500 -Subject: [PATCH 125/139] northbridge/amd/amdmct/mct_ddr3: Fix odd rank data +Subject: [PATCH 127/143] northbridge/amd/amdmct/mct_ddr3: Fix odd rank data corruption due to incorrect DQS training Change-Id: Ibc51f5052d5189e45b3d9aa98ca8febbfe13f178 Signed-off-by: Timothy Pearson --- - src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 25 +++++++++++++++++-------- + src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 25 ++++++++++++++++-------- 1 file changed, 17 insertions(+), 8 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -61,5 +61,5 @@ index c520515..739a893 100644 for (lane = lane_start; lane < lane_end; lane++) { -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0126-northbridge-amd-amdmct-mct_ddr3-Use-antiphase-to-bet.patch b/resources/libreboot/patch/kgpe-d16/0128-northbridge-amd-amdmct-mct_ddr3-Use-antiphase-to-bet.patch index 6a186e1..c27a23d 100644 --- a/resources/libreboot/patch/kgpe-d16/0126-northbridge-amd-amdmct-mct_ddr3-Use-antiphase-to-bet.patch +++ b/resources/libreboot/patch/kgpe-d16/0128-northbridge-amd-amdmct-mct_ddr3-Use-antiphase-to-bet.patch @@ -1,13 +1,13 @@ -From 602d61a1535b24fbb04105e7e4594319641da3df Mon Sep 17 00:00:00 2001 +From 6f45e9f8fbf2fe7c3dcd3ee5db6a1f09505f8c11 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Thu, 27 Aug 2015 15:10:19 -0500 -Subject: [PATCH 126/139] northbridge/amd/amdmct/mct_ddr3: Use antiphase to +Subject: [PATCH 128/143] northbridge/amd/amdmct/mct_ddr3: Use antiphase to better center DQS window Change-Id: I1d85fddd45197ca82dcaa46fe863e64589712d1f Signed-off-by: Timothy Pearson --- - src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 57 ++++++++++++++++++-------- + src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 57 +++++++++++++++++------- 1 file changed, 40 insertions(+), 17 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -153,5 +153,5 @@ index 739a893..d870f17 100644 printk(BIOS_DEBUG, "\n"); } -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0127-northbridge-amd-amdmct-mct_ddr3-Fix-broken-support-f.patch b/resources/libreboot/patch/kgpe-d16/0129-northbridge-amd-amdmct-mct_ddr3-Fix-broken-support-f.patch index d7cedd7..4dcf7c5 100644 --- a/resources/libreboot/patch/kgpe-d16/0127-northbridge-amd-amdmct-mct_ddr3-Fix-broken-support-f.patch +++ b/resources/libreboot/patch/kgpe-d16/0129-northbridge-amd-amdmct-mct_ddr3-Fix-broken-support-f.patch @@ -1,18 +1,18 @@ -From aabb2b44191d7a2716dd89a0b9f3488b2d657cb9 Mon Sep 17 00:00:00 2001 +From d9d10881a0841481d8df2e357adb870ce52f9387 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Thu, 27 Aug 2015 23:37:38 -0500 -Subject: [PATCH 127/139] northbridge/amd/amdmct/mct_ddr3: Fix broken support +Subject: [PATCH 129/143] northbridge/amd/amdmct/mct_ddr3: Fix broken support for multiple DIMMs on single channel Change-Id: I0278656e98461882d0a64519dfde54a6cf28ab0f Signed-off-by: Timothy Pearson --- - src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 336 ++++++++++++++++++++----- - src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 8 +- - src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 2 +- - src/northbridge/amd/amdmct/mct_ddr3/mctrci.c | 26 +- - src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c | 4 + - src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c | 8 +- + src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 336 +++++++++++++++++++----- + src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 8 +- + src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 2 +- + src/northbridge/amd/amdmct/mct_ddr3/mctrci.c | 26 +- + src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c | 4 + + src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c | 8 +- 6 files changed, 310 insertions(+), 74 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -598,5 +598,5 @@ index 73b231e..5cbadc3 100644 } -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0128-drivers-pc80-Add-optional-spinlock-for-nvram-CBFS-ac.patch b/resources/libreboot/patch/kgpe-d16/0130-drivers-pc80-Add-optional-spinlock-for-nvram-CBFS-ac.patch index 6bcf1d1..b85f17f 100644 --- a/resources/libreboot/patch/kgpe-d16/0128-drivers-pc80-Add-optional-spinlock-for-nvram-CBFS-ac.patch +++ b/resources/libreboot/patch/kgpe-d16/0130-drivers-pc80-Add-optional-spinlock-for-nvram-CBFS-ac.patch @@ -1,7 +1,7 @@ -From f6d958412705c488a29bfad0aaaf7bc70cdb255a Mon Sep 17 00:00:00 2001 +From 73800f43dd3190d18488720410c73f2a4769d82d Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Fri, 28 Aug 2015 19:52:05 -0500 -Subject: [PATCH 128/139] drivers/pc80: Add optional spinlock for nvram CBFS +Subject: [PATCH 130/143] drivers/pc80: Add optional spinlock for nvram CBFS access When enabling the IOMMU on certain systems dmesg is spammed with I/O page faults like the following: @@ -17,26 +17,26 @@ Decoding the faulting address: Therefore, the error appears to be triggered by an upstream C1E request. -This was eventually traced to concurrent access to the SP5100's SMBus controller by +This was eventually traced to concurrent access to the SP5100's SPI Flash controller by multiple APs during startup. Calls to the nvram read functions get_option and read_option -call CBFS functions, which in turn make near-simultaneous requests to the SMBus controller, -thus placing the SP5100 in an invalid state. This limitation is not documented in any public -AMD errata, and was only discovered through considerable debugging effort. +call CBFS functions, which in turn make near-simultaneous requests to the SPI Flash +controller, thus placing the SP5100 in an invalid state. This limitation is not documented +in any public AMD errata, and was only discovered through considerable debugging effort. Change-Id: I4e61b1ab767b1b7958ac7c1cf20eee41d2261bef Signed-off-by: Timothy Pearson --- - src/Kconfig | 4 +++ - src/arch/x86/include/arch/smp/spinlock.h | 4 ++- - src/cpu/amd/car/post_cache_as_ram.c | 3 +++ - src/drivers/pc80/mc146818rtc.c | 43 ++++++++++++++++++++++++++++++-- + src/Kconfig | 4 +++ + src/arch/x86/include/arch/smp/spinlock.h | 4 ++- + src/cpu/amd/car/post_cache_as_ram.c | 3 +++ + src/drivers/pc80/mc146818rtc.c | 43 ++++++++++++++++++++++++++++-- 4 files changed, 51 insertions(+), 3 deletions(-) diff --git a/src/Kconfig b/src/Kconfig -index 4e46364..b85e381 100644 +index 5aa33d00..70f3cf2 100644 --- a/src/Kconfig +++ b/src/Kconfig -@@ -451,6 +451,10 @@ config HAVE_ROMSTAGE_CONSOLE_SPINLOCK +@@ -450,6 +450,10 @@ config HAVE_ROMSTAGE_CONSOLE_SPINLOCK bool default n @@ -48,7 +48,7 @@ index 4e46364..b85e381 100644 def_bool n help diff --git a/src/arch/x86/include/arch/smp/spinlock.h b/src/arch/x86/include/arch/smp/spinlock.h -index 5000779..cf142a9 100644 +index 3283540..74f8ece 100644 --- a/src/arch/x86/include/arch/smp/spinlock.h +++ b/src/arch/x86/include/arch/smp/spinlock.h @@ -1,7 +1,7 @@ @@ -62,7 +62,7 @@ index 5000779..cf142a9 100644 * Your basic SMP spinlocks, allowing only a single CPU anywhere @@ -14,6 +14,8 @@ typedef struct { #ifdef __PRE_RAM__ - spinlock_t* romstage_console_lock(void); + spinlock_t *romstage_console_lock(void); void initialize_romstage_console_lock(void); +spinlock_t* romstage_nvram_cbfs_lock(void); +void initialize_romstage_nvram_cbfs_lock(void); @@ -171,5 +171,5 @@ index 07fc884..59de0a2 100644 } -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0129-mainboard-asus-kgpe-d16-Enable-CBFS-spinlocks.patch b/resources/libreboot/patch/kgpe-d16/0131-mainboard-asus-kgpe-d16-Enable-CBFS-spinlocks.patch index 494181a..48fcb00 100644 --- a/resources/libreboot/patch/kgpe-d16/0129-mainboard-asus-kgpe-d16-Enable-CBFS-spinlocks.patch +++ b/resources/libreboot/patch/kgpe-d16/0131-mainboard-asus-kgpe-d16-Enable-CBFS-spinlocks.patch @@ -1,14 +1,14 @@ -From ff495fb11ccedb64b6eab1853a8e50d30b3da80a Mon Sep 17 00:00:00 2001 +From 3bae76eb132ce6b35542e7727397556b457d6d77 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Fri, 28 Aug 2015 20:02:45 -0500 -Subject: [PATCH 129/139] mainboard/asus/kgpe-d16: Enable CBFS spinlocks +Subject: [PATCH 131/143] mainboard/asus/kgpe-d16: Enable CBFS spinlocks Change-Id: I8f6226d3e74ac5c7f29f708128a7502ced1287bf Signed-off-by: Timothy Pearson --- - src/mainboard/asus/kgpe-d16/Kconfig | 1 + - src/mainboard/asus/kgpe-d16/romstage.c | 17 +++++++++++++++-- - 2 files changed, 16 insertions(+), 2 deletions(-) + src/mainboard/asus/kgpe-d16/Kconfig | 1 + + src/mainboard/asus/kgpe-d16/romstage.c | 15 ++++++++++++++- + 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/src/mainboard/asus/kgpe-d16/Kconfig b/src/mainboard/asus/kgpe-d16/Kconfig index 084a412..a9261f9 100644 @@ -23,7 +23,7 @@ index 084a412..a9261f9 100644 select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c -index fa61f63..9998359 100644 +index cbda9ca..9998359 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -315,6 +315,18 @@ void initialize_romstage_console_lock(void) @@ -56,13 +56,6 @@ index fa61f63..9998359 100644 /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ -@@ -561,4 +574,4 @@ BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) - } - - return 0; --} -\ No newline at end of file -+} -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0130-cpu-amd-microcode-Introduce-CBFS-access-spinlock-to-.patch b/resources/libreboot/patch/kgpe-d16/0132-cpu-amd-microcode-Introduce-CBFS-access-spinlock-to-.patch index b530570..2660565 100644 --- a/resources/libreboot/patch/kgpe-d16/0130-cpu-amd-microcode-Introduce-CBFS-access-spinlock-to-.patch +++ b/resources/libreboot/patch/kgpe-d16/0132-cpu-amd-microcode-Introduce-CBFS-access-spinlock-to-.patch @@ -1,24 +1,24 @@ -From 66525594fa1976aae7d7f97e4b7455fc66e900df Mon Sep 17 00:00:00 2001 +From 150c1d37f6b42233ae47a9289563164b8685825a Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Fri, 28 Aug 2015 20:48:17 -0500 -Subject: [PATCH 130/139] cpu/amd/microcode: Introduce CBFS access spinlock to +Subject: [PATCH 132/143] cpu/amd/microcode: Introduce CBFS access spinlock to avoid IOMMU failure Change-Id: Ib7e8cb171f44833167053ca98a85cca23021dfba Signed-off-by: Timothy Pearson --- - src/Kconfig | 4 ++++ - src/arch/x86/include/arch/smp/spinlock.h | 7 ++++++- - src/cpu/amd/microcode/microcode.c | 24 +++++++++++++++++++++++- - src/mainboard/asus/kgpe-d16/Kconfig | 1 + - src/mainboard/asus/kgpe-d16/romstage.c | 15 ++++++++++++++- + src/Kconfig | 4 ++++ + src/arch/x86/include/arch/smp/spinlock.h | 7 ++++++- + src/cpu/amd/microcode/microcode.c | 24 +++++++++++++++++++++++- + src/mainboard/asus/kgpe-d16/Kconfig | 1 + + src/mainboard/asus/kgpe-d16/romstage.c | 15 ++++++++++++++- 5 files changed, 48 insertions(+), 3 deletions(-) diff --git a/src/Kconfig b/src/Kconfig -index b85e381..5d5da98 100644 +index 70f3cf2..353eede 100644 --- a/src/Kconfig +++ b/src/Kconfig -@@ -455,6 +455,10 @@ config HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK +@@ -454,6 +454,10 @@ config HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK bool default n @@ -30,7 +30,7 @@ index b85e381..5d5da98 100644 def_bool n help diff --git a/src/arch/x86/include/arch/smp/spinlock.h b/src/arch/x86/include/arch/smp/spinlock.h -index cf142a9..291c943 100644 +index 74f8ece..a9dcfcd 100644 --- a/src/arch/x86/include/arch/smp/spinlock.h +++ b/src/arch/x86/include/arch/smp/spinlock.h @@ -1,7 +1,10 @@ @@ -45,7 +45,7 @@ index cf142a9..291c943 100644 /* * Your basic SMP spinlocks, allowing only a single CPU anywhere -@@ -16,6 +19,8 @@ spinlock_t* romstage_console_lock(void); +@@ -16,6 +19,8 @@ spinlock_t *romstage_console_lock(void); void initialize_romstage_console_lock(void); spinlock_t* romstage_nvram_cbfs_lock(void); void initialize_romstage_nvram_cbfs_lock(void); @@ -151,5 +151,5 @@ index 9998359..d1b75b6 100644 /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0131-mainboard-asus-kgpe-d16-Limit-HT-speed-to-2.6GHz.patch b/resources/libreboot/patch/kgpe-d16/0133-mainboard-asus-kgpe-d16-Limit-HT-speed-to-2.6GHz.patch index 72d834c..77982af 100644 --- a/resources/libreboot/patch/kgpe-d16/0131-mainboard-asus-kgpe-d16-Limit-HT-speed-to-2.6GHz.patch +++ b/resources/libreboot/patch/kgpe-d16/0133-mainboard-asus-kgpe-d16-Limit-HT-speed-to-2.6GHz.patch @@ -1,7 +1,7 @@ -From a3c83c34f3871be5624259a8a5d76bbae0386720 Mon Sep 17 00:00:00 2001 +From b508ee385b1d1ce53d40d4ff46f3b642382906b8 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Thu, 3 Sep 2015 17:39:51 -0500 -Subject: [PATCH 131/139] mainboard/asus/kgpe-d16: Limit HT speed to 2.6GHz +Subject: [PATCH 133/143] mainboard/asus/kgpe-d16: Limit HT speed to 2.6GHz The CPU <--> CPU HT wiring on this board has only been validated to 2.6GHz. While higher frequencies appear to function initially, @@ -17,7 +17,7 @@ by running memtester locked to a node with no local memory installed. Change-Id: I8fae90c67aa0e8b103e9b8906dea50d1e92ea5a9 Signed-off-by: Timothy Pearson --- - src/mainboard/asus/kgpe-d16/romstage.c | 5 +++++ + src/mainboard/asus/kgpe-d16/romstage.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c @@ -37,5 +37,5 @@ index d1b75b6..8f1ec35 100644 uint8_t byte; msr_t msr; -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0132-cpu-amd-family_10h-family_15h-Apply-missing-Family-1.patch b/resources/libreboot/patch/kgpe-d16/0134-cpu-amd-family_10h-family_15h-Apply-missing-Family-1.patch index 126e45a..c52d584 100644 --- a/resources/libreboot/patch/kgpe-d16/0132-cpu-amd-family_10h-family_15h-Apply-missing-Family-1.patch +++ b/resources/libreboot/patch/kgpe-d16/0134-cpu-amd-family_10h-family_15h-Apply-missing-Family-1.patch @@ -1,14 +1,14 @@ -From 4dede601a2017d8a9696f8f2013a9b2b97d5169e Mon Sep 17 00:00:00 2001 +From 448990c014328f7e6951e3ba1c4dfab25e35e9dd Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Thu, 3 Sep 2015 17:43:52 -0500 -Subject: [PATCH 132/139] cpu/amd/family_10h-family_15h: Apply missing Family +Subject: [PATCH 134/143] cpu/amd/family_10h-family_15h: Apply missing Family 15h errata fixes Change-Id: I132874fe5b5a8b9a87422e2f07bff03bc5863ca4 Signed-off-by: Timothy Pearson --- - src/cpu/amd/family_10h-family_15h/defaults.h | 12 ++++++++++++ - src/northbridge/amd/amdfam10/misc_control.c | 6 ++++++ + src/cpu/amd/family_10h-family_15h/defaults.h | 12 ++++++++++++ + src/northbridge/amd/amdfam10/misc_control.c | 6 ++++++ 2 files changed, 18 insertions(+) diff --git a/src/cpu/amd/family_10h-family_15h/defaults.h b/src/cpu/amd/family_10h-family_15h/defaults.h @@ -66,5 +66,5 @@ index 4b62c69..a3d6b19 100644 } } -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0133-northbridge-amd-amdmct-mct_ddr3-Use-StopOnError-to-d.patch b/resources/libreboot/patch/kgpe-d16/0135-northbridge-amd-amdmct-mct_ddr3-Use-StopOnError-to-d.patch index 1993cab..b946b42 100644 --- a/resources/libreboot/patch/kgpe-d16/0133-northbridge-amd-amdmct-mct_ddr3-Use-StopOnError-to-d.patch +++ b/resources/libreboot/patch/kgpe-d16/0135-northbridge-amd-amdmct-mct_ddr3-Use-StopOnError-to-d.patch @@ -1,14 +1,14 @@ -From d73cea7b450c1da2d4cd4af9d28f3ea97fb40f9d Mon Sep 17 00:00:00 2001 +From be23a938df377710e927fa920a656a70409139b4 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Thu, 3 Sep 2015 18:59:53 -0500 -Subject: [PATCH 133/139] northbridge/amd/amdmct/mct_ddr3: Use StopOnError to +Subject: [PATCH 135/143] northbridge/amd/amdmct/mct_ddr3: Use StopOnError to decrease training time Change-Id: I979e27c32a3e0b101590fba0de3d7a25d6fc44d2 Signed-off-by: Timothy Pearson --- - src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 84 +++++++++++++++++++------- - src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 4 +- + src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 84 +++++++++++++++++------- + src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 4 +- 2 files changed, 64 insertions(+), 24 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -227,5 +227,5 @@ index 3ede104..667854a 100644 if (!dword) break; -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0134-mainboard-asus-kgpe-d16-Enable-GART-by-default.patch b/resources/libreboot/patch/kgpe-d16/0136-mainboard-asus-kgpe-d16-Enable-GART-by-default.patch index 22a0833..59ce417 100644 --- a/resources/libreboot/patch/kgpe-d16/0134-mainboard-asus-kgpe-d16-Enable-GART-by-default.patch +++ b/resources/libreboot/patch/kgpe-d16/0136-mainboard-asus-kgpe-d16-Enable-GART-by-default.patch @@ -1,12 +1,12 @@ -From b83b06df45933d9b0ab3f8848bf940bbfd00be67 Mon Sep 17 00:00:00 2001 +From 2170a443bd2ca52ffcc4fa596e0a9c81400b112b Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Thu, 3 Sep 2015 19:27:40 -0500 -Subject: [PATCH 134/139] mainboard/asus/kgpe-d16: Enable GART by default +Subject: [PATCH 136/143] mainboard/asus/kgpe-d16: Enable GART by default Change-Id: I73eb2425bbdb7e329a544d55461877d1dee0d05b Signed-off-by: Timothy Pearson --- - src/mainboard/asus/kgpe-d16/cmos.default | 2 +- + src/mainboard/asus/kgpe-d16/cmos.default | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default @@ -23,5 +23,5 @@ index 83c1fe8..bc4c332 100644 power_on_after_fail = On boot_option = Fallback -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0135-northbridge-amd-amdfam10-Fix-incorrect-channel-buffe.patch b/resources/libreboot/patch/kgpe-d16/0137-northbridge-amd-amdfam10-Fix-incorrect-channel-buffe.patch index 5d18509..7f99cf9 100644 --- a/resources/libreboot/patch/kgpe-d16/0135-northbridge-amd-amdfam10-Fix-incorrect-channel-buffe.patch +++ b/resources/libreboot/patch/kgpe-d16/0137-northbridge-amd-amdfam10-Fix-incorrect-channel-buffe.patch @@ -1,17 +1,17 @@ -From 057d4bcc43dfb1eec7fcf53b955592fa30d47fec Mon Sep 17 00:00:00 2001 +From 442e3d1282adc8b6fa274e880578f8bb0bfd1464 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Mon, 7 Sep 2015 03:39:15 -0500 -Subject: [PATCH 135/139] northbridge/amd/amdfam10: Fix incorrect channel +Subject: [PATCH 137/143] northbridge/amd/amdfam10: Fix incorrect channel buffer count configuration Change-Id: If70825449f298aa66f7f8b76dbd7367455a6deb1 Signed-off-by: Timothy Pearson --- - src/northbridge/amd/amdfam10/northbridge.c | 13 +++++-------- + src/northbridge/amd/amdfam10/northbridge.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c -index 8bd664d..f039a5c 100644 +index 433a21c..b4bbf23 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -188,17 +188,14 @@ static void ht_route_link(struct bus *link, scan_state mode) @@ -38,5 +38,5 @@ index 8bd664d..f039a5c 100644 if (mode == HT_ROUTE_FINAL) { -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0136-cpu-amd-family_10h-family_15h-Force-iolink-detect-to.patch b/resources/libreboot/patch/kgpe-d16/0138-cpu-amd-family_10h-family_15h-Force-iolink-detect-to.patch index 0f4e5ed..06c9be3 100644 --- a/resources/libreboot/patch/kgpe-d16/0136-cpu-amd-family_10h-family_15h-Force-iolink-detect-to.patch +++ b/resources/libreboot/patch/kgpe-d16/0138-cpu-amd-family_10h-family_15h-Force-iolink-detect-to.patch @@ -1,17 +1,17 @@ -From 587ece004106252847b7d08bf3c21c86c8b2e360 Mon Sep 17 00:00:00 2001 +From 56dd3cc28dd39ea689234513c8baeb568d8b40ea Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Mon, 7 Sep 2015 18:07:03 -0500 -Subject: [PATCH 136/139] cpu/amd/family_10h-family_15h: Force iolink detect to - either 1 or 0 +Subject: [PATCH 138/143] cpu/amd/family_10h-family_15h: Force iolink detect + to either 1 or 0 Change-Id: Ifd8f5f1ab28588d100e9e4b1fb0ec2525ad2f552 Signed-off-by: Timothy Pearson --- - src/cpu/amd/family_10h-family_15h/init_cpus.c | 4 ++-- + src/cpu/amd/family_10h-family_15h/init_cpus.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c -index 7a0701c..ff9a033 100644 +index da6424f..a0c5f93 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -1239,7 +1239,7 @@ static void cpuSetAMDPCI(u8 node) @@ -33,5 +33,5 @@ index 7a0701c..ff9a033 100644 /* Set defaults */ isoc_rsp_tok_1 = 0; -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0137-northbridge-amd-amdht-Fix-XCS-buffer-count-setup-on-.patch b/resources/libreboot/patch/kgpe-d16/0139-northbridge-amd-amdht-Fix-XCS-buffer-count-setup-on-.patch index bb4ff3b..aa57af9 100644 --- a/resources/libreboot/patch/kgpe-d16/0137-northbridge-amd-amdht-Fix-XCS-buffer-count-setup-on-.patch +++ b/resources/libreboot/patch/kgpe-d16/0139-northbridge-amd-amdht-Fix-XCS-buffer-count-setup-on-.patch @@ -1,17 +1,17 @@ -From 21df09828beb3385b1fe1eaa763578780e444b77 Mon Sep 17 00:00:00 2001 +From 01739baefdad1263adacb59442577941e037422f Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Mon, 7 Sep 2015 18:07:43 -0500 -Subject: [PATCH 137/139] northbridge/amd/amdht: Fix XCS buffer count setup on +Subject: [PATCH 139/143] northbridge/amd/amdht: Fix XCS buffer count setup on AMD Family 15h CPUs Change-Id: Ie4bc8b3ea6b110bc507beda025de53d828118f55 Signed-off-by: Timothy Pearson --- - src/northbridge/amd/amdht/h3ncmn.c | 94 +++++++++++++++++++++++++++++++++++++- + src/northbridge/amd/amdht/h3ncmn.c | 94 +++++++++++++++++++++++++++++++++++- 1 file changed, 92 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/amdht/h3ncmn.c b/src/northbridge/amd/amdht/h3ncmn.c -index 841fc0c..80fe7ce 100644 +index 369ce3e..6c111c6 100644 --- a/src/northbridge/amd/amdht/h3ncmn.c +++ b/src/northbridge/amd/amdht/h3ncmn.c @@ -2,6 +2,7 @@ @@ -98,7 +98,7 @@ index 841fc0c..80fe7ce 100644 * static void * gatherLinkData(sMainData *pDat, cNorthBridge *nb) * -@@ -2266,6 +2336,26 @@ static void fam10BufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb) +@@ -2270,6 +2340,26 @@ static void fam10BufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb) } } @@ -125,7 +125,7 @@ index 841fc0c..80fe7ce 100644 /* * North Bridge 'constructor'. * -@@ -2324,11 +2414,11 @@ void newNorthBridge(u8 node, cNorthBridge *nb) +@@ -2328,11 +2418,11 @@ void newNorthBridge(u8 node, cNorthBridge *nb) ht3SetCFGAddrMap, convertBitsToWidth, convertWidthToBits, @@ -140,5 +140,5 @@ index 841fc0c..80fe7ce 100644 0x00000200, 18, -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0138-cpu-amd-family_10h-family_15h-Fix-link-type-detectio.patch b/resources/libreboot/patch/kgpe-d16/0140-cpu-amd-family_10h-family_15h-Fix-link-type-detectio.patch index 18c1420..3cd24a1 100644 --- a/resources/libreboot/patch/kgpe-d16/0138-cpu-amd-family_10h-family_15h-Fix-link-type-detectio.patch +++ b/resources/libreboot/patch/kgpe-d16/0140-cpu-amd-family_10h-family_15h-Fix-link-type-detectio.patch @@ -1,18 +1,18 @@ -From d08d31fc7f2299fc6c12be09061c62170615d160 Mon Sep 17 00:00:00 2001 +From 3e7456a5999ae840e95b054908057e19b40aaf40 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Mon, 7 Sep 2015 22:26:55 -0500 -Subject: [PATCH 138/139] cpu/amd/family_10h-family_15h: Fix link type +Subject: [PATCH 140/143] cpu/amd/family_10h-family_15h: Fix link type detection and XCS buffer count setup Change-Id: If63dd97f070df4aab25a1e1a34df4b1112fff4b1 Signed-off-by: Timothy Pearson --- - src/cpu/amd/family_10h-family_15h/fidvid.c | 2 +- - src/cpu/amd/family_10h-family_15h/init_cpus.c | 33 +++++++++++++++------------ + src/cpu/amd/family_10h-family_15h/fidvid.c | 2 +- + src/cpu/amd/family_10h-family_15h/init_cpus.c | 33 ++++++++++++++----------- 2 files changed, 20 insertions(+), 15 deletions(-) diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c -index ed8cafa..84315b4 100644 +index 7453ad4..f4ca888 100644 --- a/src/cpu/amd/family_10h-family_15h/fidvid.c +++ b/src/cpu/amd/family_10h-family_15h/fidvid.c @@ -379,7 +379,7 @@ static u32 nb_clk_did(int node, uint64_t cpuRev, uint8_t procPkg) { @@ -25,7 +25,7 @@ index ed8cafa..84315b4 100644 /* FIXME: NB_CLKDID should be 101b for AMD_DA_C2 in package S1g3 in link Gen3 mode, but I don't know how to tell diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c -index ff9a033..f86cc75 100644 +index a0c5f93..344dab0 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -845,7 +845,7 @@ static BOOL AMD_CpuFindCapability(u8 node, u8 cap_count, u8 * offset) @@ -143,16 +143,16 @@ index ff9a033..f86cc75 100644 uint8_t isochronous; uint8_t isochronous_link_present; -@@ -1705,7 +1709,8 @@ static void cpuSetAMDPCI(u8 node) - isochronous_link_present = 0; - for (link = 0; link < 4; link++) { - if (AMD_CpuFindCapability(node, link, &offset)) { -- isochronous = (pci_read_config32(NODE_PCI(node, 0), (link * 0x20) + 0x84) >> 12) & 0x1; -+ link_real = (offset - 0x80) / 0x20; -+ isochronous = (pci_read_config32(NODE_PCI(node, 0), (link_real * 0x20) + 0x84) >> 12) & 0x1; +@@ -1706,7 +1710,8 @@ static void cpuSetAMDPCI(u8 node) + if (revision & AMD_FAM15_ALL) { + for (link = 0; link < 4; link++) { + if (AMD_CpuFindCapability(node, link, &offset)) { +- isochronous = (pci_read_config32(NODE_PCI(node, 0), (link * 0x20) + 0x84) >> 12) & 0x1; ++ link_real = (offset - 0x80) / 0x20; ++ isochronous = (pci_read_config32(NODE_PCI(node, 0), (link_real * 0x20) + 0x84) >> 12) & 0x1; - if (isochronous) - isochronous_link_present = 1; + if (isochronous) + isochronous_link_present = 1; -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0139-cpu-amd-family_10h-family_15h-Enable-DFE-on-Family-1.patch b/resources/libreboot/patch/kgpe-d16/0141-cpu-amd-family_10h-family_15h-Enable-DFE-on-Family-1.patch index da36ce8..5dfd35a 100644 --- a/resources/libreboot/patch/kgpe-d16/0139-cpu-amd-family_10h-family_15h-Enable-DFE-on-Family-1.patch +++ b/resources/libreboot/patch/kgpe-d16/0141-cpu-amd-family_10h-family_15h-Enable-DFE-on-Family-1.patch @@ -1,13 +1,13 @@ -From 43dd7e42cfd9e3af706dd28fc482921b54029496 Mon Sep 17 00:00:00 2001 +From a48cdc6abd37ccd7e41bcac11a97475a464b8a2e Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sun, 13 Sep 2015 15:54:32 -0500 -Subject: [PATCH 139/139] cpu/amd/family_10h-family_15h: Enable DFE on Family +Subject: [PATCH 141/143] cpu/amd/family_10h-family_15h: Enable DFE on Family 15h HT3 links Change-Id: I5e719984ddd723f9e375ff1a9d4fa1ef042cf3eb Signed-off-by: Timothy Pearson --- - src/cpu/amd/family_10h-family_15h/defaults.h | 8 ++++++++ + src/cpu/amd/family_10h-family_15h/defaults.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/cpu/amd/family_10h-family_15h/defaults.h b/src/cpu/amd/family_10h-family_15h/defaults.h @@ -28,5 +28,5 @@ index 7a84fcb..b906866 100644 + [7] DfeEn = 0x1 */ }; -- -1.9.1 +1.7.9.5 diff --git a/resources/libreboot/patch/kgpe-d16/0142-cpu-amd-family_10h-family_15h-Fix-build-when-microco.patch b/resources/libreboot/patch/kgpe-d16/0142-cpu-amd-family_10h-family_15h-Fix-build-when-microco.patch new file mode 100644 index 0000000..2c37b13 --- /dev/null +++ b/resources/libreboot/patch/kgpe-d16/0142-cpu-amd-family_10h-family_15h-Fix-build-when-microco.patch @@ -0,0 +1,28 @@ +From eb8c3bae85caf446f38e820e9569268731ef4cab Mon Sep 17 00:00:00 2001 +From: Timothy Pearson +Date: Mon, 19 Oct 2015 03:14:04 -0500 +Subject: [PATCH 142/143] cpu/amd/family_10h-family_15h: Fix build when + microcode not included + +Change-Id: I9bd7ea57b0e307d871215754aa490eb15fafcce2 +Signed-off-by: Timothy Pearson +--- + src/cpu/amd/family_10h-family_15h/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig +index bfb6751..be9203d 100644 +--- a/src/cpu/amd/family_10h-family_15h/Kconfig ++++ b/src/cpu/amd/family_10h-family_15h/Kconfig +@@ -11,7 +11,7 @@ config CPU_AMD_MODEL_10XXX + select UDELAY_LAPIC + select HAVE_MONOTONIC_TIMER + select SUPPORT_CPU_UCODE_IN_CBFS +- select CPU_MICROCODE_MULTIPLE_FILES ++ select CPU_MICROCODE_MULTIPLE_FILES if CPU_MICROCODE_CBFS_GENERATE + + if CPU_AMD_MODEL_10XXX + +-- +1.7.9.5 + diff --git a/resources/libreboot/patch/kgpe-d16/0143-device-smbus-Avoid-infinite-loop-if-i2c-device-has-w.patch b/resources/libreboot/patch/kgpe-d16/0143-device-smbus-Avoid-infinite-loop-if-i2c-device-has-w.patch new file mode 100644 index 0000000..bf9c829 --- /dev/null +++ b/resources/libreboot/patch/kgpe-d16/0143-device-smbus-Avoid-infinite-loop-if-i2c-device-has-w.patch @@ -0,0 +1,39 @@ +From 54ef1e4efe549e310b29258fe9c2efcc367ae942 Mon Sep 17 00:00:00 2001 +From: Timothy Pearson +Date: Thu, 22 Oct 2015 17:19:19 -0500 +Subject: [PATCH 143/143] device/smbus: Avoid infinite loop if i2c device has + wrong parent + +Change-Id: I4c615f3c5b3908178b8223cb6620c393bbfb4e7f +Signed-off-by: Timothy Pearson +--- + src/device/smbus_ops.c | 13 +++++++++++-- + 1 file changed, 11 insertions(+), 2 deletions(-) + +diff --git a/src/device/smbus_ops.c b/src/device/smbus_ops.c +index 184a06a..f4b1355 100644 +--- a/src/device/smbus_ops.c ++++ b/src/device/smbus_ops.c +@@ -29,8 +29,17 @@ struct bus *get_pbus_smbus(device_t dev) + { + struct bus *pbus = dev->bus; + +- while (pbus && pbus->dev && !ops_smbus_bus(pbus)) +- pbus = pbus->dev->bus; ++ while (pbus && pbus->dev && !ops_smbus_bus(pbus)) { ++ if (pbus->dev->bus != pbus) { ++ pbus = pbus->dev->bus; ++ } ++ else { ++ printk(BIOS_WARNING, ++ "%s Find SMBus bus operations: unable to proceed\n", ++ dev_path(dev)); ++ break; ++ } ++ } + + if (!pbus || !pbus->dev || !pbus->dev->ops + || !pbus->dev->ops->ops_smbus_bus) { +-- +1.7.9.5 + diff --git a/resources/scripts/helpers/download/coreboot b/resources/scripts/helpers/download/coreboot index b6dc16f..139dad4 100755 --- a/resources/scripts/helpers/download/coreboot +++ b/resources/scripts/helpers/download/coreboot @@ -44,7 +44,7 @@ git clone http://review.coreboot.org/coreboot cd "coreboot/" # reset to previously tested revision -git reset --hard d98471ccb412f61d7da2c5eb5ca8eeb8fece384a +git reset --hard 33fb4cf0ffb01be8bcb6b488872c87eb50e7d77f # vboot submodule is needed git submodule update --init --checkout -- 3rdparty/vboot/ diff --git a/resources/utilities/coreboot-libre/nonblobs b/resources/utilities/coreboot-libre/nonblobs index d15f435..c63a65a 100644 --- a/resources/utilities/coreboot-libre/nonblobs +++ b/resources/utilities/coreboot-libre/nonblobs @@ -355,3 +355,10 @@ ./src/mainboard/intel/mohonpeak/Kconfig ./src/mainboard/apple/macbookair4_2/early_southbridge.c ./src/cpu/intel/fsp_model_406dx/acpi.c +./src/northbridge/intel/fsp_sandybridge/fsp/Kconfig +./src/drivers/aspeed/common/ast_dram_tables.h +./src/drivers/aspeed/common/ast_tables.h +./src/mainboard/intel/cougar_canyon2/Kconfig +./src/cpu/amd/family_10h-family_15h/processor_name.c +./src/cpu/amd/family_10h-family_15h/init_cpus.c +./src/cpu/intel/fsp_model_206ax/acpi.c -- cgit v0.9.1