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* coreboot-libre: move non-blob to nonblobs listFrancis Rowe2015-10-113-4/+4
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* coreboot-libre: Crypto constants in vboot are not proprietary blobsPaul Kocialkowski2015-10-112-4/+4
| | | | Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* Update coreboot-libre based on coreboot a2bed346aFrancis Rowe2015-10-102-44/+46
| | | | | | | | | | | | | | | More microcode blobs were deleted upstream, which are therefore no longer deleted by coreboot-libre. util/broadcom/secimage/misc.c is not a blob. Some non-blobs were deleted upstream, which are therefore no longer listed in libreboot's nonblobs list. New non-blobs were found, added to the nonblobs list. vboot submodule was added, since there are parts of it that cbfstool needs. This submodule is now deblobbed by libreboot.
* New board: ThinkPad R500 (experimental)Francis Rowe2015-09-201-0/+3
| | | | | | | | | | | | | | | | | | The ich9deblob and ich9gen utilities were modified, so that they support reading and/or writing descriptor images where the GbE region is not defined. These utilities were also re-factored and tidied up a bit. A quick was noticed during the course of this work, in that Compenent 1 Density was being set to 8MiB constantly, even on systems with 4MiB flash chips. Component 2 Density was set statically to 2MiB. ich9gen now sets both to 4MiB or 8MiB, depending on whether building the descriptor for a 4MiB or 8MiB ROM image. There are still some ACPI bugs (see docs/hcl/r500.html), which will have to be fixed upstream. TODO: get hw reg dumps from a factory R500, and compare with the X200 or T400 dumps.
* coreboot-libre: update linux-libre deblob-check to v2015-08-15Francis Rowe2015-08-301-4/+114
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* Update coreboot to the latest as of 4 August 2015Francis Rowe2015-08-041-8/+33
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* Update coreboot-libreFrancis Rowe2015-06-152-17/+38
| | | | | | | | | | | | Rebase all patches. Remove the ones that are no longer needed. More CPU microcode updates were moved to coreboot's 3rdparty repository, so there are less blobs for libreboot to delete now (because the 3rdparty repository is not checked out in libreboot). Correct HDA verbs used for T400 (also R400, T500) (patch is in coreboot, merged).
* all script: use a standard styleFrancis Rowe2015-06-102-15/+15
| | | | | Based on the style used for the script in resources/scripts/helpers/build/release/
* Update coreboot + merge GM45 hybrid GPU patchesFrancis Rowe2015-05-042-9/+151
| | | | | | | | | | | | | Also add power_on_after_fail to X200 and others (prevents the bug where the system would boot when connecting the AC adapter) (option in menuconfig to use CMOS/nvram settings is now enabled) Also NetDCDC is now the default USB debug dongle used (compatible with the BBB rev C). Add two new methods for managing coreboot configs: ./build config corebootreplace ./build config corebootmodify
* coreboot-libre: provide better blob categorizationFrancis Rowe2015-03-271-24/+64
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* Update corebootFrancis Rowe2015-03-162-183/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update to new coreboot revision: 83b05eb0a85d7b7ac0837cece67afabbdb46ea65 Intel microcode updates are no longer deleted, because these no longer exist in the main coreboot branch. Instead, they exist in the optional 3rdparty repository which libreboot does not merge. note: the microcode in src/soc/intel/ still exists and is still deleted in libreboot, therefore TODO: delete the instructions in coreboot that download the 3rdparty branch MacBook2,1 cstate patch is no longer cherry picked, because this is now merged in the main coreboot repository. The patch to disable use of timestamps in non-git is now removed, because a better version of patch was submitted to and merged in coreboot. coreboot-libre: These blobs either don't exist in coreboot anymore, or have had their names changed. They are no longer listed in the deblob script: src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000025.c src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000028.c src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000101.c src/cpu/amd/model_10xxx/mc_patch_01000086.h src/cpu/amd/model_10xxx/mc_patch_0100009f.h src/cpu/amd/model_10xxx/mc_patch_010000b6.h src/cpu/amd/model_10xxx/mc_patch_010000bf.h src/cpu/amd/model_10xxx/mc_patch_010000c4.h src/northbridge/amd/agesa/family12/ssdt.asl coreboot-libre: These nonblobs either don't exist in coreboot anymore, or have had their names changed. They are no longer listed in the nonblobs or nonblobs_notes files: ./src/mainboard/digitallogic/msm586seg/mainboard.c ./src/mainboard/intel/jarrell/irq_tables.c ./src/mainboard/supermicro/x6dai_g/irq_tables.c ./src/mainboard/technologic/ts5300/mainboard.c ./src/mainboard/via/epia/irq_tables.c ./src/northbridge/via/vx800/examples/chipset_init.c ./src/southbridge/amd/cs5530/bitmap.c ./src/southbridge/amd/pi/avalon/Kconfig ./src/mainboard/google/samus/samsung_8Gb.spd.hex ./src/mainboard/google/samus/empty.spd.hex ./src/mainboard/google/samus/elpida_4Gb.spd.hex ./src/mainboard/google/samus/elpida_8Gb.spd.hex ./src/mainboard/google/samus/samsung_4Gb.spd.hex coreboot-libre: The following were added to the nonblobs file: ./src/mainboard/google/samus/spd/samsung_4Gb.spd.hex ./src/mainboard/google/samus/spd/empty.spd.hex ./src/mainboard/google/samus/spd/elpida_8Gb.spd.hex ./src/mainboard/google/samus/spd/hynix_4Gb.spd.hex ./src/mainboard/google/samus/spd/samsung_8Gb.spd.hex ./src/mainboard/google/samus/spd/hynix_8Gb.spd.hex ./src/mainboard/google/samus/spd/elpida_4Gb.spd.hex ./src/drivers/xgi/common/vb_table.h ./src/drivers/xgi/common/vb_setmode.c ./src/drivers/xgi/common/XGI_main.h ./src/mainboard/siemens/mc_tcu3/romstage.c ./src/mainboard/siemens/mc_tcu3/lcd_panel.c ./src/mainboard/siemens/mc_tcu3/modhwinfo.c ./src/mainboard/pcengines/apu1/Kconfig ./src/mainboard/asus/kfsn4-dre/get_bus_conf.c ./src/mainboard/google/samus/spd/spd.c ./src/mainboard/hp/abm/mptable.c ./src/northbridge/amd/pi/00630F01/Kconfig ./src/cpu/amd/microcode/microcode.c ./src/lib/tlcl_structures.h coreboot-libre: New blobs in coreboot are now deleted in libreboot: src/soc/intel/baytrail/microcode/M0C3067_0000031E.h src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000119.c src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000029.c src/cpu/amd/model_10xxx/mc_patch_010000d9.h src/cpu/amd/model_10xxx/mc_patch_010000dc.h src/cpu/amd/model_10xxx/mc_patch_010000db.h src/cpu/amd/model_10xxx/mc_patch_010000c7.h src/cpu/amd/model_10xxx/mc_patch_010000c8.h
* coreboot-libre: don't list vortex86ex kbd firmware as microcodeFrancis Rowe2015-03-151-1/+7
| | | | List it separately instead.
* coreboot-libre: add TODO to not delete intel microcode updatesFrancis Rowe2015-03-151-0/+5
| | | | | | These are deleted in a later coreboot, moved to its 3rdparty repo See 5818da262dc0ce56bb1d5439b6d139bc08c25554 in coreboot or http://review.coreboot.org/#/c/4531/
* coreboot-libre: don't rm */early_setup_ss.hFrancis Rowe2015-03-153-8/+8
| | | | These are not blobs!
* coreboot-libre: add GPLv3 license to the "findblobs" scriptFrancis Rowe2015-03-151-0/+18
| | | | | Ironically, this was proprietary because it lacked a license. This commit fixes that.
* coreboot-libreboot: don't rm raminit_tables (nahelem/sandybridge)Francis Rowe2015-03-153-7/+6
| | | | These are not blobs!
* coreboot-libre: don't delete the .spd.hex filesFrancis Rowe2015-03-153-32/+30
| | | | These are not blobs
* docs/release.html: Update TODO listFrancis Rowe2015-03-061-0/+3
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* bash scripts: Make script output more user-friendlyFrancis Rowe2015-02-202-4/+7
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* bash scripts: Only enable verbose output if DEBUG= is usedFrancis Rowe2015-02-192-2/+4
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* Move DEBLOB to resources/utilities/coreboot-libre/deblobFrancis Rowe2015-02-151-0/+306
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* Update coreboot (again)Francis Rowe2014-12-133-0/+8472
Also improve the deblob utilities
generated by cgit v0.9.1 at 2024-12-26 03:16:59 (EST)