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board"""
When you have to revert a revert of a revert in the same 20 minute window
then you my friend are an idiot. And that's exactly what I am.
This reverts commit d105b4a8b74645d5936cf8a51b1517f3ba89fd26.
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This reverts commit 2f3d87aec85f5759180380cbc156472378164d11.
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I'm an idiot. This patch wasn't supposed to be pushed yet because
not finished. Reverting it for the time being.
This reverts commit 89cc8c38c1cf3865c3684e5bd6658eedf0e61cfd.
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secfix directory removed (patches merged upstream)
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The release archives will be bigger, but this is a necessary change
that makes libreboot development easier.
At present, there are boards maintained in libreboot by different
people. By doing it this way, that becomes much easier. This is in
contrast to the present situation, where a change to one board
potentially affects all other boards, especially when updating to
a new version of coreboot.
Coreboot-libre scripts, download scripts, build scripts - everything.
The entire build system has been modified to reflect this change
of development.
For reasons of consistency, cbfstool and nvramtool are no longer
included in the util archives.
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Use older version of Alexander's patches, for now. Wait until
the final versions are merged upstream in GRUB.
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This reverts commit 6278d578f6f47ae2d2742b95c99df087a06d0e90.
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This reverts commit 26d16fa5cdc9e351fcb582104cf8c7b3bf9ddaf0.
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Not all CrOS devices are Chromebooks (laptops) or run on ARM, not all RK3288
CrOS devices are Chromebooks, either.
We want to support more CrOS devices, including some that are not Chromebooks,
such as the ASUS Chromebit!
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
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Temporary fix for build error.
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Also contains other fixes from coreboot, like:
* 551cff0 Derive lvds_dual_channel from EDID timings.
^ makes single/dual channel LVDS selection on GM45 automatic
* 26fc544 lenovo/t60: Enable native intel gfx init.
^ was being maintained in libreboot, now upstreamed so not needed
Framebuffer mode was disabled for the KGPE-D16, because only
text-mode works at the moment.
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coreboot build errors:
In file included from src/northbridge/amd/amdfam10/misc_control.c:35:0:
src/include/option.h:13:27: error: static declaration of 'get_option' follows non-static declaration
static inline enum cb_err get_option(void *dest, const char *name)
^
In file included from src/northbridge/amd/amdfam10/misc_control.c:34:0:
src/include/pc80/mc146818rtc.h:176:13: note: previous declaration of 'get_option' was here
enum cb_err get_option(void *dest, const char *name);
Ping tpearson about this.
Also ping him about the fact that there isn't actually an option to
enable or disable native graphics initialization, but that the option
MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG is in fact available and set to Y in the
Kconfig file. I think this is probably since there isn't even an option
ROM available for the machine, so it's pointless to offer the setting.
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This introduces Libreboot support for the Asus Chromebook C201 (codename
veyron_speedy). At this point, this produces a standalone Libreboot image that
can be flashed to the RO Coreboot partition of the SPI flash, as well as the
Libreboot version that can be flash to the RO Firmware ID partition.
Libreboot on the Chromebook C201 uses the depthcharge bootloader, modified to
display text messages instead of ChromeOS bitmaps (that encourage the use of
ChromeOS).
For convenience, an installation script, chromebook-flash-replace, is provided
along with a description of the flash layout, to ease the replacement of the
Coreboot and RO Firmware ID partitions on the full SPI flash image.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
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More microcode blobs were deleted upstream, which are therefore no
longer deleted by coreboot-libre.
util/broadcom/secimage/misc.c is not a blob.
Some non-blobs were deleted upstream, which are therefore no
longer listed in libreboot's nonblobs list.
New non-blobs were found, added to the nonblobs list.
vboot submodule was added, since there are parts of it that
cbfstool needs. This submodule is now deblobbed by libreboot.
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The ich9deblob and ich9gen utilities were modified, so that they
support reading and/or writing descriptor images where the GbE
region is not defined. These utilities were also re-factored
and tidied up a bit.
A quick was noticed during the course of this work, in that
Compenent 1 Density was being set to 8MiB constantly, even
on systems with 4MiB flash chips. Component 2 Density was
set statically to 2MiB. ich9gen now sets both to 4MiB or 8MiB,
depending on whether building the descriptor for a 4MiB or
8MiB ROM image.
There are still some ACPI bugs (see docs/hcl/r500.html), which
will have to be fixed upstream. TODO: get hw reg dumps from
a factory R500, and compare with the X200 or T400 dumps.
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Resetting to those commits already implies that they are correct,
because git already does integrity checking.
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