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-rw-r--r--resources/libreboot/patch/0000_x60t_digitizer_irda.git.diff (renamed from resources/libreboot/patch/gitdiff)55
-rw-r--r--resources/libreboot/patch/0001_i945_3dfix.git.diff37
-rw-r--r--resources/libreboot/patch/0002_x60_backlight.diff4
-rw-r--r--resources/libreboot/patch/0003_t60_backlight.diff4
4 files changed, 45 insertions, 55 deletions
diff --git a/resources/libreboot/patch/gitdiff b/resources/libreboot/patch/0000_x60t_digitizer_irda.git.diff
index 9aec941..11010d5 100644
--- a/resources/libreboot/patch/gitdiff
+++ b/resources/libreboot/patch/0000_x60t_digitizer_irda.git.diff
@@ -341,15 +341,6 @@ diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/d
index 54b7da3..f13cb3a 100644
--- a/src/mainboard/lenovo/t60/devicetree.cb
+++ b/src/mainboard/lenovo/t60/devicetree.cb
-@@ -25,7 +25,7 @@ chip northbridge/intel/i945
- register "gpu_hotplug" = "0x00000220"
- register "gpu_lvds_use_spread_spectrum_clock" = "1"
- register "gpu_lvds_is_dual_channel" = "1"
-- register "gpu_backlight" = "0x1280128"
-+ register "gpu_backlight" = "0x58BF58BE"
-
- device cpu_cluster 0 on
- chip cpu/intel/socket_mFCPGA478
@@ -153,6 +153,10 @@ chip northbridge/intel/i945
chip superio/nsc/pc87382
device pnp 164e.2 on # IR
@@ -499,15 +490,6 @@ diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/d
index dc1c5da..6f9d5d9 100644
--- a/src/mainboard/lenovo/x60/devicetree.cb
+++ b/src/mainboard/lenovo/x60/devicetree.cb
-@@ -25,7 +25,7 @@ chip northbridge/intel/i945
- register "gpu_hotplug" = "0x00000220"
- register "gpu_lvds_use_spread_spectrum_clock" = "1"
- register "gpu_lvds_is_dual_channel" = "0"
-- register "gpu_backlight" = "0x1280128"
-+ register "gpu_backlight" = "0x879F879E"
-
- device cpu_cluster 0 on
- chip cpu/intel/socket_mFCPGA478
@@ -130,10 +130,17 @@ chip northbridge/intel/i945
chip superio/nsc/pc87382
device pnp 164e.2 on # IR
@@ -541,40 +523,3 @@ index 1198fb2..8eca464 100644
/* range 0x1600 - 0x167f */
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x1601);
-diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
-index 4dd2ccf..5dbaff3 100644
---- a/src/northbridge/intel/i945/gma.c
-+++ b/src/northbridge/intel/i945/gma.c
-@@ -33,6 +33,8 @@
-
- #define GDRST 0xc0
-
-+#define BSM 0x5c
-+
- #define LVDS_CLOCK_A_POWERUP_ALL (3 << 8)
- #define LVDS_CLOCK_B_POWERUP_ALL (3 << 4)
- #define LVDS_CLOCK_BOTH_POWERUP_ALL (3 << 2)
-@@ -51,11 +53,19 @@
- static int gtt_setup(unsigned int mmiobase)
- {
- unsigned long PGETBL_save;
--
-- PGETBL_save = read32(mmiobase + PGETBL_CTL) & ~PGETBL_ENABLED;
-+ unsigned long tom; // top of memory
-+
-+ /*
-+ * The Video BIOS places the GTT right below top of memory.
-+ * It is not documented in the Intel 945 datasheet, but the Intel
-+ * developers said that it is normally placed there.
-+ *
-+ * TODO: Add option to make the GTT size runtime
-+ * configurable
-+ */
-+ tom = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), TOLUD) << 24;
-+ PGETBL_save = tom - 256 * KiB;
- PGETBL_save |= PGETBL_ENABLED;
--
-- PGETBL_save |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), 0x5c) & 0xfffff000;
- PGETBL_save |= 2; /* set GTT to 256kb */
-
- write32(mmiobase + GFX_FLSH_CNTL, 0);
diff --git a/resources/libreboot/patch/0001_i945_3dfix.git.diff b/resources/libreboot/patch/0001_i945_3dfix.git.diff
new file mode 100644
index 0000000..f417339
--- /dev/null
+++ b/resources/libreboot/patch/0001_i945_3dfix.git.diff
@@ -0,0 +1,37 @@
+diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
+index 4dd2ccf..5dbaff3 100644
+--- a/src/northbridge/intel/i945/gma.c
++++ b/src/northbridge/intel/i945/gma.c
+@@ -33,6 +33,8 @@
+
+ #define GDRST 0xc0
+
++#define BSM 0x5c
++
+ #define LVDS_CLOCK_A_POWERUP_ALL (3 << 8)
+ #define LVDS_CLOCK_B_POWERUP_ALL (3 << 4)
+ #define LVDS_CLOCK_BOTH_POWERUP_ALL (3 << 2)
+@@ -51,11 +53,19 @@
+ static int gtt_setup(unsigned int mmiobase)
+ {
+ unsigned long PGETBL_save;
+-
+- PGETBL_save = read32(mmiobase + PGETBL_CTL) & ~PGETBL_ENABLED;
++ unsigned long tom; // top of memory
++
++ /*
++ * The Video BIOS places the GTT right below top of memory.
++ * It is not documented in the Intel 945 datasheet, but the Intel
++ * developers said that it is normally placed there.
++ *
++ * TODO: Add option to make the GTT size runtime
++ * configurable
++ */
++ tom = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), TOLUD) << 24;
++ PGETBL_save = tom - 256 * KiB;
+ PGETBL_save |= PGETBL_ENABLED;
+-
+- PGETBL_save |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), 0x5c) & 0xfffff000;
+ PGETBL_save |= 2; /* set GTT to 256kb */
+
+ write32(mmiobase + GFX_FLSH_CNTL, 0);
diff --git a/resources/libreboot/patch/0002_x60_backlight.diff b/resources/libreboot/patch/0002_x60_backlight.diff
new file mode 100644
index 0000000..d787db5
--- /dev/null
+++ b/resources/libreboot/patch/0002_x60_backlight.diff
@@ -0,0 +1,4 @@
+28c28
+< register "gpu_backlight" = "0x1280128"
+---
+> register "gpu_backlight" = "0x879F879E"
diff --git a/resources/libreboot/patch/0003_t60_backlight.diff b/resources/libreboot/patch/0003_t60_backlight.diff
new file mode 100644
index 0000000..2d1a396
--- /dev/null
+++ b/resources/libreboot/patch/0003_t60_backlight.diff
@@ -0,0 +1,4 @@
+28c28
+< register "gpu_backlight" = "0x1280128"
+---
+> register "gpu_backlight" = "0x58BF58BE"