diff options
Diffstat (limited to 'resources/libreboot/patch/misc')
9 files changed, 696 insertions, 0 deletions
diff --git a/resources/libreboot/patch/misc/0001-mainboard-lenovo-t400-Add-initial-hybrid-graphics-su.patch b/resources/libreboot/patch/misc/0001-mainboard-lenovo-t400-Add-initial-hybrid-graphics-su.patch new file mode 100644 index 0000000..dae11e4 --- /dev/null +++ b/resources/libreboot/patch/misc/0001-mainboard-lenovo-t400-Add-initial-hybrid-graphics-su.patch @@ -0,0 +1,232 @@ +From 82d185307ef39c0ee9a95806a2f21679479721b4 Mon Sep 17 00:00:00 2001 +From: Timothy Pearson <tpearson@raptorengineeringinc.com> +Date: Sun, 5 Apr 2015 18:10:09 -0500 +Subject: [PATCH 1/9] mainboard/lenovo/t400: Add initial hybrid graphics + support + +TEST: Booted T400 with Intel/ATI hybrid graphics in integrated +mode with native Intel graphics init and verified integrated +panel framebuffer functionality in SeaBIOS and Linux. + +Change-Id: I37e72c5dad0d7ab3915cc3d439ae9a4a9b3787e3 +Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> +--- + src/mainboard/lenovo/t400/cmos.default | 1 + + src/mainboard/lenovo/t400/cmos.layout | 8 +- + src/mainboard/lenovo/t400/romstage.c | 143 +++++++++++++++++++++++++++++++++ + 3 files changed, 151 insertions(+), 1 deletion(-) + +diff --git a/src/mainboard/lenovo/t400/cmos.default b/src/mainboard/lenovo/t400/cmos.default +index 67b8920..06eec57 100644 +--- a/src/mainboard/lenovo/t400/cmos.default ++++ b/src/mainboard/lenovo/t400/cmos.default +@@ -14,3 +14,4 @@ sticky_fn=Disable + power_management_beeps=Enable + low_battery_beep=Enable + sata_mode=AHCI ++hybrid_graphics_mode=Integrated Only +\ No newline at end of file +diff --git a/src/mainboard/lenovo/t400/cmos.layout b/src/mainboard/lenovo/t400/cmos.layout +index 2dc91bf..44f5d04 100644 +--- a/src/mainboard/lenovo/t400/cmos.layout ++++ b/src/mainboard/lenovo/t400/cmos.layout +@@ -85,7 +85,10 @@ entries + # coreboot config options: northbridge + 941 3 e 11 gfx_uma_size + +-#944 2 r 0 unused ++# coreboot config options: graphics ++944 2 e 12 hybrid_graphics_mode ++ ++#946 2 r 0 unused + + # coreboot config options: check sums + 984 16 h 0 check_sum +@@ -137,6 +140,9 @@ enumerations + 11 3 128M + 11 5 96M + 11 6 160M ++12 0 Integrated Only ++12 1 Discrete Only ++12 2 Switchable + + # ----------------------------------------------------------------- + checksums +diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c +index a739d18..c62df60 100644 +--- a/src/mainboard/lenovo/t400/romstage.c ++++ b/src/mainboard/lenovo/t400/romstage.c +@@ -1,6 +1,7 @@ + /* + * This file is part of the coreboot project. + * ++ * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or +@@ -37,6 +38,118 @@ + #define LPC_DEV PCI_DEV(0, 0x1f, 0) + #define MCH_DEV PCI_DEV(0, 0, 0) + ++#define HYBRID_GRAPHICS_INTEGRATED_ONLY 0 ++#define HYBRID_GRAPHICS_DISCRETE_ONLY 1 ++#define HYBRID_GRAPHICS_SWITCHABLE 2 ++ ++#define HYBRID_GRAPHICS_GP_LVL_BITS 0x004a0000 ++#define HYBRID_GRAPHICS_GP_LVL2_BITS 0x00020000 ++ ++#define HYBRID_GRAPHICS_DETECT_GP_BITS 0x00000010 ++ ++#define HYBRID_GRAPHICS_INT_CLAIM_VGA 0x2 ++#define HYBRID_GRAPHICS_SEC_VGA_EN 0x2 ++ ++static void hybrid_graphics_configure_switchable_graphics(bool enable) ++{ ++ uint32_t tmp; ++ ++ if (enable) { ++ /* Disable integrated graphics legacy VGA cycles */ ++ tmp = pci_read_config16(MCH_DEV, D0F0_GGC); ++ pci_write_config16(MCH_DEV, D0F0_GGC, tmp | HYBRID_GRAPHICS_INT_CLAIM_VGA); ++ ++ /* Enable secondary VGA controller */ ++ tmp = pci_read_config16(MCH_DEV, D0F0_DEVEN); ++ pci_write_config16(MCH_DEV, D0F0_DEVEN, tmp | HYBRID_GRAPHICS_SEC_VGA_EN); ++ } ++ else { ++ /* Enable integrated graphics legacy VGA cycles */ ++ tmp = pci_read_config16(MCH_DEV, D0F0_GGC); ++ pci_write_config16(MCH_DEV, D0F0_GGC, tmp & ~HYBRID_GRAPHICS_INT_CLAIM_VGA); ++ ++ /* Disable secondary VGA controller */ ++ tmp = pci_read_config16(MCH_DEV, D0F0_DEVEN); ++ pci_write_config16(MCH_DEV, D0F0_DEVEN, tmp & ~HYBRID_GRAPHICS_SEC_VGA_EN); ++ } ++} ++ ++static void hybrid_graphics_set_up_gpio(void) ++{ ++ uint32_t tmp; ++ ++ /* Enable hybrid graphics GPIO lines */ ++ tmp = inl(DEFAULT_GPIOBASE + GP_IO_USE_SEL); ++ tmp = tmp | HYBRID_GRAPHICS_GP_LVL_BITS; ++ outl(tmp, DEFAULT_GPIOBASE + GP_IO_USE_SEL); ++ ++ tmp = inl(DEFAULT_GPIOBASE + GP_IO_USE_SEL2); ++ tmp = tmp | HYBRID_GRAPHICS_GP_LVL2_BITS; ++ outl(tmp, DEFAULT_GPIOBASE + GP_IO_USE_SEL2); ++ ++ /* Set hybrid graphics control GPIO lines to output */ ++ tmp = inl(DEFAULT_GPIOBASE + GP_IO_SEL); ++ tmp = tmp & ~HYBRID_GRAPHICS_GP_LVL_BITS; ++ outl(tmp, DEFAULT_GPIOBASE + GP_IO_SEL); ++ ++ tmp = inl(DEFAULT_GPIOBASE + GP_IO_SEL2); ++ tmp = tmp & ~HYBRID_GRAPHICS_GP_LVL2_BITS; ++ outl(tmp, DEFAULT_GPIOBASE + GP_IO_SEL2); ++ ++ /* Set hybrid graphics detect GPIO lines to input */ ++ tmp = inl(DEFAULT_GPIOBASE + GP_IO_SEL); ++ tmp = tmp | HYBRID_GRAPHICS_DETECT_GP_BITS; ++ outl(tmp, DEFAULT_GPIOBASE + GP_IO_SEL); ++} ++ ++static bool hybrid_graphics_installed(void) ++{ ++ if (inl(DEFAULT_GPIOBASE + GP_LVL) & HYBRID_GRAPHICS_DETECT_GP_BITS) ++ return false; ++ else ++ return true; ++} ++ ++static void hybrid_graphics_switch_to_integrated_graphics(void) ++{ ++ uint32_t tmp; ++ ++ /* Disable switchable graphics */ ++ hybrid_graphics_configure_switchable_graphics(false); ++ ++ /* Configure muxes */ ++ tmp = inl(DEFAULT_GPIOBASE + GP_LVL); ++ tmp = tmp & ~HYBRID_GRAPHICS_GP_LVL_BITS; ++ outl(tmp, DEFAULT_GPIOBASE + GP_LVL); ++ ++ tmp = inl(DEFAULT_GPIOBASE + GP_LVL2); ++ tmp = tmp & ~HYBRID_GRAPHICS_GP_LVL2_BITS; ++ outl(tmp, DEFAULT_GPIOBASE + GP_LVL2); ++} ++ ++static void hybrid_graphics_switch_to_discrete_graphics(void) ++{ ++ uint32_t tmp; ++ ++ /* Disable switchable graphics */ ++ hybrid_graphics_configure_switchable_graphics(false); ++ ++ /* Configure muxes */ ++ tmp = inl(DEFAULT_GPIOBASE + GP_LVL); ++ tmp = tmp | HYBRID_GRAPHICS_GP_LVL_BITS; ++ outl(tmp, DEFAULT_GPIOBASE + GP_LVL); ++ ++ tmp = inl(DEFAULT_GPIOBASE + GP_LVL2); ++ tmp = tmp | HYBRID_GRAPHICS_GP_LVL2_BITS; ++ outl(tmp, DEFAULT_GPIOBASE + GP_LVL2); ++} ++ ++static void hybrid_graphics_switch_to_dual_graphics(void) ++{ ++ /* Enable switchable graphics */ ++ hybrid_graphics_configure_switchable_graphics(true); ++} ++ + static void default_southbridge_gpio_setup(void) + { + outl(0x197e23fe, DEFAULT_GPIOBASE + GP_IO_USE_SEL); +@@ -98,6 +211,31 @@ void main(unsigned long bist) + + default_southbridge_gpio_setup(); + ++ uint8_t hybrid_graphics_mode = HYBRID_GRAPHICS_INTEGRATED_ONLY; ++ get_option(&hybrid_graphics_mode, "hybrid_graphics_mode"); ++ ++ /* Set up hybrid graphics */ ++ hybrid_graphics_set_up_gpio(); ++ if (hybrid_graphics_installed()) { ++ /* Select appropriate hybrid graphics device */ ++ printk(BIOS_DEBUG, "Hybrid graphics available, setting mode %d\n", hybrid_graphics_mode); ++ if (hybrid_graphics_mode == HYBRID_GRAPHICS_INTEGRATED_ONLY) ++ hybrid_graphics_switch_to_integrated_graphics(); ++ else if (hybrid_graphics_mode == HYBRID_GRAPHICS_DISCRETE_ONLY) ++ hybrid_graphics_switch_to_discrete_graphics(); ++ else if (hybrid_graphics_mode == HYBRID_GRAPHICS_SWITCHABLE) ++ hybrid_graphics_switch_to_integrated_graphics(); ++ /* Switchable graphics are fully enabled after raminit */ ++ /* FIXME ++ * Enabling switchable graphics prevents bootup! ++ * Debug and fix appropriately... ++ */ ++ } ++ else { ++ printk(BIOS_DEBUG, "Hybrid graphics not installed\n"); ++ hybrid_graphics_switch_to_integrated_graphics(); ++ } ++ + /* ASPM related setting, set early by original BIOS. */ + DMIBAR16(0x204) &= ~(3 << 10); + +@@ -177,6 +315,11 @@ void main(unsigned long bist) + outl(inl(DEFAULT_GPIOBASE + 0x38) & ~0x400, DEFAULT_GPIOBASE + 0x38); + + cbmem_initted = !cbmem_recovery(s3resume); ++ ++ if (hybrid_graphics_installed()) ++ if (hybrid_graphics_mode == HYBRID_GRAPHICS_SWITCHABLE) ++ hybrid_graphics_switch_to_dual_graphics(); ++ + #if CONFIG_HAVE_ACPI_RESUME + /* If there is no high memory area, we didn't boot before, so + * this is not a resume. In that case we just create the cbmem toc. +-- +1.9.1 + diff --git a/resources/libreboot/patch/misc/0002-NOTFORMERGE-lenovo-t400-hard-code-enable-integrated-.patch b/resources/libreboot/patch/misc/0002-NOTFORMERGE-lenovo-t400-hard-code-enable-integrated-.patch new file mode 100644 index 0000000..4bda8e7 --- /dev/null +++ b/resources/libreboot/patch/misc/0002-NOTFORMERGE-lenovo-t400-hard-code-enable-integrated-.patch @@ -0,0 +1,36 @@ +From 6e7cdcaa317f9fdea329839b1e6e6343cd45b642 Mon Sep 17 00:00:00 2001 +From: Francis Rowe <info@gluglug.org.uk> +Date: Mon, 15 Jun 2015 03:44:15 +0100 +Subject: [PATCH 2/9] NOTFORMERGE: lenovo/t400: hard-code enable + integrated-only video + +Written with libreboot in mind. Libreboot uses native graphics +initialization only, so we want to ensure that these systems +only use the integrated (Intel) GPU for which native init exists. + +Native graphics initialization does not yet exist for the ATI GPUs +on these laptops... + +Change-Id: I2c056a8fb498972f87c4ec1122b239fdc9a4c666 +Signed-off-by: Francis Rowe <info@gluglug.org.uk> +--- + src/mainboard/lenovo/t400/romstage.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c +index c62df60..daf6fa8 100644 +--- a/src/mainboard/lenovo/t400/romstage.c ++++ b/src/mainboard/lenovo/t400/romstage.c +@@ -212,7 +212,8 @@ void main(unsigned long bist) + default_southbridge_gpio_setup(); + + uint8_t hybrid_graphics_mode = HYBRID_GRAPHICS_INTEGRATED_ONLY; +- get_option(&hybrid_graphics_mode, "hybrid_graphics_mode"); ++ /* Not for merge! Hard-code enable integrated-only by commenting this line: */ ++ /* get_option(&hybrid_graphics_mode, "hybrid_graphics_mode"); */ + + /* Set up hybrid graphics */ + hybrid_graphics_set_up_gpio(); +-- +1.9.1 + diff --git a/resources/libreboot/patch/misc/0003-lenovo-x60-use-correct-BLC_PWM_CTL-value.patch b/resources/libreboot/patch/misc/0003-lenovo-x60-use-correct-BLC_PWM_CTL-value.patch new file mode 100644 index 0000000..4afc7f5 --- /dev/null +++ b/resources/libreboot/patch/misc/0003-lenovo-x60-use-correct-BLC_PWM_CTL-value.patch @@ -0,0 +1,31 @@ +From e4b5b65c93122126344771f2042f8d7a3468be19 Mon Sep 17 00:00:00 2001 +From: Francis Rowe <info@gluglug.org.uk> +Date: Mon, 22 Jun 2015 17:37:06 +0100 +Subject: [PATCH 3/9] lenovo/x60: use correct BLC_PWM_CTL value + +Bit 16 in BLC_PWM_CTL enables brightness controls, but the +current value is generic. Use the proper value, obtained +by reading BLC_PWM_CTL while running the VBIOS. + +Change-Id: Ib273359e1c285b405a9bb26fc217c2f7e255b99f +Signed-off-by: Francis Rowe <info@gluglug.org.uk> +--- + src/mainboard/lenovo/x60/devicetree.cb | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb +index b4d1144..4d62116 100644 +--- a/src/mainboard/lenovo/x60/devicetree.cb ++++ b/src/mainboard/lenovo/x60/devicetree.cb +@@ -26,7 +26,7 @@ chip northbridge/intel/i945 + + register "gpu_hotplug" = "0x00000220" + register "gpu_lvds_use_spread_spectrum_clock" = "1" +- register "gpu_backlight" = "0x1290128" ++ register "gpu_backlight" = "0x879F879E" + + device cpu_cluster 0 on + chip cpu/intel/socket_mFCPGA478 +-- +1.9.1 + diff --git a/resources/libreboot/patch/misc/0004-lenovo-t60-Enable-brightness-controls-native-graphic.patch b/resources/libreboot/patch/misc/0004-lenovo-t60-Enable-brightness-controls-native-graphic.patch new file mode 100644 index 0000000..ec6b33e --- /dev/null +++ b/resources/libreboot/patch/misc/0004-lenovo-t60-Enable-brightness-controls-native-graphic.patch @@ -0,0 +1,36 @@ +From 770021ce66a0fddebb9639c4df0696ecfca45488 Mon Sep 17 00:00:00 2001 +From: Francis Rowe <info@gluglug.org.uk> +Date: Mon, 15 Jun 2015 19:59:46 +0100 +Subject: [PATCH 4/9] lenovo/t60: Enable brightness controls (native graphics) + +This makes the Fn Home/End keys work for controlling the +brightness of the display. Value obtained by reading +BLC_PWM_CTL when running the VBIOS (option ROM). + +On i945 legacy brightness control is enabled by a single +bit in BLC_PWM_CTL. It's bit 16 or bit 0 (the other one +reverses polarity). Set the bit to enable brightness +controls. + +Change-Id: I22e261f2ce28ec81cd208a73e6311ec67146eb72 +Signed-off-by: Francis Rowe <info@gluglug.org.uk> +--- + src/mainboard/lenovo/t60/devicetree.cb | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb +index b28f1ad..9e6ce02 100644 +--- a/src/mainboard/lenovo/t60/devicetree.cb ++++ b/src/mainboard/lenovo/t60/devicetree.cb +@@ -26,7 +26,7 @@ chip northbridge/intel/i945 + + register "gpu_hotplug" = "0x00000220" + register "gpu_lvds_use_spread_spectrum_clock" = "1" +- register "gpu_backlight" = "0x1280128" ++ register "gpu_backlight" = "0x58BF58BE" + + device cpu_cluster 0 on + chip cpu/intel/socket_mFCPGA478 +-- +1.9.1 + diff --git a/resources/libreboot/patch/misc/0005-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch b/resources/libreboot/patch/misc/0005-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch new file mode 100644 index 0000000..b088d3e --- /dev/null +++ b/resources/libreboot/patch/misc/0005-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch @@ -0,0 +1,88 @@ +From 1024b5e6c476dcc195dca742746735277f63236b Mon Sep 17 00:00:00 2001 +From: Francis Rowe <info@gluglug.org.uk> +Date: Mon, 13 Oct 2014 00:14:53 +0100 +Subject: [PATCH 5/9] NOTFORMERGE: ec/lenovo/h8: + wlan/trackpoint/touchpad/bluetooth/wwan + +Permanently enable them. + +Change-Id: Ic76ab9ab9c865f30312378e18af58bece6c3260a +Signed-off-by: Francis Rowe <info@gluglug.org.uk> +--- + src/ec/lenovo/h8/h8.c | 21 +++++++++++---------- + src/ec/lenovo/pmh7/pmh7.c | 11 ++++------- + 2 files changed, 15 insertions(+), 17 deletions(-) + +diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c +index 2cafc88..a6cb6b6 100644 +--- a/src/ec/lenovo/h8/h8.c ++++ b/src/ec/lenovo/h8/h8.c +@@ -255,9 +255,11 @@ static void h8_enable(struct device *dev) + + ec_write(H8_FAN_CONTROL, H8_FAN_CONTROL_AUTO); + +- if (get_option(&val, "wlan") != CB_SUCCESS) +- val = 1; +- h8_wlan_enable(val); ++ // Permanently enable wifi ++ // Intel wifi could be a security risk because it uses firmware. Wlan chip has DMA ++ // and could leak data over a side-channel. Using another manufacturer is recommended. ++ // see http://libreboot.org/docs/index.html#recommended_wifi ++ h8_wlan_enable(1); + + h8_trackpoint_enable(1); + h8_usb_power_enable(1); +@@ -265,14 +267,13 @@ static void h8_enable(struct device *dev) + if (get_option(&val, "volume") == CB_SUCCESS) + ec_write(H8_VOLUME_CONTROL, val); + +- if (get_option(&val, "bluetooth") != CB_SUCCESS) +- val = 1; +- h8_bluetooth_enable(val); +- +- if (get_option(&val, "wwan") != CB_SUCCESS) +- val = 1; ++ // Permanently enable bluetooth. ++ // NOTE: bluetooth is a potential security risk. Physical removal of the bluetooth module is recommended. ++ h8_bluetooth_enable(1); + +- h8_wwan_enable(val); ++ // Permanently enable wwan. ++ // NOTE: wwan is a security risk (remove access plus DMA). Physical removal of both the wwan and sim card is recommended. ++ h8_wwan_enable(1); + + if (conf->has_uwb) { + if (get_option(&val, "uwb") != CB_SUCCESS) +diff --git a/src/ec/lenovo/pmh7/pmh7.c b/src/ec/lenovo/pmh7/pmh7.c +index cc6e891..38aef16 100644 +--- a/src/ec/lenovo/pmh7/pmh7.c ++++ b/src/ec/lenovo/pmh7/pmh7.c +@@ -106,7 +106,6 @@ static void enable_dev(struct device *dev) + { + struct ec_lenovo_pmh7_config *conf = dev->chip_info; + struct resource *resource; +- u8 val; + + resource = new_resource(dev, EC_LENOVO_PMH7_INDEX); + resource->flags = IORESOURCE_IO | IORESOURCE_FIXED; +@@ -118,13 +117,11 @@ static void enable_dev(struct device *dev) + pmh7_backlight_enable(conf->backlight_enable); + pmh7_dock_event_enable(conf->dock_event_enable); + +- if (get_option(&val, "touchpad") != CB_SUCCESS) +- val = 1; +- pmh7_touchpad_enable(val); ++ // Permanently enable touchpad ++ pmh7_touchpad_enable(1); + +- if (get_option(&val, "trackpoint") != CB_SUCCESS) +- val = 1; +- pmh7_trackpoint_enable(val); ++ // Permanently enable trackpoint ++ pmh7_trackpoint_enable(1); + } + + struct chip_operations ec_lenovo_pmh7_ops = { +-- +1.9.1 + diff --git a/resources/libreboot/patch/misc/0006-northbridge-gm45-raminit.c-enable-GS45-high-performa.patch b/resources/libreboot/patch/misc/0006-northbridge-gm45-raminit.c-enable-GS45-high-performa.patch new file mode 100644 index 0000000..33b7978 --- /dev/null +++ b/resources/libreboot/patch/misc/0006-northbridge-gm45-raminit.c-enable-GS45-high-performa.patch @@ -0,0 +1,52 @@ +From 115b09a63d1e5eb07d8c12a6c5369c1577b41f42 Mon Sep 17 00:00:00 2001 +From: Steve Shenton <sgsit@libreboot.org> +Date: Fri, 7 Aug 2015 08:22:27 +0100 +Subject: [PATCH 6/9] northbridge/gm45/raminit.c: enable GS45 high-performance + mode + +The datasheets for GS45 describe a high- and low-performance mode +for different CPUs. Coreboot currently disables GS45 altogether, +but forcing coreboot to treat high-performance GS45 as GM45 makes +the X200S and X200 Tablet boot if it has the right CPU type. + +Hardcode-enable GS45 high-performance mode in coreboot, passing it +off as GM45. This is known to work with all CPUs except the SU +(low performance) models. + +The low-performance models are unsupported anyway, requiring +extensive work on the raminit. For now, this patch increases +compatibility to a whole new chipset (GS45), depending on the CPU. + +Change-Id: I2719385e93c37d254ce38e0f5f486262160234e1 +Signed-off-by: Steve Shenton <sgsit@libreboot.org> +Signed-off-by: Francis Rowe <info@gluglug.org.uk> +--- + src/northbridge/intel/gm45/raminit.c | 5 ++--- + 1 file changed, 2 insertions(+), 3 deletions(-) + +diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c +index 9c4fecd..1614b7c 100644 +--- a/src/northbridge/intel/gm45/raminit.c ++++ b/src/northbridge/intel/gm45/raminit.c +@@ -108,8 +108,7 @@ void get_gmch_info(sysinfo_t *sysinfo) + printk(BIOS_SPEW, "GMCH: GS40\n"); + break; + case GMCH_GS45: +- printk(BIOS_SPEW, "GMCH: GS45, using low power mode by default\n"); +- sysinfo->gs45_low_power_mode = 1; ++ printk(BIOS_SPEW, "GMCH: GS45, using high performance mode by default\n"); + break; + case GMCH_PM45: + printk(BIOS_SPEW, "GMCH: PM45\n"); +@@ -1692,7 +1691,7 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume) + { + const dimminfo_t *const dimms = sysinfo->dimms; + const timings_t *const timings = &sysinfo->selected_timings; +- const int sff = sysinfo->gfx_type == GMCH_GS45; ++ const int sff = (sysinfo->gfx_type == GMCH_GS45) && (sysinfo->gs45_low_power_mode == 1); + + int ch; + u8 reg8; +-- +1.9.1 + diff --git a/resources/libreboot/patch/misc/0007-lenovo-r400-Add-clone-of-Lenovo-T400.patch b/resources/libreboot/patch/misc/0007-lenovo-r400-Add-clone-of-Lenovo-T400.patch new file mode 100644 index 0000000..8e4f61a --- /dev/null +++ b/resources/libreboot/patch/misc/0007-lenovo-r400-Add-clone-of-Lenovo-T400.patch @@ -0,0 +1,86 @@ +From 199e542660a3a9947051485fa1b5b8f6e2fd6495 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Micha=C5=82=20Mas=C5=82owski?= <mtjm@mtjm.eu> +Date: Tue, 3 Feb 2015 23:26:05 +0100 +Subject: [PATCH 7/9] lenovo/r400: Add clone of Lenovo T400 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The existing code for the Lenovo T400 works without changes on the +Lenovo R400. Same HDA verbs are provided by Lenovo BIOS on both +laptops. + +Change-Id: I1dadddd7250ab80a4c40c2435865d72e3e5d99c9 +Signed-off-by: Michał Masłowski <mtjm@mtjm.eu> +Signed-off-by: Francis Rowe <info@gluglug.org.uk> +--- + src/mainboard/lenovo/r400/Kconfig | 7 +++++++ + src/mainboard/lenovo/r400/Kconfig.name | 2 ++ + src/mainboard/lenovo/r400/board_info.txt | 6 ++++++ + src/mainboard/lenovo/t400/Kconfig | 6 +++++- + 4 files changed, 20 insertions(+), 1 deletion(-) + create mode 100644 src/mainboard/lenovo/r400/Kconfig + create mode 100644 src/mainboard/lenovo/r400/Kconfig.name + create mode 100644 src/mainboard/lenovo/r400/board_info.txt + +diff --git a/src/mainboard/lenovo/r400/Kconfig b/src/mainboard/lenovo/r400/Kconfig +new file mode 100644 +index 0000000..0966bf1 +--- /dev/null ++++ b/src/mainboard/lenovo/r400/Kconfig +@@ -0,0 +1,7 @@ ++if BOARD_LENOVO_R400 ++ ++config MAINBOARD_PART_NUMBER ++ string ++ default "ThinkPad R400" ++ ++endif +diff --git a/src/mainboard/lenovo/r400/Kconfig.name b/src/mainboard/lenovo/r400/Kconfig.name +new file mode 100644 +index 0000000..15a99b1 +--- /dev/null ++++ b/src/mainboard/lenovo/r400/Kconfig.name +@@ -0,0 +1,2 @@ ++config BOARD_LENOVO_R400 ++ bool "ThinkPad R400" +diff --git a/src/mainboard/lenovo/r400/board_info.txt b/src/mainboard/lenovo/r400/board_info.txt +new file mode 100644 +index 0000000..007ec6c +--- /dev/null ++++ b/src/mainboard/lenovo/r400/board_info.txt +@@ -0,0 +1,6 @@ ++Category: laptop ++ROM package: SOIC-16 or SOIC-8 ++ROM protocol: SPI ++ROM socketed: n ++Flashrom support: n ++Clone of: lenovo/t400 +diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig +index e410f20..467cd63 100644 +--- a/src/mainboard/lenovo/t400/Kconfig ++++ b/src/mainboard/lenovo/t400/Kconfig +@@ -1,4 +1,4 @@ +-if BOARD_LENOVO_T400 ++if BOARD_LENOVO_T400 || BOARD_LENOVO_R400 + + config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y +@@ -27,10 +27,14 @@ config MAINBOARD_DIR + string + default lenovo/t400 + ++if BOARD_LENOVO_T400 ++ + config MAINBOARD_PART_NUMBER + string + default "ThinkPad T400" + ++endif ++ + config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 +-- +1.9.1 + diff --git a/resources/libreboot/patch/misc/0008-lenovo-t500-Add-clone-of-Lenovo-T400.patch b/resources/libreboot/patch/misc/0008-lenovo-t500-Add-clone-of-Lenovo-T400.patch new file mode 100644 index 0000000..479905d --- /dev/null +++ b/resources/libreboot/patch/misc/0008-lenovo-t500-Add-clone-of-Lenovo-T400.patch @@ -0,0 +1,67 @@ +From 2a9b4169a25273dcf3c474c76455ab31d1e2839b Mon Sep 17 00:00:00 2001 +From: Francis Rowe <info@gluglug.org.uk> +Date: Sun, 14 Jun 2015 15:40:00 +0100 +Subject: [PATCH 8/9] lenovo/t500: Add clone of Lenovo T400 + +The existing code for the Lenovo T400 works without changes on the +Lenovo T500. Same HDA verbs are provided by Lenovo BIOS on both +laptops. + +Change-Id: I300408a8a0ed00476aee6061925befc2822fb505 +Signed-off-by: Francis Rowe <info@gluglug.org.uk> +--- + src/mainboard/lenovo/t400/Kconfig | 2 +- + src/mainboard/lenovo/t500/Kconfig | 7 +++++++ + src/mainboard/lenovo/t500/Kconfig.name | 2 ++ + src/mainboard/lenovo/t500/board_info.txt | 6 ++++++ + 4 files changed, 16 insertions(+), 1 deletion(-) + create mode 100644 src/mainboard/lenovo/t500/Kconfig + create mode 100644 src/mainboard/lenovo/t500/Kconfig.name + create mode 100644 src/mainboard/lenovo/t500/board_info.txt + +diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig +index 467cd63..0eac311 100644 +--- a/src/mainboard/lenovo/t400/Kconfig ++++ b/src/mainboard/lenovo/t400/Kconfig +@@ -1,4 +1,4 @@ +-if BOARD_LENOVO_T400 || BOARD_LENOVO_R400 ++if BOARD_LENOVO_T400 || BOARD_LENOVO_T500 || BOARD_LENOVO_R400 + + config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y +diff --git a/src/mainboard/lenovo/t500/Kconfig b/src/mainboard/lenovo/t500/Kconfig +new file mode 100644 +index 0000000..e1e8420 +--- /dev/null ++++ b/src/mainboard/lenovo/t500/Kconfig +@@ -0,0 +1,7 @@ ++if BOARD_LENOVO_T500 ++ ++config MAINBOARD_PART_NUMBER ++ string ++ default "ThinkPad T500" ++ ++endif +diff --git a/src/mainboard/lenovo/t500/Kconfig.name b/src/mainboard/lenovo/t500/Kconfig.name +new file mode 100644 +index 0000000..89c6087 +--- /dev/null ++++ b/src/mainboard/lenovo/t500/Kconfig.name +@@ -0,0 +1,2 @@ ++config BOARD_LENOVO_T500 ++ bool "ThinkPad T500" +diff --git a/src/mainboard/lenovo/t500/board_info.txt b/src/mainboard/lenovo/t500/board_info.txt +new file mode 100644 +index 0000000..007ec6c +--- /dev/null ++++ b/src/mainboard/lenovo/t500/board_info.txt +@@ -0,0 +1,6 @@ ++Category: laptop ++ROM package: SOIC-16 or SOIC-8 ++ROM protocol: SPI ++ROM socketed: n ++Flashrom support: n ++Clone of: lenovo/t400 +-- +1.9.1 + diff --git a/resources/libreboot/patch/misc/0009-chromeos-Allow-disabling-vboot-firmware-verification.patch b/resources/libreboot/patch/misc/0009-chromeos-Allow-disabling-vboot-firmware-verification.patch new file mode 100644 index 0000000..6df7636 --- /dev/null +++ b/resources/libreboot/patch/misc/0009-chromeos-Allow-disabling-vboot-firmware-verification.patch @@ -0,0 +1,68 @@ +From a5dba25113e8bd989b74763baabd7a07931fa314 Mon Sep 17 00:00:00 2001 +From: Paul Kocialkowski <contact@paulk.fr> +Date: Sun, 9 Aug 2015 10:23:38 +0200 +Subject: [PATCH 9/9] chromeos: Allow disabling vboot firmware verification + when ChromeOS is enabled + +Some ChromeOS bindings might be wanted without using vboot verification, for +instance to boot up depthcharge from the version of Coreboot installed in the +write-protected part of the SPI flash (without jumping to a RW firmware). + +Vboot firmware verification is still selected by default when ChromeOS is +enabled, but this allows more flexibility since vboot firmware verification is +no longer a hard requirement for ChromeOS (that this particular use case still +allows booting ChromeOS). + +In the future, it would make sense to have all the separate components that +CONFIG_CHROMEOS enables have their own config options, so that they can be +enabled separately. + +Change-Id: Ia4057a56838aa05dcf3cb250ae1a27fd91402ddb +Signed-off-by: Paul Kocialkowski <contact@paulk.fr> +--- + src/vendorcode/google/chromeos/Kconfig | 2 +- + src/vendorcode/google/chromeos/vboot2/Kconfig | 4 ++++ + 2 files changed, 5 insertions(+), 1 deletion(-) + +diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig +index 8309d19..694e0d7 100644 +--- a/src/vendorcode/google/chromeos/Kconfig ++++ b/src/vendorcode/google/chromeos/Kconfig +@@ -31,7 +31,6 @@ config CHROMEOS + select BOOTMODE_STRAPS + select ELOG + select COLLECT_TIMESTAMPS +- select VBOOT_VERIFY_FIRMWARE + help + Enable ChromeOS specific features like the GPIO sub table in + the coreboot table. NOTE: Enabling this option on an unsupported +@@ -129,6 +128,7 @@ config VIRTUAL_DEV_SWITCH + + config VBOOT_VERIFY_FIRMWARE + bool "Verify firmware with vboot." ++ default y if CHROMEOS + default n + depends on HAVE_HARD_RESET + help +diff --git a/src/vendorcode/google/chromeos/vboot2/Kconfig b/src/vendorcode/google/chromeos/vboot2/Kconfig +index 930b009..610a847 100644 +--- a/src/vendorcode/google/chromeos/vboot2/Kconfig ++++ b/src/vendorcode/google/chromeos/vboot2/Kconfig +@@ -16,6 +16,8 @@ + ## Foundation, Inc. + ## + ++if VBOOT_VERIFY_FIRMWARE ++ + config VBOOT_STARTS_IN_BOOTBLOCK + bool "Vboot starts verifying in bootblock" + default n +@@ -133,3 +135,5 @@ config VBOOT_DYNAMIC_WORK_BUFFER + ram to allocate the vboot work buffer. That means vboot verification + is after memory init and requires main memory to back the work + buffer. ++ ++endif # VBOOT_VERIFY_FIRMWARE +-- +1.9.1 + |