1 files changed, 0 insertions, 89 deletions
diff --git a/resources/libreboot/patch/coreboot/369b561315ca68d0cdedc38208105a513c7139b5/grub/kcma-d8/0012-northbridge-amd-amdmct-mct_ddr3-Enable-fast-refresh-.patch b/resources/libreboot/patch/coreboot/369b561315ca68d0cdedc38208105a513c7139b5/grub/kcma-d8/0012-northbridge-amd-amdmct-mct_ddr3-Enable-fast-refresh-.patch
deleted file mode 100644
index 36efd72..0000000
--- a/resources/libreboot/patch/coreboot/369b561315ca68d0cdedc38208105a513c7139b5/grub/kcma-d8/0012-northbridge-amd-amdmct-mct_ddr3-Enable-fast-refresh-.patch
+++ /dev/null
@@ -1,89 +0,0 @@
-From 2eb03f516b6555636282713527bf9f2e672bf97b Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <tpearson@raptorengineeringinc.com>
-Date: Tue, 24 Nov 2015 14:11:50 -0600
-Subject: [PATCH 12/45] northbridge/amd/amdmct/mct_ddr3: Enable fast refresh on
- ETR devices
-
-When an Extended Temperature Range DIMM is installed on a channel
-the refresh rate should be increased per the BKDG recommendations
-to allow correct operation at higher temperature ranges.
-
-Set fast refresh on a channel if an ETR DIMM is installed on that
-channel.
-
-Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
----
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 12 +++++++++++-
- src/northbridge/amd/amdmct/mct_ddr3/mct_d.h |  5 +++--
- 2 files changed, 14 insertions(+), 3 deletions(-)
-
-diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-index ac5220e..beb71f9 100644
---- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
-@@ -3993,6 +3993,7 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat,
- 	u32 DramTimingLo, DramTimingHi;
- 	u8 tCK16x;
- 	u16 Twtr;
-+	uint8_t Etr[2];
- 	u8 LDIMM;
- 	u8 MTB16x;
- 	u8 byte;
-@@ -4011,6 +4012,8 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat,
- 	Trc = 0;
- 	Twr = 0;
- 	Twtr = 0;
-+	for (i=0; i < 2; i++)
-+		Etr[i] = 0;
- 	for (i=0; i < 4; i++)
- 		Trfc[i] = 0;
- 	Tfaw = 0;
-@@ -4077,6 +4080,10 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat,
- 			val *= MTB16x;
- 			if (Tfaw < val)
- 				Tfaw = val;
-+
-+			/* Determine if the DIMMs on this channel support 95°C ETR */
-+			if (pDCTstat->spd_data.spd_bytes[dct + i][SPD_Thermal] & 0x1)
-+				Etr[dct] = 1;
- 		}	/* Dimm Present */
- 	}
- 
-@@ -4248,7 +4255,10 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat,
- 		dev = pDCTstat->dev_dct;
- 
- 		dword = Get_NB32_DCT(dev, dct, 0x8c);				/* DRAM Timing High */
--		val = 2;							/* Tref = 7.8us */
-+		if (Etr[dct])
-+			val = 3;						/* Tref = 3.9us */
-+		else
-+			val = 2;						/* Tref = 7.8us */
- 		dword &= ~(0x3 << 16);
- 		dword |= (val & 0x3) << 16;
- 		Set_NB32_DCT(dev, dct, 0x8c, dword);				/* DRAM Timing High */
-diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
-index 5f72ff3..e7361ac 100644
---- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
-+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
-@@ -217,8 +217,8 @@
- #define SPD_CASHigh		15
- #define SPD_tAAmin		16
- 
--#define SPD_DEVATTRIB	22
--#define SPD_EDCTYPE	11
-+#define SPD_DEVATTRIB		22
-+#define SPD_EDCTYPE		11
- 	#define JED_ADRCPAR	0x04
- 
- #define SPD_tWRmin		17
-@@ -232,6 +232,7 @@
- #define SPD_tRTPmin		27
- #define SPD_Upper_tFAW		28
- #define SPD_tFAWmin		29
-+#define SPD_Thermal		31
- 
- #define SPD_RefRawCard		62
- #define SPD_AddressMirror	63
--- 
-2.1.4
-