diff options
Diffstat (limited to 'resources/libreboot/patch/0002-northbridge-intel-gm45-gma-Add-backlight-control-reg.patch')
| -rw-r--r-- | resources/libreboot/patch/0002-northbridge-intel-gm45-gma-Add-backlight-control-reg.patch | 61 |
1 files changed, 61 insertions, 0 deletions
diff --git a/resources/libreboot/patch/0002-northbridge-intel-gm45-gma-Add-backlight-control-reg.patch b/resources/libreboot/patch/0002-northbridge-intel-gm45-gma-Add-backlight-control-reg.patch new file mode 100644 index 0000000..6be1246 --- /dev/null +++ b/resources/libreboot/patch/0002-northbridge-intel-gm45-gma-Add-backlight-control-reg.patch @@ -0,0 +1,61 @@ +From 9f3557bfdc06fc87e50f39336fe24a4c599a5c5d Mon Sep 17 00:00:00 2001 +From: Timothy Pearson <tpearson@raptorengineeringinc.com> +Date: Mon, 6 Apr 2015 22:01:23 -0500 +Subject: [PATCH 02/22] northbridge/intel/gm45/gma: Add backlight control + register field + +This allows the backlight control register to be set via devicetree.cb + +Change-Id: I32b42dfc1cc609fb6f8995c6158c85be67633770 +Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> +--- + src/drivers/intel/gma/i915.h | 1 + + src/northbridge/intel/gm45/gma.c | 8 ++++++-- + 2 files changed, 7 insertions(+), 2 deletions(-) + +diff --git a/src/drivers/intel/gma/i915.h b/src/drivers/intel/gma/i915.h +index 0d5b8af..36ac5fc 100644 +--- a/src/drivers/intel/gma/i915.h ++++ b/src/drivers/intel/gma/i915.h +@@ -291,6 +291,7 @@ struct i915_gpu_controller_info + int lvds_dual_channel; + int link_frequency_270_mhz; + int lvds_num_lanes; ++ u32 backlight; + }; + + int i915lightup(unsigned int physbase, unsigned int mmio, +diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c +index 4cf2776..b08422a 100644 +--- a/src/northbridge/intel/gm45/gma.c ++++ b/src/northbridge/intel/gm45/gma.c +@@ -446,12 +446,13 @@ static void gma_func0_init(struct device *dev) + /* Init graphics power management */ + gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); + ++ struct northbridge_intel_gm45_config *conf = dev->chip_info; ++ + #if !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT + /* PCI Init, will run VBIOS */ + pci_dev_init(dev); + #else + u32 physbase; +- struct northbridge_intel_gm45_config *conf = dev->chip_info; + struct resource *lfb_res; + struct resource *pio_res; + +@@ -475,7 +476,10 @@ static void gma_func0_init(struct device *dev) + /* Post VBIOS init */ + /* Enable Backlight */ + gtt_write(BLC_PWM_CTL2, (1 << 31)); +- gtt_write(BLC_PWM_CTL, 0x06100610); ++ if (conf->gfx.backlight == 0) ++ gtt_write(BLC_PWM_CTL, 0x06100610); ++ else ++ gtt_write(BLC_PWM_CTL, conf->gfx.backlight); + } + + static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) +-- +1.9.1 + |