diff options
Diffstat (limited to 'docs/src/install')
| -rw-r--r-- | docs/src/install/bbb_ehci.texi | 400 | ||||
| -rw-r--r-- | docs/src/install/bbb_setup.texi | 284 | ||||
| -rw-r--r-- | docs/src/install/c201.texi | 163 | ||||
| -rw-r--r-- | docs/src/install/index.texi | 274 | ||||
| -rw-r--r-- | docs/src/install/kgpe-d16.texi | 66 | ||||
| -rw-r--r-- | docs/src/install/r400_external.texi | 296 | ||||
| -rw-r--r-- | docs/src/install/r500_external.texi | 241 | ||||
| -rw-r--r-- | docs/src/install/t400_external.texi | 296 | ||||
| -rw-r--r-- | docs/src/install/t500_external.texi | 296 | ||||
| -rw-r--r-- | docs/src/install/t60_unbrick.texi | 152 | ||||
| -rw-r--r-- | docs/src/install/x200_external.texi | 277 | ||||
| -rw-r--r-- | docs/src/install/x60_unbrick.texi | 164 | ||||
| -rw-r--r-- | docs/src/install/x60tablet_unbrick.texi | 112 |
13 files changed, 3021 insertions, 0 deletions
diff --git a/docs/src/install/bbb_ehci.texi b/docs/src/install/bbb_ehci.texi new file mode 100644 index 0000000..8a25db3 --- /dev/null +++ b/docs/src/install/bbb_ehci.texi @@ -0,0 +1,400 @@ +\input texinfo +@documentencoding UTF-8 + +@macro textsuperscript{text} +@iftex +@textsuperscript{\text\} +@end iftex +@ifnottex +^@{\text\@} +@end ifnottex +@end macro + +@ifnottex +@paragraphindent 0 +@end ifnottex +@titlepage +@title EHCI debugging on the BeagleBone Black +@end titlepage + +@node Top +@top EHCI debugging on the BeagleBone Black + +@menu +* EHCI debugging on the BeagleBone Black:: +* EHCI debugging:: +@end menu + +@node EHCI debugging on the BeagleBone Black +@chapter EHCI debugging on the BeagleBone Black +@anchor{#ehci-debugging-on-the-beaglebone-black} +@uref{index.html,Back to previous index} + +@node EHCI debugging +@chapter EHCI debugging +@anchor{#ehci-debugging} +@enumerate +@item +@ref{#FindUSBportonthetargetthatsupportsEHCIdebug,Find USB port on the target that supports EHCI debug} +@item +@ref{#InitialsetupofBBBtoactasEHCIdebugdongle,Initial setup of BBB to act as EHCI debug dongle} +@item +@ref{#PatchBBBsgdbgpmoduleoptionalbuthighlyrecommended,Patch BBB's @code{g_dbgp} module (optional, but highly recommended)} +@item +@ref{#ConfigurelibrebootwithEHCIdebug,Configure libreboot with EHCI debug} +@enumerate +@item +@ref{#SelectingHCDIndexandUSBDebugport,Selecting @code{HCD Index} and @code{USB Debug port}} +@end enumerate + +@item +@ref{#Howtogetthedebuglogs,How to get the debug logs} +@item +@ref{#EnebleEHCIDebugonthetargetskerneloptionalrecommended,Eneble EHCI Debug on the target's kernel (optional, recommended)} +@item +@ref{#References,References} +@end enumerate + +If your computer does not boot after installing libreboot, it is very useful to get debug logs from it, from the payload (grub) and/or the kernel (if gets to there). All of them stream debug logs on the available serial (RS-232) by default. However, most of todays laptops lack RS-232 port. The other option is to stream the logs to USB EHCI debug port. + +This section explains step-by-step how to setup BBB as a “USB EHCI debug dongle” and configure libreboot and the linux kernel to stream logs to it (TODO: grub). + +I will refer to three computers: + +@itemize +@item +@strong{host} - this is the computer you use, have tools, compiler, Internet, etc +@item +@strong{BBB} - Beaglebone Black (rev. B or higher, i use rev. C) +@item +@strong{target} - the computer you are trying to install liberboot +@end itemize + +@node Find USB port on the target that supports EHCI debug +@subsection Find USB port on the target that supports EHCI debug +@anchor{#find-usb-port-on-the-target-that-supports-ehci-debug} +Not all USB controllers support EHCI debug (see: @uref{http://www.coreboot.org/EHCI_Debug_Port#Hardware_capability,EHCI Debug Port} ). Even more, if a USB controller supports EHCI debug, it is available only @strong{on a single port} that might or might not be exposed externally. + +@itemize +@item +You need running OS (GNU/Linux) on your target for this step (If you've flashed libreboot and it does not boot, you have to flush back the stock bios) +@item +You need USB memory stick (the data on it will not be touched). +@item +The EHCI debugging can not be done through external hub, BBB must be connected directly to the debug port of the controller (so, no hubs) +@end itemize + +@itemize +@item +Download@textsuperscript{@ref{#___fn1,1}} @uref{http://www.coreboot.org/pipermail/coreboot/attachments/20080909/ae11c291/attachment.sh,this} shell script. +@end itemize + +@enumerate +@item +Plug the usb stick in the first available usb port +@item +Run the script, you will get output similar to following: +@item +The buses the support debug are Bus 3 (0000:00:1a.0) on Port 1 and Bus 4 (0000:00:1d.0) on port 2. Your usb stick is plugged on Bus 1, Port 3 +@item +Repeat the steps, plugging the USB stick in the next available port +@item +Go through all available ports and remember(write down) those for which bus/port of the usb stick matches one of the bus/port that support debug (bold). +@end enumerate + +Remember (write down) for each port (external plug) you found that supports debug: @strong{PCI device id, the bus id, the port number, and the physical location of the usb plug.} + +If you do not find a match, you can not get debug over EHCI. Sorry. + +@textsuperscript{1} The guys from coreboot were talking about including the script in coreboot distribution (check the status). + +@node Initial setup of BBB to act as EHCI debug dongle +@subsection Initial setup of BBB to act as EHCI debug dongle +@anchor{#initial-setup-of-bbb-to-act-as-ehci-debug-dongle} +BBB must be powered with a barrel power connector since the mini-B USB plug will be used for the EHCI debug stream. So you will need: + +@itemize +@item +power supply (5V, 2A(10W) is sufficient). +@item +an extra usb cable: A to mini-B +@end itemize + +(On BBB) The linux kernel includes module (g_dbgp that enables one of the usb ports on a computer to behave as EHCI debug dongle. Make sure you have this module available on your BBB (Debian 7.8 that comes with BBB should have it), if not, you should compile it yourself (see next section): + +@verbatim +ls /lib/modules/3.8.13-bone70/kernel/drivers/usb/gadget/g_dbgp.ko +@end verbatim + +Unload all other g_* modules: + +@verbatim +# lsmod +# rmmod g_multi +... +@end verbatim + +Then load g_dbgp : + +@verbatim +# modprobe g_dbgp +# lsmod # should show that g_dbgp is loaded, and no other g_* +@end verbatim + +Plug the mini-B side of the USB cable in your BBB and the A side in your target. Then one of the usb devices on your target (with lsusb ) should be: + +@verbatim +Bus 001 Device 024: ID 0525:c0de Netchip Technology, Inc. +@end verbatim + +If you see the device on the target, you are good to continue to the next step. + +@node Patch BBB's g_dbgp module optional but highly recommended +@subsection Patch BBB's g_dbgp module (optional, but highly recommended) +@anchor{#patch-bbbs-g_dbgp-module-optional-but-highly-recommended} +For the reasons why you need this, see: @uref{http://www.coreboot.org/EHCI_Gadget_Debug,EHCI Gadget Debug}.@*Make sure that you have cross compiling environment for arm-linux-gnueabihf setup on your @emph{host}. + +@itemize +@item +On BBB: uname -r - this will give you version number like 3.8.13-bone70 (I will refer to this as: $mav.$miv-$lv: where mav=3.8, miv=13, lv=bone70 +@item +Get the BBB kernel ready on your host for cross-compiling: +@end itemize + +@verbatim +$ cd $work_dir +$ git clone https://github.com/beagleboard/kernel.git +$ cd kernel +$ git checkout $mav (see above) +$ ./patch.sh +$ wget http://arago-project.org/git/projects/?p=am33x-cm3.git\;a=blob_plain\;f=bin/am335x-pm-firmware.bin\;hb=HEAD -O kernel/firmware/am335x-pm-firmware.bin +$ cp configs/beaglebone kernel/arch/arm/configs/beaglebone_defconfig +@end verbatim + +@itemize +@item +Download the patch from @uref{http://www.coreboot.org/images/8/88/Ehci-debug-gadget-patches.tar.gz,here} +@item +tar -xf Ehci-debug-gadget-patches.tar.gz (will create dir: usbdebug-gadget) +@item +Note that there are two patches (patch_1 and patch_2) for each of the two different version of the kernel (3.8 and 3.10). I will use 3.8. (If using kernel 3.12 patch_1 is not needed) +@item +cd kernel (note that this is one more level: you should be in $work_dir/kernel/kernel) +@item +Apply the patches: +@end itemize + +@verbatim +git apply ../usbdebug-gadget/v3.8-debug-gadget/0001-usb-dbgp-gadget-Fix-re-connecting-after-USB-disconne.patch +git apply ../usbdebug-gadget/v3.8-debug-gadget/0002-usb-serial-gadget-no-TTY-hangup-on-USB-disconnect-WI.patch +; +make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- beaglebone_defconfig -j4@ +@end verbatim + +@itemize +@item +You should also apply the linux-libre @emph{deblob} script to turn it into linux-libre (deletes all the blobs from the linux kernel). @uref{http://www.fsfla.org/ikiwiki/selibre/linux-libre/,fsfla website} - see @uref{http://www.fsfla.org/svn/fsfla/software/linux-libre/scripts/,scripts}. +@item +Get your current BBB kernel config (from: /boot/config-<ver>) and copy it to your host as $work_dir/kernel/kernel/.config +@item +Set proper version number: +@itemize +@item +On your host, edit $work_dir/kernel/kernel/.config (the one you've just copied from BBB), find the line CONFIG_LOCALVERSION="<something or empty>" and change it to CONFIG_LOCALVERSION="-$lv", so it will look something like: CONFIG_LOCALVERSION="-bone70" +@end itemize + +@item +Also, make sure that: CONFIG_USB_G_DBGP=m (If not, make menuconfig, and set @@Device Drivers-> USB Support -> USB Gadget Support -> EHCI Debug Device Gadget=m +@item +Build the module: +@end itemize + +@verbatim +$ make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- -j4 (is it possoble to build only the gadget modules) +$ mkdir ../tmp && make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- INSTALL_MOD_PATH=../tmp modules_install +@end verbatim + +@itemize +@item +on BBB, backup /lib/modules/3.8.13-bone70/kernel/drivers/usb/gadget (i.e. mv /lib/modules/3.8.13-bone70/kernel/drivers/usb/gadget $HOME) +@item +copy the freshly compiled usb/gadget dir to /lib/modules/3.8.13-bone70/kernel/drivers/usb +@item +restart BBB +@item +Remove all g_* modules (rmmod g_<>) +@item +modprobpe g_dbgp +@end itemize + +@node Configure libreboot with EHCI debug +@subsection Configure libreboot with EHCI debug +@anchor{#configure-libreboot-with-ehci-debug} +Libreboot(coreboot) should be configured with debug turned on and to push debug messages to the EHCI debug port.@*If you've downloaded the binary distribution, you can check if it is properly configured in the following way: + +@itemize +@item +Go to the libreboot dist root directory cd $libreboot_bin +@item +Locate the rom image for your target (I will call it: $img_path) +@item +Running the following command will extract the config in a file ./my_config: +@end itemize + +@verbatim +./cbfstool/i686/cbfstool $img_path extract -n config -f ./my_config +@end verbatim + +@itemize +@item +Make sure that the following params in the config are set as following: +@end itemize + +@verbatim +CONFIG_USBDEBUG=y (Generic Drivers -> USB 2.0 EHCI debug dongle support) +CONFIG_USBDEBUG_IN_ROMSTAGE=y (Generic Drivers -> Enable early (pre-RAM) usbdebug) +CONFIG_USBDEBUG_HCD_INDEX=<HCD Index of usb controller - see below> (Generic Drivers -> Index for EHCI controller to use with usbdebug) +CONFIG_USBDEBUG_DEFAULT_PORT=<USB Debug port - see below> (Generic Drivers -> Default USB port to use as Debug Port) +@end verbatim + +The following three are behind radio button in the menu. Only the first one@textsuperscript{@ref{#___fn2,2}} should be = y + +@verbatim +USBDEBUG_DONGLE_STD=y (Generic Drivers -> Type of dongle (Net20DC or compatible) -> Net20DC or compatible) +CONFIG_USBDEBUG_DONGLE_BEAGLEBONE=n (Generic Drivers -> Type of dongle (Net20DC or compatible) -> BeagleBone) +CONFIG_USBDEBUG_DONGLE_BEAGLEBONE_BLACK=n (Generic Drivers -> Type of dongle (Net20DC or compatible) -> BeagleBone Black) +@end verbatim + +@textsuperscript{2} The g_dbgp module on BeagleBone Black (Rev. C) reports it self as Net20DC, the other options are for older BB(B) - ver1. This is documented @uref{https://johnlewis.ie/coreboot-ehci-debug-gadget-demonstration/,here} (also tested/verified). + +Then:@* + +@verbatim +CONFIG_CONSOLE_USB=y (Console -> USB dongle console output) +@end verbatim + +Also Debugging ---> Output verbose XYZ ) (@strong{FIXME} somebody verify these): + +@verbatim +CONFIG_DEBUG_CBFS=y (Output verbose CBFS debug messages ) +CONFIG_HAVE_DEBUG_RAM_SETUP=y (??? What/where is this) +CONFIG_DEBUG_RAM_SETUP=y (Output verbose RAM init debug messages) +CONFIG_DEBUG_SMI=y (Output verbose SMI debug messages) +CONFIG_DEBUG_ACPI=y (Output verbose ACPI debug messages ) +CONFIG_DEBUG_USBDEBUG=y (Output verbose USB 2.0 EHCI debug dongle messages) +@end verbatim + +If some of the above mentioned configuration options are not as specified, you have to configure and compile libreboot yourself. Please refer to the doc(@strong{FIXME: link} about compiling libreboot. +@menu +* Selecting HCD Index and USB Debug port:: +@end menu + +@node Selecting HCD Index and USB Debug port +@subsubsection Selecting HCD Index and USB Debug port +@anchor{#selecting-hcd-index-and-usb-debug-port} +This applies (and works) only if the USB controller that supports debug (found in the first section) is from Intel.@*If the PCI ID of the port you found in the first section is 0000:00:1a.0 or 0000:00:1d.0 , you are ok. Otherwise you have to try without guarantee that will work. + +If the externally exposed port is on a bus with PCI ID == 0000:00:1a.0 then for CONFIG_USBDEBUG_HCD_INDEX choose 2, otherwise choose 0 . + +For CONFIG_USBDEBUG_DEFAULT_PORT choose the port from the first section that correspond to the PCI ID + +Notes:@*The above is based on the implementation of coreboot/src/southbridge/intel/common/usb_debug.c : pci_ehci_dbg_dev() .@*This is enough as it applies for the supported GM45/G45 Thinkpads. coreboot support some other contollers too, but they are irellevent for libreboot (for now). + +@itemize +@item +On T500 (with switchable GPU) the debug ports for both intel controllers is exposed. +@item +On x200t the debug ports for both intel controllers is exposed. +@end itemize + +@node How to get the debug logs +@subsection How to get the debug logs +@anchor{#how-to-get-the-debug-logs} +@itemize +@item +Plug the USB cable in the target's debug port (the one you found in step 1) and BBB's mini-B USB +@item +Make sure no other then g_dbgp of the g_* modules is loaded on your BBB +@item +On the BBB: +@end itemize + +@verbatim +stty -icrnl -inlcr -F /dev/ttyGS0 +cat /dev/ttyGS0 +@end verbatim + +@itemize +@item +Power on the target with libreboot +@item +You should see debug logs comming on your BBB console +@end itemize + +Note that this is not permanent on BBB, if you reboot it, you have to rmmod g_* and modprobe g_dbgp + +@node Eneble EHCI Debug on the target's kernel optional recommended +@subsection Eneble EHCI Debug on the target's kernel (optional, recommended) +@anchor{#eneble-ehci-debug-on-the-targets-kernel-optional-recommended} +You have to know how to compile kernel for your target. + +@enumerate +@item +Check if early debugging is already enabled: grep CONFIG_EARLY_PRINTK_DBGP /boot/config-<ver> +@item +If enabled, you do not have to compile the kernel (skip this step). Otherwise, prepare kernel source for your distribution and select (Kernel hacking -> Early printk via EHCI debug port). Compile and install the new kernel. +@item +Edit your grub configuration and add following to the kenel parameters@textsuperscript{@ref{#___fn20,20}}@textsuperscript{@ref{#___fn21,21}}: earlyprintk=dbgp,keep. Also, try: earlyprintk=dbgp<N>,keep where N is the debug port id if the first does not work. +@end enumerate + +@node References +@subsection References +@anchor{#references} +@textsuperscript{10} @uref{http://www.coreboot.org/EHCI_Debug_Port,EHCI Debug Port} + +@textsuperscript{11} @uref{https://johnlewis.ie/coreboot-ehci-debug-gadget-demonstration/,coreboot EHCI debug gadget demonstration} + +@textsuperscript{12} @uref{http://www.coreboot.org/EHCI_Gadget_Debug,EHCI Gadget Debug} + +@textsuperscript{13} @uref{http://www.coreboot.org/images/8/88/Ehci-debug-gadget-patches.tar.gz,Ehci-debug-gadget-patches.tar.gz} + +@textsuperscript{14} @uref{http://wiki.beyondlogic.org/index.php/BeagleBoneBlack_Building_Kernel,Compiling the BeagleBone Black Kernel} + +@textsuperscript{15} http://dumb-looks-free.blogspot.ca/2014/06/beaglebone-black-bbb-compile-kernel.html + +@textsuperscript{16} http://dumb-looks-free.blogspot.fr/2014/06/beaglebone-black-bbb-kernal-headers.html + +@textsuperscript{17} @uref{http://elinux.org/Building_BBB_Kernel,Building BBB Kernel} + +@textsuperscript{18} http://komposter.com.ua/documents/USB-2.0-Debug-Port%28John-Keys%29.pdf + +@textsuperscript{19} @uref{http://cs.usfca.edu/~cruse/cs698s10/,Exploring USB at the Hardware/Software Interface} + +@textsuperscript{20} https://www.kernel.org/doc/Documentation/x86/earlyprintk.txt + +@textsuperscript{21} https://wiki.ubuntu.com/Kernel/Debugging/USBearlyprintk + +@strong{TODO}: + +@enumerate +@item +grub does not send messages to EHCI debug. Investigate. +@item +The section “Configure libreboot with EHCI debug” can be skipped/simplified if a common configuration works for all relevant targets is selected as defualt +@item +Patch and compule g_dbgp on BBB instead cross-compile +@item +Find a simple way to send debug messages from targets userland +@end enumerate + +Copyright © 2015 Alex David <opdecirkel@@gmail.com>@* Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license can be found at @uref{../resources/licenses/gfdl-1.3.txt,gfdl-1.3.txt} + +Updated versions of the license (when available) can be found at @uref{https://www.gnu.org/licenses/licenses.html,https://www.gnu.org/licenses/licenses.html} + +UNLESS OTHERWISE SEPARATELY UNDERTAKEN BY THE LICENSOR, TO THE EXTENT POSSIBLE, THE LICENSOR OFFERS THE LICENSED MATERIAL AS-IS AND AS-AVAILABLE, AND MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND CONCERNING THE LICENSED MATERIAL, WHETHER EXPRESS, IMPLIED, STATUTORY, OR OTHER. THIS INCLUDES, WITHOUT LIMITATION, WARRANTIES OF TITLE, MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NON-INFRINGEMENT, ABSENCE OF LATENT OR OTHER DEFECTS, ACCURACY, OR THE PRESENCE OR ABSENCE OF ERRORS, WHETHER OR NOT KNOWN OR DISCOVERABLE. WHERE DISCLAIMERS OF WARRANTIES ARE NOT ALLOWED IN FULL OR IN PART, THIS DISCLAIMER MAY NOT APPLY TO YOU. + +TO THE EXTENT POSSIBLE, IN NO EVENT WILL THE LICENSOR BE LIABLE TO YOU ON ANY LEGAL THEORY (INCLUDING, WITHOUT LIMITATION, NEGLIGENCE) OR OTHERWISE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, CONSEQUENTIAL, PUNITIVE, EXEMPLARY, OR OTHER LOSSES, COSTS, EXPENSES, OR DAMAGES ARISING OUT OF THIS PUBLIC LICENSE OR USE OF THE LICENSED MATERIAL, EVEN IF THE LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH LOSSES, COSTS, EXPENSES, OR DAMAGES. WHERE A LIMITATION OF LIABILITY IS NOT ALLOWED IN FULL OR IN PART, THIS LIMITATION MAY NOT APPLY TO YOU. + +The disclaimer of warranties and limitation of liability provided above shall be interpreted in a manner that, to the extent possible, most closely approximates an absolute disclaimer and waiver of all liability. + +@bye diff --git a/docs/src/install/bbb_setup.texi b/docs/src/install/bbb_setup.texi new file mode 100644 index 0000000..78dc126 --- /dev/null +++ b/docs/src/install/bbb_setup.texi @@ -0,0 +1,284 @@ +\input texinfo +@documentencoding UTF-8 + +@ifnottex +@paragraphindent 0 +@end ifnottex +@titlepage +@title How to program an SPI flash chip with the BeagleBone Black +@end titlepage + +@node Top +@top How to program an SPI flash chip with the BeagleBone Black + +@menu +* How to program an SPI flash chip with the BeagleBone Black:: +* Hardware requirements:: +* Setting up the 33V DC PSU:: +* Accessing the operating system on the BBB:: +* Setting up spidev on the BBB:: +* Connecting the Pomona 5250/5252:: +* Notes about stability:: +@end menu + +@node How to program an SPI flash chip with the BeagleBone Black +@chapter How to program an SPI flash chip with the BeagleBone Black +@anchor{#how-to-program-an-spi-flash-chip-with-the-beaglebone-black} +This document exists as a guide for reading from or writing to an SPI flash chip with the BeagleBone Black, using the @uref{http://flashrom.org/Flashrom,flashrom} software. BeagleBone Black rev. C was used when creating this guide, but earlier revisions may also work. + +@uref{index.html,Back to previous index} + +@node Hardware requirements +@chapter Hardware requirements +@anchor{#hardware-requirements} +Shopping list (pictures of this hardware is shown later): + +@itemize +@item +External SPI programmer: @strong{BeagleBone Black} (rev. C) is highly recommended. Sometimes referred to as 'BBB'. @uref{http://beagleboard.org/black,This page} contains a list of distributors. farnell sells them - @uref{http://farnell.com/,http://farnell.com/} - If you can't get a BBB, there are other programmers listed on flashrom.org, but not all of them will be suitable for libreboot's purpose. (some may also require blobs. all BBs and BBBs though can be used without blobs). There are also some programmers not listed on flashrom.org, that can also work. A BB (original beaglebone) should work as well, though you might have to replace the distro that it came with. +@item +Electrical/insulative tape: cover the entire bottom surface of the BBB (the part that rests on a surface). This is important, when placing the BBB on top of a board so that nothing shorts. - easy to find in most hardware/electronics stores +@item +Clip for connecting to the flash chip: if you have a SOIC-16 flash chip (16 pins), you will need the @strong{Pomona 5252} or equivalent. For SOIC-8 flash chips (8 pins), you will need the @strong{Pomona 5250} or equivalent. Do check which chip you have, before ordering a clip. Also, make sure to buy at least two clips (they break easily). - Farnell sells these, and ships to many countries. @uref{http://farnell.com/,http://farnell.com/} - Some people find these difficult to get, especially in South America. If you have more links to suppliers, please contact the libreboot project with the relevant information. - @strong{if you can't get a pomona clip, some other clips might work (eg 3M) but are not always reliable. You can also directly solder the wires to the chip, if that suits you. The clip is just for convenience, really.} +@item +@strong{External 3.3V DC power supply}, for powering the flash chip. An ATX power supply / PSU (common on Intel/AMD desktop computers) will work for this. A lab PSU (DC) will also work (adjusted to 3.3V). Etc. +@itemize +@item +Getting a multimeter might be worthwhile, to verify that it's supplying 3.3V +@end itemize + +@item +@strong{External 5V DC power supply} (barrel connector), for powering the BBB. The BeagleBone can have power supplied via USB, but a dedicated power supply is recommended. These should be easy to find in most places that sell electronics. - @strong{OPTIONAL. Only needed if not powering with the USB cable, or if you want to use @uref{bbb_ehci.html,EHCI debug}} +@item +@strong{Pin header / jumper cables} (2.54mm / 0.1" headers) You should get male-male, male-female and female-female cables in 10cm size. Just get a load of them. other possible names for these cables: +@itemize +@item +flying leads +@item +dupont (this is just one possible brand name) +@item +Often used on breadboards, so they might be called breadboard cables +@item +Maybe they are called @strong{wires} instead of cables or leads +@item +They are also the same cables used on the GPIOs on the RPi +@item +@strong{adafruit.com} sells them, and there are others +@item +@strong{Some people find these difficult to buy. Contact the libreboot project if you have more links to sellers.} +@item +You might also be able to make these cables yourself. +@end itemize + +For PSU connections, long cables (e.g. 20cm) is fine, and you can extend it longer than that if needed. +@item +@strong{Mini USB A-B cable} (the BeagleBone probably already comes with one.) - @strong{OPTIONAL - only needed for @uref{bbb_ehci.html,EHCI debug} or for serial/ssh access without ethernet cable (g_multi kernel module)} +@item +@strong{FTDI TTL cable or debug board}, for accessing the serial console on your BBB. @uref{http://elinux.org/Beagleboard:BeagleBone_Black_Serial,This page} contains a list. - @strong{OPTIONAL - only needed for serial console on the BBB, if not using SSH via ethernet cable} +@end itemize + +@ref{#pagetop,Back to top of page.} + +@node Setting up the 33V DC PSU +@chapter Setting up the 3.3V DC PSU +@anchor{#setting-up-the-3.3v-dc-psu} +ATX PSU pinouts are on @uref{https://en.wikipedia.org/wiki/Power_supply_unit_%28computer%29#Wiring_diagrams,wikipedia} + +You can use pin 1 or 2 (orange wire) on a 20-pin or 24-pin ATX PSU for 3.3V, and any of the ground/earth sources (black cables) for ground. Short PS_ON# / Power on (green wire. pin 16 on 24-pin ATX PSU, or pin 14 on a 20-pin ATX PSU) to a ground (black. there is one right next to it) using a wire/paperclip/jumper then power on the PSU by grounding PS_ON# (this is also how an ATX motherboard turns on a PSU). + +@strong{DO **NOT** use pin 4, 6, do **NOT** use pin 19 or 20 (on a 20-pin ATX PSU), and DO **NOT** use pin 21, 22 or 23 (on a 24-pin ATX PSU). Those wires (the red ones) are 5V, and they **WILL** kill your flash chip. ***NEVER*** supply more than 3.3V to your flash chip. (that is, if it's a 3.3V flash chip. 5V and 1.8V SPI flash chips do exist, but they are rare. always check what voltage your chip takes. most take 3.3V)} + +You only need one 3.3V supply and one ground for the flash chip, after grounding PS_ON#. + +The male end of a 0.1" or 2.54mm header cable is not thick enough to remain permanently connected to the ATX PSU on its own. When connecting header cables to the connector on the ATX PSU, use a female end attached to a thicker piece of wire (you could use a paper clip), or wedge the male end of the jumper cable into the sides of the hole in the connector, instead of going through the centre. + +Here is an example set up:@* @image{../resources/images/x200/psu33,,,,jpg} + +@node Accessing the operating system on the BBB +@chapter Accessing the operating system on the BBB +@anchor{#accessing-the-operating-system-on-the-bbb} +The operating system on your BBB will probably have an SSH daemon running where the root account has no password. Use SSH to access the operating system and set a root password. By default, the OS on your BBB will most likely use DHCP, so it should already have an IP address. + +You will also be using the OS on your BBB for programming an SPI flash chip. +@menu +* Alternatives to SSH in case SSH fails:: +@end menu + +@node Alternatives to SSH in case SSH fails +@section Alternatives to SSH (in case SSH fails) +@anchor{#alternatives-to-ssh-in-case-ssh-fails} +You can also use a serial FTDI debug board with GNU Screen, to access the serial console.@* # @strong{screen /dev/ttyUSB0 115200}@* Here are some example photos:@* @image{../resources/images/x200/ftdi,,,,jpg} @image{../resources/images/x200/ftdi_port,,,,jpg}@* + +You can also connect the USB cable from the BBB to another computer and a new network interface will appear, with its own IP address. This is directly accessible from SSH, or screen:@* # @strong{screen /dev/ttyACM0 115200} + +You can also access the uboot console, using the serial method instead of SSH. + +@node Setting up spidev on the BBB +@chapter Setting up spidev on the BBB +@anchor{#setting-up-spidev-on-the-bbb} +Log on as root on the BBB, using either SSH or a serial console as defined in @ref{#bbb_access,#bbb_access}. Make sure that you have internet access on your BBB. + +Follow the instructions at @uref{http://elinux.org/BeagleBone_Black_Enable_SPIDEV#SPI0,http://elinux.org/BeagleBone_Black_Enable_SPIDEV#SPI0} up to (and excluding) the point where it tells you to modify uEnv.txt + +You need to update the software on the BBB first. If you have an element14 brand BBB (sold by Premier Farnell plc. stores like Farnell element14, Newark element14, and Embest), you may need to @uref{https://groups.google.com/forum/?_escaped_fragment_=msg/beagleboard/LPjCn4LEY2I/alozBGsbTJMJ#!msg/beagleboard/LPjCn4LEY2I/alozBGsbTJMJ,work around a bug} in the LED aging init script before you can update your software. If you don't have a file named /etc/init.d/led_aging.sh, you can skip this step and update your software as described below. Otherwise, replace the contents of this file with: + +@verbatim +#!/bin/sh -e +### BEGIN INIT INFO +# Provides: led_aging.sh +# Required-Start: $local_fs +# Required-Stop: $local_fs +# Default-Start: 2 3 4 5 +# Default-Stop: 0 1 6 +# Short-Description: Start LED aging +# Description: Starts LED aging (whatever that is) +### END INIT INFO + +x=$(/bin/ps -ef | /bin/grep "[l]ed_acc") +if [ ! -n "$x" -a -x /usr/bin/led_acc ]; then + /usr/bin/led_acc & +fi +@end verbatim + +Run @strong{apt-get update} and @strong{apt-get upgrade} then reboot the BBB, before continuing. + +Check that the firmware exists:@* # @strong{ls /lib/firmware/BB-SPI0-01-00A0.*}@* Output: + +@verbatim +/lib/firmware/BB-SPI0-01-00A0.dtbo +@end verbatim + +Then:@* # @strong{echo BB-SPI0-01 > /sys/devices/bone_capemgr.*/slots}@* # @strong{cat /sys/devices/bone_capemgr.*/slots}@* Output: + +@verbatim + 0: 54:PF--- + 1: 55:PF--- + 2: 56:PF--- + 3: 57:PF--- + 4: ff:P-O-L Bone-LT-eMMC-2G,00A0,Texas Instrument,BB-BONE-EMMC-2G + 5: ff:P-O-L Bone-Black-HDMI,00A0,Texas Instrument,BB-BONELT-HDMI + 7: ff:P-O-L Override Board Name,00A0,Override Manuf,BB-SPI0-01 +@end verbatim + +Verify that the spidev device now exists:@* # @strong{ls -al /dev/spid*}@* Output: + +@verbatim +crw-rw---T 1 root spi 153, 0 Nov 19 21:07 /dev/spidev1.0 +@end verbatim + +Now the BBB is ready to be used for flashing. Make this persist across reboots:@* In /etc/default/capemgr add @strong{CAPE=BB-SPI0-01} at the end (or change the existing @strong{CAPE=} entry to say that, if an entry already exists. + +Get flashrom from the libreboot_util release archive, or build it from libreboot_src/git if you need to. An ARM binary (statically compiled) for flashrom exists in libreboot_util releases. Put the flashrom binary on your BBB. + +You may also need ich9gen, if you will be flashing an ICH9-M laptop (such as the X200). Get it from libreboot_util, or build it from libreboot_src, and put the ARM binary for it on your BBB. + +Finally, get the ROM image that you would like to flash and put that on your BBB. + +Now test flashrom:@* # @strong{./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512}@* Output: + +@verbatim +Calibrating delay loop... OK. +No EEPROM/flash device found. +Note: flashrom can never write if the flash chip isn't found automatically. +@end verbatim + +This means that it's working (the clip isn't connected to any flash chip, so the error is fine). + +@node Connecting the Pomona 5250/5252 +@chapter Connecting the Pomona 5250/5252 +@anchor{#connecting-the-pomona-52505252} +Use this image for reference when connecting the pomona to the BBB: @uref{http://beagleboard.org/Support/bone101#headers,http://beagleboard.org/Support/bone101#headers} (D0 = MISO or connects to MISO). + +The following shows how to connect clip to the BBB (on the P9 header), for SOIC-16 (clip: Pomona 5252): + +@verbatim + NC - - 21 + 1 - - 17 + NC - - NC + NC - - NC + NC - - NC + NC - - NC + 18 - - 3.3V (PSU) + 22 - - NC - this is pin 1 on the flash chip +This is how you will connect. Numbers refer to pin numbers on the BBB, on the plugs near the DC jack. + +You may also need to connect pins 1 and 9 (tie to 3.3V supply). These are HOLD# and WP#. +On some systems they are held high, if the flash chip is attached to the board. +If you're flashing a chip that isn't connected to a board, you'll almost certainly +have to connect them. + +SOIC16 pinout (more info available online, or in the datasheet for your flash chip): +HOLD 1-16 SCK +VDD 2-15 MOSI +N/C 3-14 N/C +N/C 4-13 N/C +N/C 5-12 N/C +N/C 6-11 N/C +SS 7-10 GND +MISO 8-9 WP +@end verbatim + +The following shows how to connect clip to the BBB (on the P9 header), for SOIC-8 (clip: Pomona 5250): + +@verbatim + 18 - - 1 + 22 - - NC + NC - - 21 + 3.3V (PSU) - - 17 - this is pin 1 on the flash chip +This is how you will connect. Numbers refer to pin numbers on the BBB, on the plugs near the DC jack. + +You may also need to connect pins 3 and 7 (tie to 3.3V supply). These are HOLD# and WP#. +On some systems they are held high, if the flash chip is attached to the board. +If you're flashing a chip that isn't connected to a board, you'll almost certainly +have to connect them. + +SOIC8 pinout (more info available online, or in the datasheet for your flash chip): +SS 1-8 VDD +MISO 2-7 HOLD +WP 3-6 SCK +GND 4-5 MOSI +@end verbatim + +@strong{NC = no connection} + +@strong{DO NOT connect 3.3V (PSU) yet. ONLY connect this once the pomona is connected to the flash chip.} + +@strong{You also need to connect the BLACK wire (ground/earth) from the 3.3V PSU to pin 2 on the BBB (P9 header). It is safe to install this now (that is, before you connect the pomona to the flash chip); in fact, you should.} + +if you need to extend the 3.3v psu leads, just use the same colour M-F leads, @strong{but} keep all other leads short (10cm or less) + +You should now have something that looks like this:@* @image{../resources/images/x200/5252_bbb0,,,,jpg} @image{../resources/images/x200/5252_bbb1,,,,jpg} + +@ref{#pagetop,Back to top of page.} + +@node Notes about stability +@chapter Notes about stability +@anchor{#notes-about-stability} +@uref{http://flashrom.org/ISP,http://flashrom.org/ISP} is what we typically do in libreboot, though not always. That page has some notes about using resistors to affect stability. Currently, we use spispeed=512 (512kHz) but it is possible to use higher speeds while maintaining stability. + +tty0_ in #libreboot was able to get better flashing speeds with the following configuration: + +@itemize +@item +"coax" with 0.1 mm core and aluminum foley (from my kitchen), add 100 Ohm resistors (serial) +@item +put heatshrink above the foley, for: CS, CLK, D0, D1 +@item +Twisted pair used as core (in case more capacitors are needed) +@item +See this image: @uref{http://i.imgur.com/qHGxKpj.jpg,http://i.imgur.com/qHGxKpj.jpg} +@item +He was able to flash at 50MHz (lower speeds are also fine). +@end itemize + +Copyright © 2014, 2015 Francis Rowe <info@@gluglug.org.uk>@* Copyright © 2015 Patrick "P. J." McDermott <pj@@pehjota.net>@* Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license can be found at @uref{../resources/licenses/gfdl-1.3.txt,gfdl-1.3.txt} + +Updated versions of the license (when available) can be found at @uref{https://www.gnu.org/licenses/licenses.html,https://www.gnu.org/licenses/licenses.html} + +UNLESS OTHERWISE SEPARATELY UNDERTAKEN BY THE LICENSOR, TO THE EXTENT POSSIBLE, THE LICENSOR OFFERS THE LICENSED MATERIAL AS-IS AND AS-AVAILABLE, AND MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND CONCERNING THE LICENSED MATERIAL, WHETHER EXPRESS, IMPLIED, STATUTORY, OR OTHER. THIS INCLUDES, WITHOUT LIMITATION, WARRANTIES OF TITLE, MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NON-INFRINGEMENT, ABSENCE OF LATENT OR OTHER DEFECTS, ACCURACY, OR THE PRESENCE OR ABSENCE OF ERRORS, WHETHER OR NOT KNOWN OR DISCOVERABLE. WHERE DISCLAIMERS OF WARRANTIES ARE NOT ALLOWED IN FULL OR IN PART, THIS DISCLAIMER MAY NOT APPLY TO YOU. + +TO THE EXTENT POSSIBLE, IN NO EVENT WILL THE LICENSOR BE LIABLE TO YOU ON ANY LEGAL THEORY (INCLUDING, WITHOUT LIMITATION, NEGLIGENCE) OR OTHERWISE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, CONSEQUENTIAL, PUNITIVE, EXEMPLARY, OR OTHER LOSSES, COSTS, EXPENSES, OR DAMAGES ARISING OUT OF THIS PUBLIC LICENSE OR USE OF THE LICENSED MATERIAL, EVEN IF THE LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH LOSSES, COSTS, EXPENSES, OR DAMAGES. WHERE A LIMITATION OF LIABILITY IS NOT ALLOWED IN FULL OR IN PART, THIS LIMITATION MAY NOT APPLY TO YOU. + +The disclaimer of warranties and limitation of liability provided above shall be interpreted in a manner that, to the extent possible, most closely approximates an absolute disclaimer and waiver of all liability. + +@bye diff --git a/docs/src/install/c201.texi b/docs/src/install/c201.texi new file mode 100644 index 0000000..9ea5feb --- /dev/null +++ b/docs/src/install/c201.texi @@ -0,0 +1,163 @@ +\input texinfo +@documentencoding UTF-8 + +@ifnottex +@paragraphindent 0 +@end ifnottex +@titlepage +@title ASUS Chromebook C201 installation guide +@end titlepage + +@node Top +@top ASUS Chromebook C201 installation guide + +@menu +* ASUS Chromebook C201 installation guide:: +* Installing Libreboot to the SPI flash:: +@end menu + +@node ASUS Chromebook C201 installation guide +@chapter ASUS Chromebook C201 installation guide +@anchor{#asus-chromebook-c201-installation-guide} +These instructions are for installing Libreboot to the ASUS Chromebook C201. Since the device ships with Coreboot, the installation instructions are the same before and after flashing Libreboot for the first time. + +@strong{If you are using libreboot_src or git, then make sure that you built the sources first (see @uref{../git/index.html#build,../git/index.html#build}).} + +Look at the @ref{#rom,list of ROM images} to see which image is compatible with your device. + +Libreboot can be installed internally from the device, with sufficient privileges. The installation process requires using @strong{Google's modified version of flashrom}, that has support for reflashing the Chromebook's SPI flash. Otherwise, flashing externally will work with the upstream flashrom version. + +@strong{Google's modified version of flashrom} is free software and its source code is made available by Google: @uref{https://chromium.googlesource.com/chromiumos/third_party/flashrom/,flashrom}.@* It is not distributed along with Libreboot yet. However, it is preinstalled on the device, with ChromeOS. + +Installing Libreboot internally requires sufficient privileges on the system installed on the device.@* When the device has ChromeOS installed (as it does initially), it is necessary to gain root privileges in ChromeOS, to be able to access a root shell. + +@itemize +@item +@ref{#root_chromeos,Gaining root privileges on ChromeOS} +@item +@ref{#preparing_device,Preparing the device for the installation} +@itemize +@item +@ref{#configuring_verified_boot_parameters,Configuring verified boot parameters} +@item +@ref{#removing_write_protect_screw,Removing the write protect screw} +@end itemize + +@item +@uref{,Installing Libreboot to the SPI flash} +@itemize +@item +@ref{#installing_libreboot_internally,Installing Libreboot internally, from the device} +@item +@ref{#installing_libreboot_externally,Installing Libreboot externally, with a SPI flash programmer} +@end itemize + +@end itemize + +@uref{../index.html,Back to main index} + +Gaining root privileges on ChromeOS + +In order to gain root privileges on ChromeOS, developer mode has to be enabled from the recovery mode screen and debugging features have to be enabled in ChromeOS. + +Instructions to access the @uref{../depthcharge/index.html#recovery_mode_screen,recovery mode screen} and @uref{../depthcharge/index.html#enabling_developer_mode,enabling developer mode} are available on the page dedicated to @uref{../depthcharge/index.html,depthcharge}. + +Once developer mode is enabled, the device will boot to the @uref{../depthcharge/index.html#developer_mode_screen,developer mode screen}. ChromeOS can be booted by waiting for 30 seconds (the delay is shortened in Libreboot) or by pressing @strong{Ctrl + D} + +After the system has booted, root access can be enabled by clicking on the @strong{Enable debugging features} link. A confirmation dialog will ask whether to proceed.@* After confirming by clicking @strong{Proceed}, the device will reboot and ask for the root password to set. Finally, the operation has to be confirmed by clicking @strong{Enable}. + +After setting the root password, it becomes possible to log-in as root. A tty prompt can be obtained by pressing @strong{Ctrl}+@strong{Alt}+@strong{Previous}. The @strong{Previous} key is the one on the top left of the keyboard. + +Preparing the device for the installation + +Before installing Libreboot on the device, both its software and hardware has to be prepared to allow the installation procedure and to ensure that security features don't get in the way. +@menu +* Configuring verified boot parameters:: +* Removing the write protect screw:: +@end menu + +@node Configuring verified boot parameters +@section Configuring verified boot parameters +@anchor{#configuring-verified-boot-parameters} +It is recommended to have access to the @uref{../depthcharge/index.html#developer_mode_screen,developer mode screen} and to @uref{../depthcharge/index.html#configuring_verified_boot_parameters,configure the following verified boot parameters}: + +@itemize +@item +Kernels signature verification: @emph{disabled} +@item +External media boot: @emph{enabled} +@end itemize + +Those changes can be reverted later, when the device is known to be in a working state. + +@node Removing the write protect screw +@section Removing the write protect screw +@anchor{#removing-the-write-protect-screw} +Since part of the SPI flash is write-protected by a screw, it is necessary to remove the screw to remove the write protection and allow writing Libreboot to the @emph{read-only} part of the flash. + +To access the screw, the device has to be opened. There are 7 screws to remove from the bottom of the device, as shown on the picture below. One is hidden under the top right pad. After removing the screws, the keyboard plastic part can be carefully detached from the rest. @strong{Beware: there are cables attached to it!} It is advised to flip the keyboard plastic part over, as shown on the picture below. The write protect screw is located next to the SPI flash chip, circled in red in the picture below. It has to be removed. + +@uref{../resources/images/c201/screws.jpg,@image{../resources/images/c201/screws,,,Screws,jpg}} @uref{../resources/images/c201/wp-screw.jpg,@image{../resources/images/c201/wp-screw,,,WP screw,jpg}} + +The write protect screw can be put back in place later, when the device is known to be in a working state. + +@node Installing Libreboot to the SPI flash +@chapter Installing Libreboot to the SPI flash +@anchor{#installing-libreboot-to-the-spi-flash} +The SPI flash (that holds Libreboot) is divided into various partitions that are used to implement parts of the CrOS security system. Libreboot is installed in the @emph{read-only} coreboot partition, that becomes writable after removing the write-protect screw. +@menu +* Installing Libreboot internally from the device:: +* Installing Libreboot externally with a SPI flash programmer:: +@end menu + +@node Installing Libreboot internally from the device +@section Installing Libreboot internally, from the device +@anchor{#installing-libreboot-internally-from-the-device} +Before installing Libreboot to the SPI flash internally, the device has to be reassembled. + +All the files from the @strong{veyron_speedy} release (or build) have to be transferred to the device. + +The SPI flash has to be read first:@* # @strong{flashrom -p host -r flash.img}@* @strong{Note: it might be a good idea to copy the produced flash.img file at this point and store it outside of the device for backup purposes.} + +Then, the @strong{cros-flash-replace} script has to be executed as such:@* # @strong{./cros-firmware-replace flash.img coreboot ro-frid}@* If any error is shown, it is definitely a bad idea to go further than this point. + +The resulting flash image can then be flashed back:@* # @strong{flashrom -p host -w flash.img}@* + +You should also see within the output the following:@* @strong{"Verifying flash... VERIFIED."} + +Shut down. The device will now boot to Libreboot. + +@node Installing Libreboot externally with a SPI flash programmer +@section Installing Libreboot externally, with a SPI flash programmer +@anchor{#installing-libreboot-externally-with-a-spi-flash-programmer} +Before installing Libreboot to the SPI flash internally, the device has to be opened. + +The SPI flash is located next to the write protect screw. Its layout is indicated in the picture below. Note that it is not necessary to connect @strong{WP#} since removing the screw already connects it to ground. Before writing to the chip externally, the battery connector has to be detached. It is located under the heat spreader, that has to be unscrewed from the rest of the case. The battery connector is located on the right and has colorful cables, as shown on the picture below. + +@uref{../resources/images/c201/spi-flash-layout.jpg,@image{../resources/images/c201/spi-flash-layout,,,SPI flash layout,jpg}} @uref{../resources/images/c201/battery-connector.jpg,@image{../resources/images/c201/battery-connector,,,Battery connector,jpg}} + +All the files from the @strong{veyron_speedy} release (or build) have to be transferred to the host. + +The SPI flash has to be read first (using the right spi programmer):@* # @strong{flashrom -p @emph{programmer} -r flash.img}@* @strong{Note: it might be a good idea to copy the produced flash.img file at this point and store it outside of the device for backup purposes.} + +Then, the @strong{cros-flash-replace} script has to be executed as such:@* # @strong{./cros-firmware-replace flash.img coreboot ro-frid}@* If any error is shown, it is definitely a bad idea to go further than this point. + +The resulting flash image can then be flashed back (using the right spi programmer):@* # @strong{flashrom -p @emph{programmer} -w flash.img}@* + +You should also see within the output the following:@* @strong{"Verifying flash... VERIFIED."} + +The device will now boot to Libreboot. + +@ref{#pagetop,Back to top of page.} + +Copyright © 2015 Paul Kocialkowski <contact@@paulk.fr>@* Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license can be found at @uref{../resources/licenses/gfdl-1.3.txt,gfdl-1.3.txt} + +Updated versions of the license (when available) can be found at @uref{https://www.gnu.org/licenses/licenses.html,https://www.gnu.org/licenses/licenses.html} + +UNLESS OTHERWISE SEPARATELY UNDERTAKEN BY THE LICENSOR, TO THE EXTENT POSSIBLE, THE LICENSOR OFFERS THE LICENSED MATERIAL AS-IS AND AS-AVAILABLE, AND MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND CONCERNING THE LICENSED MATERIAL, WHETHER EXPRESS, IMPLIED, STATUTORY, OR OTHER. THIS INCLUDES, WITHOUT LIMITATION, WARRANTIES OF TITLE, MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NON-INFRINGEMENT, ABSENCE OF LATENT OR OTHER DEFECTS, ACCURACY, OR THE PRESENCE OR ABSENCE OF ERRORS, WHETHER OR NOT KNOWN OR DISCOVERABLE. WHERE DISCLAIMERS OF WARRANTIES ARE NOT ALLOWED IN FULL OR IN PART, THIS DISCLAIMER MAY NOT APPLY TO YOU. + +TO THE EXTENT POSSIBLE, IN NO EVENT WILL THE LICENSOR BE LIABLE TO YOU ON ANY LEGAL THEORY (INCLUDING, WITHOUT LIMITATION, NEGLIGENCE) OR OTHERWISE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, CONSEQUENTIAL, PUNITIVE, EXEMPLARY, OR OTHER LOSSES, COSTS, EXPENSES, OR DAMAGES ARISING OUT OF THIS PUBLIC LICENSE OR USE OF THE LICENSED MATERIAL, EVEN IF THE LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH LOSSES, COSTS, EXPENSES, OR DAMAGES. WHERE A LIMITATION OF LIABILITY IS NOT ALLOWED IN FULL OR IN PART, THIS LIMITATION MAY NOT APPLY TO YOU. + +The disclaimer of warranties and limitation of liability provided above shall be interpreted in a manner that, to the extent possible, most closely approximates an absolute disclaimer and waiver of all liability. + +@bye diff --git a/docs/src/install/index.texi b/docs/src/install/index.texi new file mode 100644 index 0000000..8ca7e39 --- /dev/null +++ b/docs/src/install/index.texi @@ -0,0 +1,274 @@ +\input texinfo +@documentencoding UTF-8 + +@ifnottex +@paragraphindent 0 +@end ifnottex +@titlepage +@title Installing libreboot +@end titlepage + +@node Top +@top Installing libreboot + +@menu +* Installing libreboot:: +* List of ROM images in libreboot:: +* How to update or install libreboot if you are already running libreboot or coreboot:: +* ThinkPad X60/T60 Initial installation guide if running the proprietary firmware:: +* MacBook21 Initial installation guide if running the proprietary firmware:: +@end menu + +@node Installing libreboot +@chapter Installing libreboot +@anchor{#installing-libreboot} +This section relates to installing libreboot on supported targets. + +@uref{../index.html,Back to previous index} +@menu +* Software methods:: +* Hardware methods:: +@end menu + +@node Software methods +@section Software methods +@anchor{#software-methods} +@itemize +@item +@ref{#rom,List of ROM images in libreboot} +@item +@ref{#flashrom,How to update or install libreboot (if you are already running libreboot or coreboot)} +@item +@ref{#flashrom,KFSN4-DRE: initial installation guide (if running the proprietary firmware or libreboot)} +@item +@ref{#flashrom_lenovobios,ThinkPad X60/T60: Initial installation guide (if running the proprietary firmware)} +@item +@ref{#flashrom_macbook21,MacBook2,1: Initial installation guide (if running the proprietary firmware)} +@item +@uref{c201.html,ASUS Chromebook C201 installation guide} (Installing Libreboot internally, from the device) +@end itemize + +@node Hardware methods +@section Hardware methods +@anchor{#hardware-methods} +@itemize +@item +@uref{bbb_setup.html,How to program an SPI flash chip with the BeagleBone Black} +@item +@uref{bbb_ehci.html,How to configure EHCI debugging on the BeagleBone Black} +@item +@uref{kgpe-d16.html,KGPE-D16 (needed if running the proprietary firmware, or to unbrick)} +@item +@uref{x60_unbrick.html,ThinkPad X60: Recovery guide} +@item +@uref{x60tablet_unbrick.html,ThinkPad X60 Tablet: Recovery guide} +@item +@uref{t60_unbrick.html,ThinkPad T60: Recovery guide} +@item +@uref{x200_external.html,ThinkPad X200/X200S/X200T (needed if running the proprietary firmware, or to unbrick)} +@item +@uref{r400_external.html,ThinkPad R400 (needed if running the proprietary firmware, or to unbrick)} +@item +@uref{r500_external.html,ThinkPad R500 (needed if running the proprietary firmware, or to unbrick)} +@item +@uref{t400_external.html,ThinkPad T400 (needed if running the proprietary firmware, or to unbrick)} +@item +@uref{t500_external.html,ThinkPad T500 (needed if running the proprietary firmware, or to unbrick)} +@item +@uref{c201.html,ASUS Chromebook C201 installation guide} (Installing Libreboot externally, with a SPI flash programmer) +@end itemize + +@node List of ROM images in libreboot +@chapter List of ROM images in libreboot +@anchor{#list-of-rom-images-in-libreboot} +Libreboot distributes pre-compiled ROM images, built from the libreboot source code. These images are provided for user convenience, so that they don't have to build anything from source on their own. + +The ROM images in each archive use the following at the end of the file name, if they are built with the GRUB payload: @strong{_@emph{keymap}_@emph{mode}.rom} + +Available @emph{modes}: @strong{vesafb} or @strong{txtmode}. The @emph{vesafb} ROM images are recommended, in most cases; @emph{txtmode} ROM images come with MemTest86+, which requires text-mode instead of the usual framebuffer used by coreboot native graphics initialization. + +@emph{keymap} can be one of several keymaps that keyboard supports (there are quite a few), which affects the keyboard layout configuration that is used in GRUB. It doesn't matter which ROM image you choose here, as far as the keymap in GNU/Linux is concerned. + +Keymaps are named appropriately according to each keyboard layout support in GRUB. To learn how these keymaps are created, see @uref{../grub/index.html#grub_keyboard,../grub/index.html#grub_keyboard} +@menu +* QEMU:: +@end menu + +@node QEMU +@section QEMU +@anchor{#qemu} +Libreboot comes with ROM images built for QEMU, by default: + +Examples of how to use libreboot ROM images in QEMU: + +@itemize +@item +$ @strong{qemu-system-i386 -M q35 -m 512 -bios qemu_q35_ich9_keymap_mode.rom} +@item +$ @strong{qemu-system-i386 -M pc -m 512 -bios qemu_i440fx_piix4_keymap_mode.rom} +@end itemize + +You can optionally specify the @strong{-serial stdio} argument, so that QEMU will emulate a serial terminal on the standard input/output (most likely your terminal emulator or TTY). + +Other arguments are available for QEMU. The manual will contain more information. + +@ref{#pagetop,Back to top of page.} + +@node How to update or install libreboot if you are already running libreboot or coreboot +@chapter How to update or install libreboot (if you are already running libreboot or coreboot) +@anchor{#how-to-update-or-install-libreboot-if-you-are-already-running-libreboot-or-coreboot} +On all current targets, updating libreboot can be accomplished without disassembly and, therefore, without having to externally re-flash using any dedicated hardware. In other words, you can do everything entirely in software, directly from the OS that is running on your libreboot system. + +@strong{If you are using libreboot_src or git, then make sure that you built the sources first (see @uref{../git/index.html#build,../git/index.html#build}).} + +Look at the @ref{#rom,list of ROM images} to see which image is compatible with your device. +@menu +* Are you currently running the original proprietary firmware?:: +* ASUS KFSN4-DRE?:: +* ASUS KGPE-D16?:: +* Are you currently running libreboot or coreboot?:: +* MAC address on GM45 X200/R400/T400/T500:: +* Flash chip size:: +* All good?:: +@end menu + +@node Are you currently running the original proprietary firmware? +@section Are you currently running the original, proprietary firmware? +@anchor{#are-you-currently-running-the-original-proprietary-firmware} +If you are currently running the proprietary firmware (not libreboot or coreboot), then the flashing instructions for your system are going to be different. + +X60/T60 users running the proprietary firmware should refer to @ref{#flashrom_lenovobios,#flashrom_lenovobios}. MacBook2,1 users running Apple EFI should refer to @ref{#flashrom_macbook21,#flashrom_macbook21} + +X200 users, refer to @uref{x200_external.html,x200_external.html}, R400 users refer to @uref{r400_external.html,r400_external.html}, R500 users refer to @uref{r500_external.html,r500_external.html}, T400 users refer to @uref{t400_external.html,t400_external.html}, T500 users refer to @uref{t500_external.html,t500_external.html} + +@node ASUS KFSN4-DRE? +@section ASUS KFSN4-DRE? +@anchor{#asus-kfsn4-dre} +Internal flashing should work just fine, even if you are currently booting the proprietary firmware. + +Libreboot currently lacks documentation for externally re-flashing an LPC flash chip. However, these boards have the flash chip inside of a PLCC socket, and it is possible to hot-swap the chips. If you want to back up your known-working image, simply hot-swap the chip for one that is the same capacity, after having dumped a copy of the current firmware (flashrom -p internal -r yourchosenname.rom), and then flash that chip with the known-working image. Check whether the system still boots, and if it does, then it should be safe to flash the new image (because you now have a backup of the old image). + +Keeping at least one spare LPC PLCC chip with working firmware on it is highly recommended, in case of bricks. + +@strong{DO NOT hot-swap the chip with your bare hands. Use a PLCC chip extractor. These can be found online. See @uref{http://www.coreboot.org/Developer_Manual/Tools#Chip_removal_tools,http://www.coreboot.org/Developer_Manual/Tools#Chip_removal_tools}} + +Do check the HCL entry: @uref{../hcl/kfsn4-dre.html,../hcl/kfsn4-dre.html} + +@node ASUS KGPE-D16? +@section ASUS KGPE-D16? +@anchor{#asus-kgpe-d16} +If you have the proprietary BIOS, you need to flash libreboot externally. See @uref{kgpe-d16.html,kgpe-d16.html}. + +If you already have coreboot or libreboot installed, without write protection on the flash chip, then you can do it in software (otherwise, see link above). + +@strong{DO NOT hot-swap the chip with your bare hands. Use a PDIP-8 chip extractor. These can be found online. See @uref{http://www.coreboot.org/Developer_Manual/Tools#Chip_removal_tools,http://www.coreboot.org/Developer_Manual/Tools#Chip_removal_tools}} + +Do check the HCL entry: @uref{../hcl/kgpe-d16.html,../hcl/kgpe-d16.html} + +@node Are you currently running libreboot or coreboot? +@section Are you currently running libreboot (or coreboot)? +@anchor{#are-you-currently-running-libreboot-or-coreboot} +X60/T60 users should be fine with this guide. If you write-protected the flash chip, please refer to @uref{x60_unbrick.html,x60_unbrick.html}, @uref{x60tablet_unbrick.html,x60tablet_unbrick.html} or @uref{t60_unbrick.html,t60_unbrick.html}. @emph{This probably does not apply to you. Most people do not write-protect the flash chip, so you probably didn't either.} + +Similarly, it is possible to write-protect the flash chip in coreboot or libreboot on GM45 laptops (X200/R400/R500/T400/T500). If you did this, then you will need to use the links above for flashing, treating your laptop as though it currently has the proprietary firmware (because write-protected SPI flash requires external re-flashing, as is also the case when running the proprietary firmware). + +If you did not write-protect the flash chip, or it came to you without any write-protection (@strong{@emph{libreboot does not write-protect the flash chip by default, so this probably applies to you}}), read on! + +@node MAC address on GM45 X200/R400/T400/T500 +@section MAC address on GM45 (X200/R400/T400/T500) +@anchor{#mac-address-on-gm45-x200r400t400t500} +@strong{Users of the X200/R400/T400/T500 take note:} The MAC address for the onboard ethernet chipset is located inside the flash chip. Libreboot ROM images for these laptops contain a generic MAC address by default (00:F5:F0:40:71:FE), but this is not what you want. @emph{Make sure to change the MAC address inside the ROM image, before flashing it. The instructions on @uref{../hcl/gm45_remove_me.html#ich9gen,../hcl/gm45_remove_me.html#ich9gen} show how to do this.} + +It is important that you change the default MAC address, before flashing. It will be printed on a sticker at the bottom of the laptop, or it will be printed on a sticker next to or underneath the RAM. Alternatively, and assuming that your current firmware has the correct MAC address in it, you can get it from your OS. + +@strong{R500 users: your laptop lacks a GbE region, because it has a different NIC. You do not need to change the MAC address on this laptop; it will already be correct. You can simply flash the available ROM images for the R500, as-is. See @uref{../hcl/r500.html#nogbe,../hcl/r500.html#nogbe}.} + +@node Flash chip size +@section Flash chip size +@anchor{#flash-chip-size} +Use this to find out:@* # @strong{dmidecode | grep ROM\ Size} + +@node All good? +@section All good? +@anchor{#all-good} +Excellent! Moving on... + +Download the @emph{libreboot_util.tar.xz} archive, and extract it. Inside, you will find a directory called @emph{flashrom}. This contains statically compiled executable files of the @emph{flashrom} utility, which you will use to re-flash your libreboot system. + +Simply use @emph{cd} on your terminal, to switch to the @emph{libreboot_util} directory. Inside, there is a script called @emph{flash}, which will detect what CPU architecture you have (e.g. i686, x86_64) and use the appropriate executable. It is also possible for you to build these executables from the libreboot source code archives. + +How to update the flash chip contents:@* $ @strong{sudo ./flash update @ref{#rom,yourrom.rom}} + +Ocassionally, coreboot changes the name of a given board. If flashrom complains about a board mismatch, but you are sure that you chose the correct ROM image, then run this alternative command:@* $ @strong{sudo ./flash forceupdate @ref{#rom,yourrom.rom}} + +You should see @strong{"Verifying flash... VERIFIED."} written at the end of the flashrom output. @strong{Shut down} after you see this, and then boot up again after a few seconds. + +@ref{#pagetop,Back to top of page} + +@node ThinkPad X60/T60 Initial installation guide if running the proprietary firmware +@chapter ThinkPad X60/T60: Initial installation guide (if running the proprietary firmware) +@anchor{#thinkpad-x60t60-initial-installation-guide-if-running-the-proprietary-firmware} +@strong{This is for the ThinkPad X60 and T60 while running Lenovo BIOS. If you already have coreboot or libreboot running, then go to @ref{#flashrom,#flashrom} instead!} + +@strong{If you are flashing a Lenovo ThinkPad T60, be sure to read @uref{../hcl/index.html#supported_t60_list,../hcl/index.html#supported_t60_list}} + +@strong{If you are using libreboot_src or git, then make sure that you built the sources first (see @uref{../git/index.html#build,../git/index.html#build}).} + +@strong{Warning: this guide will not instruct the user how to backup the original Lenovo BIOS firmware. These backups are tied to each system, and will not work on any other. For that, please refer to @uref{http://www.coreboot.org/Board:lenovo/x60/Installation,http://www.coreboot.org/Board:lenovo/x60/Installation}.} + +@strong{If you're using libreboot 20150518, note that there is a mistake in the flashing script. Apply this patch to the BASH script named @emph{flash} (this is the script for flashing libreboot into your X60): @uref{../resources/misc/patch/x60flashscript.patch,x60flashscript.patch}. This patch is merged in the main git repository, and in all releases after 20150518.} + +The first half of the procedure is as follows:@* $ @strong{sudo ./flash i945lenovo_firstflash @ref{#rom,yourrom.rom}.} + +You should see within the output the following:@* @strong{"Updated BUC.TS=1 - 64kb address ranges at 0xFFFE0000 and 0xFFFF0000 are swapped"}. + +You should also see within the output the following:@* @strong{"Your flash chip is in an unknown state"}, @strong{"FAILED"} and @strong{"DO NOT REBOOT OR POWEROFF"}@* Seeing this means that the operation was a @strong{resounding} success! @strong{DON'T PANIC}. + +See this link for more details: @uref{http://thread.gmane.org/gmane.linux.bios.flashrom/575,http://thread.gmane.org/gmane.linux.bios.flashrom/575}. + +If the above is what you see, then @strong{SHUT DOWN}. Wait a few seconds, and then boot; libreboot is running, but there is a 2nd procedure @strong{*needed*} (see below). + +When you have booted up again, you must also do this:@* $ @strong{sudo ./flash i945lenovo_secondflash @ref{#rom,yourrom.rom}} + +If flashing fails at this stage, try the following:@* $ @strong{sudo ./flashrom/i686/flashrom -p internal:laptop=force_I_want_a_brick -w @ref{#rom,yourrom.rom}} + +You should see within the output the following:@* @strong{"Updated BUC.TS=0 - 128kb address range 0xFFFE0000-0xFFFFFFFF is untranslated"} + +You should also see within the output the following:@* @strong{"Verifying flash... VERIFIED."} + +@ref{#pagetop,Back to top of page.} + +@node MacBook21 Initial installation guide if running the proprietary firmware +@chapter MacBook2,1: Initial installation guide (if running the proprietary firmware) +@anchor{#macbook21-initial-installation-guide-if-running-the-proprietary-firmware} +@strong{If you have a MacBook1,1, refer to @uref{../hcl/index.html#macbook11,../hcl/index.html#macbook11} for flashing instructions.} + +@strong{This is for the MacBook2,1 while running Apple EFI firmware. If you already have coreboot or libreboot running, then go to @ref{#flashrom,#flashrom} instead!} + +Be sure to read the information in @uref{../hcl/index.html#macbook21,../hcl/index.html#macbook21}. + +@strong{Warning: this guide will not instruct the user how to backup the original Apple EFI firmware. For that, please refer to @uref{http://www.coreboot.org/Board:apple/macbook21,http://www.coreboot.org/Board:apple/macbook21}.} + +@strong{If you are using libreboot_src or git, then make sure that you built the sources first (see @uref{../git/index.html#build,../git/index.html#build}).} + +Look at the @ref{#rom,list of ROM images} to see which image is compatible with your device. + +Use this flashing script, to install libreboot:@* $ @strong{sudo ./flash i945apple_firstflash @ref{#rom,yourrom.rom}} + +You should also see within the output the following:@* @strong{"Verifying flash... VERIFIED."} + +Shut down. + +@ref{#pagetop,Back to top of page.} + +Copyright © 2014, 2015 Francis Rowe <info@@gluglug.org.uk>@* Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license can be found at @uref{../resources/licenses/gfdl-1.3.txt,gfdl-1.3.txt} + +Updated versions of the license (when available) can be found at @uref{https://www.gnu.org/licenses/licenses.html,https://www.gnu.org/licenses/licenses.html} + +UNLESS OTHERWISE SEPARATELY UNDERTAKEN BY THE LICENSOR, TO THE EXTENT POSSIBLE, THE LICENSOR OFFERS THE LICENSED MATERIAL AS-IS AND AS-AVAILABLE, AND MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND CONCERNING THE LICENSED MATERIAL, WHETHER EXPRESS, IMPLIED, STATUTORY, OR OTHER. THIS INCLUDES, WITHOUT LIMITATION, WARRANTIES OF TITLE, MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NON-INFRINGEMENT, ABSENCE OF LATENT OR OTHER DEFECTS, ACCURACY, OR THE PRESENCE OR ABSENCE OF ERRORS, WHETHER OR NOT KNOWN OR DISCOVERABLE. WHERE DISCLAIMERS OF WARRANTIES ARE NOT ALLOWED IN FULL OR IN PART, THIS DISCLAIMER MAY NOT APPLY TO YOU. + +TO THE EXTENT POSSIBLE, IN NO EVENT WILL THE LICENSOR BE LIABLE TO YOU ON ANY LEGAL THEORY (INCLUDING, WITHOUT LIMITATION, NEGLIGENCE) OR OTHERWISE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, CONSEQUENTIAL, PUNITIVE, EXEMPLARY, OR OTHER LOSSES, COSTS, EXPENSES, OR DAMAGES ARISING OUT OF THIS PUBLIC LICENSE OR USE OF THE LICENSED MATERIAL, EVEN IF THE LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH LOSSES, COSTS, EXPENSES, OR DAMAGES. WHERE A LIMITATION OF LIABILITY IS NOT ALLOWED IN FULL OR IN PART, THIS LIMITATION MAY NOT APPLY TO YOU. + +The disclaimer of warranties and limitation of liability provided above shall be interpreted in a manner that, to the extent possible, most closely approximates an absolute disclaimer and waiver of all liability. + +@bye diff --git a/docs/src/install/kgpe-d16.texi b/docs/src/install/kgpe-d16.texi new file mode 100644 index 0000000..41a834b --- /dev/null +++ b/docs/src/install/kgpe-d16.texi @@ -0,0 +1,66 @@ +\input texinfo +@documentencoding UTF-8 + +@ifnottex +@paragraphindent 0 +@end ifnottex +@titlepage +@title KGPE-D16 external flashing instructions +@end titlepage + +@node Top +@top KGPE-D16 external flashing instructions + +@menu +* KGPE-D16 external flashing instructions:: +* KGPE-D16 boards and full systems with libreboot preinstalled:: +* External programmer:: +@end menu + +@node KGPE-D16 external flashing instructions +@chapter KGPE-D16 external flashing instructions +@anchor{#kgpe-d16-external-flashing-instructions} +Initial flashing instructions for X200. + +This guide is for those who want libreboot on their ThinkPad X200 while they still have the original Lenovo BIOS present. This guide can also be followed (adapted) if you brick your X200, to know how to recover. + +This guide is for those who want libreboot on their ASUS KGPE-D16 motherboard, while they still have the proprietary ASUS BIOS present. This guide can also be followed (adapted) if you brick you board, to know how to recover. + +For more general information about this board, refer to @uref{../hcl/kgpe-d16.html,../hcl/kgpe-d16.html}. + +TODO: show photos here, and other info. + +@itemize +@item +@ref{#preinstall,KGPE-D16 boards (and full systems) with libreboot preinstalled} +@item +@ref{#programmer,External programmer} +@end itemize + +@uref{index.html,Back to main index} + +@node KGPE-D16 boards and full systems with libreboot preinstalled +@chapter KGPE-D16 boards (and full systems) with libreboot preinstalled +@anchor{#kgpe-d16-boards-and-full-systems-with-libreboot-preinstalled} +If you don't want to install libreboot yourself, companies exist that sell these boards with libreboot pre-installed, along with a free GNU/Linux distribution. + +Check the @uref{../../suppliers,suppliers} page for more information. + +@node External programmer +@chapter External programmer +@anchor{#external-programmer} +Refer to @uref{bbb_setup.html,bbb_setup.html} for a guide on how to set up an external SPI programmer. + +The flash chip is in a PDIP 8 socket (SPI flash chip) on the motherboard, which you take out and then re-flash with libreboot, using the programmer. @strong{DO NOT} remove the chip with your hands. Use a chip extractor tool. + +Copyright © 2015 Francis Rowe <info@@gluglug.org.uk>@* Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license can be found at @uref{../resources/licenses/gfdl-1.3.txt,gfdl-1.3.txt} + +Updated versions of the license (when available) can be found at @uref{https://www.gnu.org/licenses/licenses.html,https://www.gnu.org/licenses/licenses.html} + +UNLESS OTHERWISE SEPARATELY UNDERTAKEN BY THE LICENSOR, TO THE EXTENT POSSIBLE, THE LICENSOR OFFERS THE LICENSED MATERIAL AS-IS AND AS-AVAILABLE, AND MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND CONCERNING THE LICENSED MATERIAL, WHETHER EXPRESS, IMPLIED, STATUTORY, OR OTHER. THIS INCLUDES, WITHOUT LIMITATION, WARRANTIES OF TITLE, MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NON-INFRINGEMENT, ABSENCE OF LATENT OR OTHER DEFECTS, ACCURACY, OR THE PRESENCE OR ABSENCE OF ERRORS, WHETHER OR NOT KNOWN OR DISCOVERABLE. WHERE DISCLAIMERS OF WARRANTIES ARE NOT ALLOWED IN FULL OR IN PART, THIS DISCLAIMER MAY NOT APPLY TO YOU. + +TO THE EXTENT POSSIBLE, IN NO EVENT WILL THE LICENSOR BE LIABLE TO YOU ON ANY LEGAL THEORY (INCLUDING, WITHOUT LIMITATION, NEGLIGENCE) OR OTHERWISE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, CONSEQUENTIAL, PUNITIVE, EXEMPLARY, OR OTHER LOSSES, COSTS, EXPENSES, OR DAMAGES ARISING OUT OF THIS PUBLIC LICENSE OR USE OF THE LICENSED MATERIAL, EVEN IF THE LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH LOSSES, COSTS, EXPENSES, OR DAMAGES. WHERE A LIMITATION OF LIABILITY IS NOT ALLOWED IN FULL OR IN PART, THIS LIMITATION MAY NOT APPLY TO YOU. + +The disclaimer of warranties and limitation of liability provided above shall be interpreted in a manner that, to the extent possible, most closely approximates an absolute disclaimer and waiver of all liability. + +@bye diff --git a/docs/src/install/r400_external.texi b/docs/src/install/r400_external.texi new file mode 100644 index 0000000..4d5518b --- /dev/null +++ b/docs/src/install/r400_external.texi @@ -0,0 +1,296 @@ +\input texinfo +@documentencoding UTF-8 + +@ifnottex +@paragraphindent 0 +@end ifnottex +@titlepage +@title ThinkPad R400: flashing tutorial (BeagleBone Black) +@end titlepage + +@node Top +@top ThinkPad R400: flashing tutorial (BeagleBone Black) + +@menu +* Flashing the R400 with a BeagleBone Black:: +* Libreboot T400:: +* LCD compatibly:: +* A note about CPUs:: +* A note about GPUs:: +* CPU paste required:: +* Flash chip size:: +* MAC address:: +* Initial BBB configuration:: +* Thermal paste IMPORTANT:: +* Wifi:: +* WWAN:: +* Memory:: +@end menu + +@node Flashing the R400 with a BeagleBone Black +@chapter Flashing the R400 with a BeagleBone Black +@anchor{#flashing-the-r400-with-a-beaglebone-black} +Initial flashing instructions for R400. + +This guide is for those who want libreboot on their ThinkPad R400 while they still have the original Lenovo BIOS present. This guide can also be followed (adapted) if you brick your R400, to know how to recover. + +Before following this section, please make sure to setup your libreboot ROM properly first. Although ROM images are provided pre-built in libreboot, there are some modifications that you need to make to the one you chose before flashing. (instructions referenced later in this guide) + +@uref{index.html,Back to main index} + +@node Libreboot T400 +@chapter Libreboot T400 +@anchor{#libreboot-t400} +You may also be interested in the smaller, more portable @uref{t400_external.html,Libreboot T400}. +@menu +* Serial port:: +@end menu + +@node Serial port +@section Serial port +@anchor{#serial-port} +EHCI debug might not be needed. It has been reported that the docking station for this laptop has a serial port, so it might be possible to use that instead. + +@node LCD compatibly +@chapter LCD compatibly +@anchor{#lcd-compatibly} +Not all LCD panels are compatible yet. See @uref{../hcl/gm45_lcd.html,../hcl/gm45_lcd.html}. + +@node A note about CPUs +@chapter A note about CPUs +@anchor{#a-note-about-cpus} +@uref{http://www.thinkwiki.org/wiki/Category:R400,ThinkWiki} has a list of CPUs for this system. The Core 2 Duo P8400 and P8600 are believed to work in libreboot. The Core 2 Duo T9600 was confirmed to work, so the T9400 probably also works. @strong{The Core 2 Duo T5870/5670 and Celeron M 575/585 are untested!} +@menu +* Quad-core CPUs:: +@end menu + +@node Quad-core CPUs +@section Quad-core CPUs +@anchor{#quad-core-cpus} +Although blocked by lenovobios (as was reported), it is reported that there are quad-core CPUs for GM45. This laptop has socketed CPUs, so it might be possible to use them (they are untested in coreboot; support may have to be added). Core 2 Quad Q9000, Q9100 or QX9300. + +Look at this link:@* @uref{https://en.wikipedia.org/wiki/List_of_Intel_Core_2_microprocessors#Quad-Core_Notebook_processors,https://en.wikipedia.org/wiki/List_of_Intel_Core_2_microprocessors#Quad-Core_Notebook_processors} + +@node A note about GPUs +@chapter A note about GPUs +@anchor{#a-note-about-gpus} +Some models have an Intel GPU, while others have both an ATI and an Intel GPU; this is referred to as "switchable graphics". In the @emph{BIOS setup} program for lenovobios, you can specify that the system will use one or the other (but not both). + +Libreboot is known to work on systems with only the Intel GPU, using native graphics initialization. On systems with switchable graphics, the Intel GPU is used and the ATI GPU is disabled, so native graphics initialization works all the same. + +@node CPU paste required +@chapter CPU paste required +@anchor{#cpu-paste-required} +See @ref{#paste,#paste}. + +@node Flash chip size +@chapter Flash chip size +@anchor{#flash-chip-size} +Use this to find out:@* # @strong{dmidecode | grep ROM\ Size}@* + +@ref{#pagetop,Back to top of page.} + +@node MAC address +@chapter MAC address +@anchor{#mac-address} +On the R400, the MAC address for the onboard gigabit ethernet chipset is stored inside the flash chip, along with other configuration data. + +Keep a note of the MAC address before disassembly; this is very important, because you will need to insert this into the libreboot ROM image before flashing it. It will be written in one of these locations: + +@image{../resources/images/t400/macaddress0,,,,jpg} @image{../resources/images/t400/macaddress1,,,,jpg} @image{../resources/images/x200/disassembly/0001,,,,jpg} + +@node Initial BBB configuration +@chapter Initial BBB configuration +@anchor{#initial-bbb-configuration} +Refer to @uref{bbb_setup.html,bbb_setup.html} for how to setup the BBB for flashing. + +The following shows how to connect clip to the BBB (on the P9 header), for SOIC-16 (clip: Pomona 5252): + +@verbatim +POMONA 5252 (correlate with the BBB guide) +=== ethernet jack and VGA port ==== + NC - - 21 + 1 - - 17 + NC - - NC + NC - - NC + NC - - NC + NC - - NC + 18 - - 3.3V (PSU) + 22 - - NC - this is pin 1 on the flash chip +=== SATA port === +This is how you will connect. Numbers refer to pin numbers on the BBB, on the plugs near the DC jack. +@end verbatim + +The following shows how to connect clip to the BBB (on the P9 header), for SOIC-8 (clip: Pomona 5250): + +@verbatim +POMONA 5250 (correlate with the BBB guide) +=== RAM slots ==== + 18 - - 1 + 22 - - NC + NC - - 21 + 3.3V (PSU) - - 17 - this is pin 1 on the flash chip +=== slot where the AC jack is connected === +This is how you will connect. Numbers refer to pin numbers on the BBB, on the plugs near the DC jack. +@end verbatim + +@menu +* Disassembly:: +@end menu + +@node Disassembly +@section Disassembly +@anchor{#disassembly} +Remove all screws:@* @image{../resources/images/r400/0000,,,,jpg}@* Remove the HDD and optical drive:@* @image{../resources/images/r400/0001,,,,jpg}@* Remove the hinge screws:@* @image{../resources/images/r400/0002,,,,jpg} @image{../resources/images/r400/0003,,,,jpg} + +Remove the palm rest and keyboard:@* @image{../resources/images/r400/0004,,,,jpg} @image{../resources/images/r400/0005,,,,jpg} + +Remove these screws, and then remove the bezel:@* @image{../resources/images/r400/0006,,,,jpg} @image{../resources/images/r400/0007,,,,jpg} + +Remove the speaker screws, but don't remove the speakers yet (just set them loose):@* @image{../resources/images/r400/0008,,,,jpg} @image{../resources/images/r400/0009,,,,jpg} @image{../resources/images/r400/0010,,,,jpg} + +Remove these screws, and then remove the metal plate:@* @image{../resources/images/r400/0011,,,,jpg} @image{../resources/images/r400/0012,,,,jpg} @image{../resources/images/r400/0013,,,,jpg} + +Remove the antennas from the wifi card, and then start unrouting them:@* @image{../resources/images/r400/0014,,,,jpg} @image{../resources/images/r400/0015,,,,jpg} @image{../resources/images/r400/0016,,,,jpg} @image{../resources/images/r400/0017,,,,jpg} @image{../resources/images/r400/0018,,,,jpg} @image{../resources/images/r400/0019,,,,jpg} + +Disconnect the LCD cable from the motherboard:@* @image{../resources/images/r400/0020,,,,jpg} @image{../resources/images/r400/0021,,,,jpg} @image{../resources/images/r400/0022,,,,jpg} @image{../resources/images/r400/0023,,,,jpg} + +Remove the hinge screws, and then remove the LCD panel:@* @image{../resources/images/r400/0024,,,,jpg} @image{../resources/images/r400/0025,,,,jpg} @image{../resources/images/r400/0026,,,,jpg} @image{../resources/images/r400/0027,,,,jpg} + +Remove this:@* @image{../resources/images/r400/0028,,,,jpg} @image{../resources/images/r400/0029,,,,jpg} + +Remove this long cable (there are 3 connections):@* @image{../resources/images/r400/0030,,,,jpg} @image{../resources/images/r400/0031,,,,jpg} @image{../resources/images/r400/0032,,,,jpg} @image{../resources/images/r400/0033,,,,jpg} + +Disconnect the speaker cable, and remove the speakers:@* @image{../resources/images/r400/0034,,,,jpg} + +Remove the heatsink screws, remove the fan and then remove the heatsink/fan:@* @image{../resources/images/r400/0035,,,,jpg} @image{../resources/images/r400/0036,,,,jpg} @image{../resources/images/r400/0037,,,,jpg} @image{../resources/images/r400/0038,,,,jpg} + +Remove the NVRAM battery:@* @image{../resources/images/r400/0039,,,,jpg} @image{../resources/images/r400/0040,,,,jpg} + +Remove this screw:@* @image{../resources/images/r400/0041,,,,jpg} @image{../resources/images/r400/0042,,,,jpg} + +Disconnect the AC jack:@* @image{../resources/images/r400/0043,,,,jpg} @image{../resources/images/r400/0044,,,,jpg} + +Remove this screw and then remove what is under it:@* @image{../resources/images/r400/0045,,,,jpg} + +Remove this:@* @image{../resources/images/r400/0046,,,,jpg} + +Lift the motherboard (which is still inside the cage) from the side on the right, removing it completely:@* @image{../resources/images/r400/0047,,,,jpg} @image{../resources/images/r400/0048,,,,jpg} + +Remove all screws, marking each hole so that you know where to re-insert them. You should place the screws in a layout corresponding to the order that they were in before removal: @image{../resources/images/r400/0049,,,,jpg} @image{../resources/images/r400/0050,,,,jpg} + +Remove the motherboard from the cage, and the SPI flash chip will be next to the memory slots:@* @image{../resources/images/r400/0051,,,,jpg} @image{../resources/images/r400/0052,,,,jpg} + +Connect your programmer, then connect GND and 3.3V@* @image{../resources/images/t400/0065,,,,jpg} @image{../resources/images/t400/0066,,,,jpg} @image{../resources/images/t400/0067,,,,jpg} @image{../resources/images/t400/0069,,,,jpg} @image{../resources/images/t400/0070,,,,jpg} @image{../resources/images/t400/0071,,,,jpg} + +A dedicated 3.3V PSU was used to create this guide, but at ATX PSU is also fine:@* @image{../resources/images/t400/0072,,,,jpg} + +Of course, make sure to turn on your PSU:@* @image{../resources/images/x200/disassembly/0013,,,,jpg} + +Now, you should be ready to install libreboot. + +Flashrom binaries for ARM (tested on a BBB) are distributed in libreboot_util. Alternatively, libreboot also distributes flashrom source code which can be built. + +Log in as root on your BBB, using the instructions in @uref{bbb_setup.html#bbb_access,bbb_setup.html#bbb_access}. + +Test that flashrom works:@* # @strong{./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512}@* In this case, the output was: + +@verbatim +flashrom v0.9.7-r1854 on Linux 3.8.13-bone47 (armv7l) +flashrom is free software, get the source code at http://www.flashrom.org +Calibrating delay loop... OK. +Found Macronix flash chip "MX25L6405(D)" (8192 kB, SPI) on linux_spi. +Found Macronix flash chip "MX25L6406E/MX25L6436E" (8192 kB, SPI) on linux_spi. +Found Macronix flash chip "MX25L6445E/MX25L6473E" (8192 kB, SPI) on linux_spi. +Multiple flash chip definitions match the detected chip(s): "MX25L6405(D)", "MX25L6406E/MX25L6436E", "MX25L6445E/MX25L6473E" +Please specify which chip definition to use with the -c <chipname> option. +@end verbatim + +How to backup factory.rom (change the -c option as neeed, for your flash chip):@* # @strong{./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -r factory.rom}@* # @strong{./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -r factory1.rom}@* # @strong{./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -r factory2.rom}@* Note: the @strong{-c} option is not required in libreboot's patched flashrom, because the redundant flash chip definitions in @emph{flashchips.c} have been removed.@* Now compare the 3 images:@* # @strong{sha512sum factory*.rom}@* If the hashes match, then just copy one of them (the factory.rom) to a safe place (on a drive connected to another system, not the BBB). This is useful for reverse engineering work, if there is a desirable behaviour in the original firmware that could be replicated in coreboot and libreboot. + +Follow the instructions at @uref{../hcl/gm45_remove_me.html#ich9gen,../hcl/gm45_remove_me.html#ich9gen} to change the MAC address inside the libreboot ROM image, before flashing it. Although there is a default MAC address inside the ROM image, this is not what you want. @strong{Make sure to always change the MAC address to one that is correct for your system.} + +Now flash it:@* # @strong{./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -w path/to/libreboot/rom/image.rom -V} + +@image{../resources/images/x200/disassembly/0015,,,,jpg} + +You might see errors, but if it says @strong{Verifying flash... VERIFIED} at the end, then it's flashed and should boot. If you see errors, try again (and again, and again); the message @strong{Chip content is identical to the requested image} is also an indication of a successful installation. + +Example output from running the command (see above): + +@verbatim +flashrom v0.9.7-r1854 on Linux 3.8.13-bone47 (armv7l) +flashrom is free software, get the source code at http://www.flashrom.org +Calibrating delay loop... OK. +Found Macronix flash chip "MX25L6405(D)" (8192 kB, SPI) on linux_spi. +Reading old flash chip contents... done. +Erasing and writing flash chip... FAILED at 0x00001000! Expected=0xff, Found=0x00, failed byte count from 0x00000000-0x0000ffff: 0xd716 +ERASE FAILED! +Reading current flash chip contents... done. Looking for another erase function. +Erase/write done. +Verifying flash... VERIFIED. +@end verbatim + +@ref{#pagetop,Back to top of page.} + +@node Thermal paste IMPORTANT +@chapter Thermal paste (IMPORTANT) +@anchor{#thermal-paste-important} +Because part of this procedure involved removing the heatsink, you will need to apply new paste. Arctic MX-4 is ok. You will also need isopropyl alcohol and an anti-static cloth to clean with. + +When re-installing the heatsink, you must first clean off all old paste with the alcohol/cloth. Then apply new paste. Arctic MX-4 is also much better than the default paste used on these systems. + +@image{../resources/images/t400/paste,,,,jpg} + +NOTE: the photo above is for illustration purposes only, and does not show how to properly apply the thermal paste. Other guides online detail the proper application procedure. + +@node Wifi +@chapter Wifi +@anchor{#wifi} +The R400 typically comes with an Intel wifi chipset, which does not work without proprietary software. For a list of wifi chipsets that work without proprietary software, see @uref{../hcl/index.html#recommended_wifi,../hcl/index.html#recommended_wifi}. + +Some R400 laptops might come with an Atheros chipset, but this is 802.11g only. + +It is recommended that you install a new wifi chipset. This can only be done after installing libreboot, because the original firmware has a whitelist of approved chips, and it will refuse to boot if you use an 'unauthorized' wifi card. + +The following photos show an Atheros AR5B95 being installed, to replace the Intel chip that this R400 came with:@* @image{../resources/images/t400/0012,,,,jpg} @image{../resources/images/t400/ar5b95,,,,jpg} + +@node WWAN +@chapter WWAN +@anchor{#wwan} +If you have a WWAN/3G card and/or sim card reader, remove them permanently. The WWAN-3G card has proprietary firmware inside; the technology is identical to what is used in mobile phones, so it can also track your movements. + +Not to be confused with wifi (wifi is fine). + +@node Memory +@chapter Memory +@anchor{#memory} +You need DDR3 SODIMM PC3-8500 RAM installed, in matching pairs (speed/size). Non-matching pairs won't work. You can also install a single module (meaning, one of the slots will be empty) in slot 0. + +Make sure that the RAM you buy is the 2Rx8 density. + +The following photo shows 8GiB (2x4GiB) of RAM installed:@* @image{../resources/images/t400/memory,,,,jpg} +@menu +* Boot it!:: +@end menu + +@node Boot it! +@section Boot it! +@anchor{#boot-it} +You should see something like this: + +@image{../resources/images/t400/boot0,,,,jpg} @image{../resources/images/t400/boot1,,,,jpg} + +Now @uref{../gnulinux/index.html,install GNU/Linux}. + +Copyright © 2014, 2015 Francis Rowe <info@@gluglug.org.uk>@* Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license can be found at @uref{../resources/licenses/gfdl-1.3.txt,gfdl-1.3.txt} + +Updated versions of the license (when available) can be found at @uref{https://www.gnu.org/licenses/licenses.html,https://www.gnu.org/licenses/licenses.html} + +UNLESS OTHERWISE SEPARATELY UNDERTAKEN BY THE LICENSOR, TO THE EXTENT POSSIBLE, THE LICENSOR OFFERS THE LICENSED MATERIAL AS-IS AND AS-AVAILABLE, AND MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND CONCERNING THE LICENSED MATERIAL, WHETHER EXPRESS, IMPLIED, STATUTORY, OR OTHER. THIS INCLUDES, WITHOUT LIMITATION, WARRANTIES OF TITLE, MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NON-INFRINGEMENT, ABSENCE OF LATENT OR OTHER DEFECTS, ACCURACY, OR THE PRESENCE OR ABSENCE OF ERRORS, WHETHER OR NOT KNOWN OR DISCOVERABLE. WHERE DISCLAIMERS OF WARRANTIES ARE NOT ALLOWED IN FULL OR IN PART, THIS DISCLAIMER MAY NOT APPLY TO YOU. + +TO THE EXTENT POSSIBLE, IN NO EVENT WILL THE LICENSOR BE LIABLE TO YOU ON ANY LEGAL THEORY (INCLUDING, WITHOUT LIMITATION, NEGLIGENCE) OR OTHERWISE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, CONSEQUENTIAL, PUNITIVE, EXEMPLARY, OR OTHER LOSSES, COSTS, EXPENSES, OR DAMAGES ARISING OUT OF THIS PUBLIC LICENSE OR USE OF THE LICENSED MATERIAL, EVEN IF THE LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH LOSSES, COSTS, EXPENSES, OR DAMAGES. WHERE A LIMITATION OF LIABILITY IS NOT ALLOWED IN FULL OR IN PART, THIS LIMITATION MAY NOT APPLY TO YOU. + +The disclaimer of warranties and limitation of liability provided above shall be interpreted in a manner that, to the extent possible, most closely approximates an absolute disclaimer and waiver of all liability. + +@bye diff --git a/docs/src/install/r500_external.texi b/docs/src/install/r500_external.texi new file mode 100644 index 0000000..5b46f7f --- /dev/null +++ b/docs/src/install/r500_external.texi @@ -0,0 +1,241 @@ +\input texinfo +@documentencoding UTF-8 + +@ifnottex +@paragraphindent 0 +@end ifnottex +@titlepage +@title ThinkPad R500: flashing tutorial (BeagleBone Black) +@end titlepage + +@node Top +@top ThinkPad R500: flashing tutorial (BeagleBone Black) + +@menu +* Flashing the R500 with a BeagleBone Black:: +* LCD compatibly:: +* A note about CPUs:: +* A note about GPUs:: +* CPU paste required:: +* Flash chip size:: +* MAC address:: +* Initial BBB configuration:: +* Thermal paste IMPORTANT:: +* Wifi:: +* WWAN:: +* Memory:: +@end menu + +@node Flashing the R500 with a BeagleBone Black +@chapter Flashing the R500 with a BeagleBone Black +@anchor{#flashing-the-r500-with-a-beaglebone-black} +Initial flashing instructions for R500. + +This guide is for those who want libreboot on their ThinkPad R500 while they still have the original Lenovo BIOS present. This guide can also be followed (adapted) if you brick your R500, to know how to recover. + +Before following this section, please make sure to setup your libreboot ROM properly first. Although ROM images are provided pre-built in libreboot, there are some modifications that you need to make to the one you chose before flashing. (instructions referenced later in this guide) + +@strong{NOTE: This board is unsupported in libreboot 20150518. To use it in libreboot, for now, you must build for it from source using the libreboot git repository.} + +@uref{index.html,Back to main index} +@menu +* Serial port:: +@end menu + +@node Serial port +@section Serial port +@anchor{#serial-port} +EHCI debug might not be needed. It has been reported that the docking station for this laptop has a serial port, so it might be possible to use that instead. + +@node LCD compatibly +@chapter LCD compatibly +@anchor{#lcd-compatibly} +Not all LCD panels are known to be compatible yet. See @uref{../hcl/gm45_lcd.html,../hcl/gm45_lcd.html}. + +@node A note about CPUs +@chapter A note about CPUs +@anchor{#a-note-about-cpus} +@uref{http://www.thinkwiki.org/wiki/Category:R500,ThinkWiki} has a list of CPUs for this system. The Core 2 Duo P8400, P8600 and P8700 are believed to work in libreboot. The Core 2 Duo T9600 was confirmed to work (on a different laptop, but still GM45), so the T9400 probably also works. @strong{The Core 2 Duo T5870/5670 and Celeron M 575/585 are untested!} +@menu +* Quad-core CPUs:: +@end menu + +@node Quad-core CPUs +@section Quad-core CPUs +@anchor{#quad-core-cpus} +Although blocked by lenovobios (as was reported), it is reported that there are quad-core CPUs for GM45. This laptop has socketed CPUs, so it might be possible to use them (they are untested in coreboot; support may have to be added). Core 2 Quad Q9000, Q9100 or QX9300. + +Look at this link:@* @uref{https://en.wikipedia.org/wiki/List_of_Intel_Core_2_microprocessors#Quad-Core_Notebook_processors,https://en.wikipedia.org/wiki/List_of_Intel_Core_2_microprocessors#Quad-Core_Notebook_processors} + +@node A note about GPUs +@chapter A note about GPUs +@anchor{#a-note-about-gpus} +@uref{http://www.thinkwiki.org/wiki/Category:R500,ThinkWiki} lists two possible GPUs: Intel or ATI. Only the Intel GPUs work in libreboot; the ATI GPUs require a proprietary Video BIOS, and so those are unsupported in libreboot. + +On other GM45 laptops in libreboot (e.g. T400, T500), so-called @emph{switchable graphics} is used, which means that the laptop will have @strong{both} an ATI and Intel GPU, or it will only have Intel, depending on which variation you have. On the systems with ATI and Intel, you can disable the ATI GPU and use only the Intel GPU, which works in libreboot. + +@strong{It is unknown whether R500 laptops with an ATI GPU still have an Intel GPU, where you could disable the ATI GPU and use the Intel GPU. These are budget laptops, so it's highly likely that Lenovo decided on this model to ship with one GPU or the other, but not both (GPUs cost money).} + +@strong{It is **HIGHLY** recommended, when ordering an R500 laptop, to **ENSURE** that the one you're ordering has an Intel GPU.} + +@node CPU paste required +@chapter CPU paste required +@anchor{#cpu-paste-required} +See @ref{#paste,#paste}. + +@node Flash chip size +@chapter Flash chip size +@anchor{#flash-chip-size} +Use this to find out:@* # @strong{dmidecode | grep ROM\ Size}@* + +It is believed that all R500 laptops have only SOIC-8 (4MiB) chips. + +@ref{#pagetop,Back to top of page.} + +@node MAC address +@chapter MAC address +@anchor{#mac-address} +Unlike other GM45 thinkpads, the R500 has a different onboard gigabit NIC, where the MAC address is built-in. You do not need to change the MAC address at all on this laptop; simply flash the provided ROM images, as-is. + +@node Initial BBB configuration +@chapter Initial BBB configuration +@anchor{#initial-bbb-configuration} +Refer to @uref{bbb_setup.html,bbb_setup.html} for how to setup the BBB for flashing. + +The following shows how to connect clip to the BBB (on the P9 header), for SOIC-8 (clip: Pomona 5250): + +@verbatim +POMONA 5250 (correlate with the BBB guide) +=== VGA and ethernet socket === + 18 - - 1 + 22 - - NC + NC - - 21 + 3.3V (PSU) - - 17 - this is pin 1 on the flash chip +=== DVD drive === +This is how you will connect. Numbers refer to pin numbers on the BBB, on the plugs near the DC jack. +@end verbatim + +@menu +* Disassembly:: +@end menu + +@node Disassembly +@section Disassembly +@anchor{#disassembly} +@image{../resources/images/r500/0001,,,,JPG} @image{../resources/images/r500/0002,,,,JPG} @image{../resources/images/r500/0003,,,,JPG} @image{../resources/images/r500/0004,,,,JPG} @image{../resources/images/r500/0005,,,,JPG} @image{../resources/images/r500/0006,,,,JPG} @image{../resources/images/r500/0007,,,,JPG} @image{../resources/images/r500/0008,,,,JPG} @image{../resources/images/r500/0009,,,,JPG} @image{../resources/images/r500/0010,,,,JPG} @image{../resources/images/r500/0011,,,,JPG} @image{../resources/images/r500/0012,,,,JPG} @image{../resources/images/r500/0013,,,,JPG} @image{../resources/images/r500/0014,,,,JPG} @image{../resources/images/r500/0015,,,,JPG} @image{../resources/images/r500/0016,,,,JPG} @image{../resources/images/r500/0017,,,,JPG} @image{../resources/images/r500/0018,,,,JPG} @image{../resources/images/r500/0019,,,,JPG} @image{../resources/images/r500/0020,,,,JPG} @image{../resources/images/r500/0021,,,,JPG} @image{../resources/images/r500/0022,,,,JPG} @image{../resources/images/r500/0023,,,,JPG} @image{../resources/images/r500/0024,,,,JPG} @image{../resources/images/r500/0025,,,,JPG} @image{../resources/images/r500/0026,,,,JPG} @image{../resources/images/r500/0027,,,,JPG} @image{../resources/images/r500/0028,,,,JPG} @image{../resources/images/r500/0029,,,,JPG} @image{../resources/images/r500/0030,,,,JPG} @image{../resources/images/r500/0031,,,,JPG} + +Remove the motherboard from the cage, and the SPI flash chip will be next to the memory slots:@* @image{../resources/images/r500/0032,,,,JPG} @image{../resources/images/r500/flashchip,,,,jpg} + +The following image is for illustration only, to show how a SOIC-8 clip is connected. This photo is from a T500, which has a different arrangement to the R500:@* @image{../resources/images/t500/0061,,,,jpg} + +Connect your programmer, then connect GND and 3.3V@* @image{../resources/images/t400/0067,,,,jpg} @image{../resources/images/t400/0069,,,,jpg} @image{../resources/images/t400/0070,,,,jpg} @image{../resources/images/t400/0071,,,,jpg} + +A dedicated 3.3V PSU was used to create this guide, but at ATX PSU is also fine:@* @image{../resources/images/t400/0072,,,,jpg} + +Of course, make sure to turn on your PSU:@* @image{../resources/images/x200/disassembly/0013,,,,jpg} + +Now, you should be ready to install libreboot. + +Flashrom binaries for ARM (tested on a BBB) are distributed in libreboot_util. Alternatively, libreboot also distributes flashrom source code which can be built. + +Log in as root on your BBB, using the instructions in @uref{bbb_setup.html#bbb_access,bbb_setup.html#bbb_access}. + +Test that flashrom works:@* # @strong{./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512}@* In this case, the output was: + +@verbatim +flashrom v0.9.7-r1854 on Linux 3.8.13-bone47 (armv7l) +flashrom is free software, get the source code at http://www.flashrom.org +Calibrating delay loop... OK. +Found Macronix flash chip "MX25L6405(D)" (8192 kB, SPI) on linux_spi. +Found Macronix flash chip "MX25L6406E/MX25L6436E" (8192 kB, SPI) on linux_spi. +Found Macronix flash chip "MX25L6445E/MX25L6473E" (8192 kB, SPI) on linux_spi. +Multiple flash chip definitions match the detected chip(s): "MX25L6405(D)", "MX25L6406E/MX25L6436E", "MX25L6445E/MX25L6473E" +Please specify which chip definition to use with the -c <chipname> option. +@end verbatim + +How to backup factory.rom (change the -c option as neeed, for your flash chip):@* # @strong{./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -r factory.rom}@* # @strong{./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -r factory1.rom}@* # @strong{./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -r factory2.rom}@* Note: the @strong{-c} option is not required in libreboot's patched flashrom, because the redundant flash chip definitions in @emph{flashchips.c} have been removed.@* Now compare the 3 images:@* # @strong{sha512sum factory*.rom}@* If the hashes match, then just copy one of them (the factory.rom) to a safe place (on a drive connected to another system, not the BBB). This is useful for reverse engineering work, if there is a desirable behaviour in the original firmware that could be replicated in coreboot and libreboot. + +Now flash it:@* # @strong{./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -w path/to/libreboot/rom/image.rom -V} + +@image{../resources/images/x200/disassembly/0015,,,,jpg} + +You might see errors, but if it says @strong{Verifying flash... VERIFIED} at the end, then it's flashed and should boot. If you see errors, try again (and again, and again); the message @strong{Chip content is identical to the requested image} is also an indication of a successful installation. + +Example output from running the command (see above): + +@verbatim +flashrom v0.9.7-r1854 on Linux 3.8.13-bone47 (armv7l) +flashrom is free software, get the source code at http://www.flashrom.org +Calibrating delay loop... OK. +Found Macronix flash chip "MX25L6405(D)" (8192 kB, SPI) on linux_spi. +Reading old flash chip contents... done. +Erasing and writing flash chip... FAILED at 0x00001000! Expected=0xff, Found=0x00, failed byte count from 0x00000000-0x0000ffff: 0xd716 +ERASE FAILED! +Reading current flash chip contents... done. Looking for another erase function. +Erase/write done. +Verifying flash... VERIFIED. +@end verbatim + +@ref{#pagetop,Back to top of page.} + +@node Thermal paste IMPORTANT +@chapter Thermal paste (IMPORTANT) +@anchor{#thermal-paste-important} +Because part of this procedure involved removing the heatsink, you will need to apply new paste. Arctic Silver 5 is ok. You will also need isopropyl alcohol and an anti-static cloth to clean with. + +When re-installing the heatsink, you must first clean off all old paste with the alcohol/cloth. Then apply new paste. AS5 is also much better than the default paste used on these systems. + +@image{../resources/images/t400/paste,,,,jpg} + +NOTE: the photo above is for illustration purposes only, and does not show how to properly apply the thermal paste. Other guides online detail the proper application procedure. + +@node Wifi +@chapter Wifi +@anchor{#wifi} +The R500 typically comes with an Intel wifi chipset, which does not work without proprietary software. For a list of wifi chipsets that work without proprietary software, see @uref{../hcl/index.html#recommended_wifi,../hcl/index.html#recommended_wifi}. + +Some R500 laptops might come with an Atheros chipset, but this is 802.11g only. + +It is recommended that you install a new wifi chipset. This can only be done after installing libreboot, because the original firmware has a whitelist of approved chips, and it will refuse to boot if you use an 'unauthorized' wifi card. + +The following photos show an Atheros AR5B95 being installed, to replace the Intel chip that this R500 came with:@* @image{../resources/images/t400/0012,,,,jpg} @image{../resources/images/t400/ar5b95,,,,jpg} + +@node WWAN +@chapter WWAN +@anchor{#wwan} +If you have a WWAN/3G card and/or sim card reader, remove them permanently. The WWAN-3G card has proprietary firmware inside; the technology is identical to what is used in mobile phones, so it can also track your movements. + +Not to be confused with wifi (wifi is fine). + +@node Memory +@chapter Memory +@anchor{#memory} +You need DDR3 SODIMM PC3-8500 RAM installed, in matching pairs (speed/size). Non-matching pairs won't work. You can also install a single module (meaning, one of the slots will be empty) in slot 0. + +Make sure that the RAM you buy is the 2Rx8 density. + +The following photo shows 8GiB (2x4GiB) of RAM installed:@* @image{../resources/images/t400/memory,,,,jpg} +@menu +* Boot it!:: +@end menu + +@node Boot it! +@section Boot it! +@anchor{#boot-it} +You should see something like this: + +@image{../resources/images/t400/boot0,,,,jpg} @image{../resources/images/t400/boot1,,,,jpg} + +Now @uref{../gnulinux/index.html,install GNU/Linux}. + +Copyright © 2015 Francis Rowe <info@@gluglug.org.uk>@* Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license can be found at @uref{../resources/licenses/gfdl-1.3.txt,gfdl-1.3.txt} + +Updated versions of the license (when available) can be found at @uref{https://www.gnu.org/licenses/licenses.html,https://www.gnu.org/licenses/licenses.html} + +UNLESS OTHERWISE SEPARATELY UNDERTAKEN BY THE LICENSOR, TO THE EXTENT POSSIBLE, THE LICENSOR OFFERS THE LICENSED MATERIAL AS-IS AND AS-AVAILABLE, AND MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND CONCERNING THE LICENSED MATERIAL, WHETHER EXPRESS, IMPLIED, STATUTORY, OR OTHER. THIS INCLUDES, WITHOUT LIMITATION, WARRANTIES OF TITLE, MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NON-INFRINGEMENT, ABSENCE OF LATENT OR OTHER DEFECTS, ACCURACY, OR THE PRESENCE OR ABSENCE OF ERRORS, WHETHER OR NOT KNOWN OR DISCOVERABLE. WHERE DISCLAIMERS OF WARRANTIES ARE NOT ALLOWED IN FULL OR IN PART, THIS DISCLAIMER MAY NOT APPLY TO YOU. + +TO THE EXTENT POSSIBLE, IN NO EVENT WILL THE LICENSOR BE LIABLE TO YOU ON ANY LEGAL THEORY (INCLUDING, WITHOUT LIMITATION, NEGLIGENCE) OR OTHERWISE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, CONSEQUENTIAL, PUNITIVE, EXEMPLARY, OR OTHER LOSSES, COSTS, EXPENSES, OR DAMAGES ARISING OUT OF THIS PUBLIC LICENSE OR USE OF THE LICENSED MATERIAL, EVEN IF THE LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH LOSSES, COSTS, EXPENSES, OR DAMAGES. WHERE A LIMITATION OF LIABILITY IS NOT ALLOWED IN FULL OR IN PART, THIS LIMITATION MAY NOT APPLY TO YOU. + +The disclaimer of warranties and limitation of liability provided above shall be interpreted in a manner that, to the extent possible, most closely approximates an absolute disclaimer and waiver of all liability. + +@bye diff --git a/docs/src/install/t400_external.texi b/docs/src/install/t400_external.texi new file mode 100644 index 0000000..7afe4bd --- /dev/null +++ b/docs/src/install/t400_external.texi @@ -0,0 +1,296 @@ +\input texinfo +@documentencoding UTF-8 + +@ifnottex +@paragraphindent 0 +@end ifnottex +@titlepage +@title ThinkPad T400: flashing tutorial (BeagleBone Black) +@end titlepage + +@node Top +@top ThinkPad T400: flashing tutorial (BeagleBone Black) + +@menu +* Flashing the T400 with a BeagleBone Black:: +* T400 laptops with libreboot pre-installed:: +* LCD compatibly:: +* A note about CPUs:: +* A note about GPUs:: +* CPU paste required:: +* Flash chip size:: +* MAC address:: +* Initial BBB configuration:: +* Thermal paste IMPORTANT:: +* Wifi:: +* WWAN:: +* Memory:: +@end menu + +@node Flashing the T400 with a BeagleBone Black +@chapter Flashing the T400 with a BeagleBone Black +@anchor{#flashing-the-t400-with-a-beaglebone-black} +Initial flashing instructions for T400. + +This guide is for those who want libreboot on their ThinkPad T400 while they still have the original Lenovo BIOS present. This guide can also be followed (adapted) if you brick your T400, to know how to recover. + +@uref{index.html,Back to main index} + +@node T400 laptops with libreboot pre-installed +@chapter T400 laptops with libreboot pre-installed +@anchor{#t400-laptops-with-libreboot-pre-installed} +If you don't want to install libreboot yourself, companies exist that sell these laptops with libreboot pre-installed, along with a free GNU/Linux distribution. + +Check the @uref{../../suppliers,suppliers} page for more information. +@menu +* Serial port:: +@end menu + +@node Serial port +@section Serial port +@anchor{#serial-port} +EHCI debug might not be needed. It has been reported that the docking station for this laptop has a serial port, so it might be possible to use that instead. + +@node LCD compatibly +@chapter LCD compatibly +@anchor{#lcd-compatibly} +Not all LCD panels are compatible yet. See @uref{../hcl/gm45_lcd.html,../hcl/gm45_lcd.html}. + +@node A note about CPUs +@chapter A note about CPUs +@anchor{#a-note-about-cpus} +@uref{http://www.thinkwiki.org/wiki/Category:T400,ThinkWiki} has a list of CPUs for this system. The Core 2 Duo P8400, P8600 and P8700 are believed to work in libreboot. The T9600 was confirmed to work, so the T9500/T9550 probably also work. +@menu +* Quad-core CPUs:: +@end menu + +@node Quad-core CPUs +@section Quad-core CPUs +@anchor{#quad-core-cpus} +Although blocked by lenovobios (as was reported), it is reported that there are quad-core CPUs for GM45. This laptop has socketed CPUs, so it might be possible to use them (they are untested in coreboot; support may have to be added). Core 2 Quad Q9000, Q9100 or QX9300. + +Look at this link:@* @uref{https://en.wikipedia.org/wiki/List_of_Intel_Core_2_microprocessors#Quad-Core_Notebook_processors,https://en.wikipedia.org/wiki/List_of_Intel_Core_2_microprocessors#Quad-Core_Notebook_processors} + +@node A note about GPUs +@chapter A note about GPUs +@anchor{#a-note-about-gpus} +Some models have an Intel GPU, while others have both an ATI and an Intel GPU; this is referred to as "switchable graphics". In the @emph{BIOS setup} program for lenovobios, you can specify that the system will use one or the other (but not both). + +Libreboot is known to work on systems with only the Intel GPU, using native graphics initialization. On systems with switchable graphics, the Intel GPU is used and the ATI GPU is disabled, so native graphics initialization works all the same. + +@node CPU paste required +@chapter CPU paste required +@anchor{#cpu-paste-required} +See @ref{#paste,#paste}. + +@node Flash chip size +@chapter Flash chip size +@anchor{#flash-chip-size} +Use this to find out:@* # @strong{dmidecode | grep ROM\ Size} + +@ref{#pagetop,Back to top of page.} + +@node MAC address +@chapter MAC address +@anchor{#mac-address} +On the T400, the MAC address for the onboard gigabit ethernet chipset is stored inside the flash chip, along with other configuration data. + +Keep a note of the MAC address before disassembly; this is very important, because you will need to insert this into the libreboot ROM image before flashing it. It will be written in one of these locations: + +@image{../resources/images/t400/macaddress0,,,,jpg} @image{../resources/images/t400/macaddress1,,,,jpg} @image{../resources/images/x200/disassembly/0001,,,,jpg} + +@node Initial BBB configuration +@chapter Initial BBB configuration +@anchor{#initial-bbb-configuration} +Refer to @uref{bbb_setup.html,bbb_setup.html} for how to configure the BBB for flashing. + +The following shows how to connect clip to the BBB (on the P9 header), for SOIC-16 (clip: Pomona 5252): + +@verbatim +POMONA 5252 (correlate with the BBB guide) +=== ethernet jack and VGA port ==== + NC - - 21 + 1 - - 17 + NC - - NC + NC - - NC + NC - - NC + NC - - NC + 18 - - 3.3V (PSU) + 22 - - NC - this is pin 1 on the flash chip +=== SATA port === +This is how you will connect. Numbers refer to pin numbers on the BBB, on the plugs near the DC jack. +@end verbatim + +The following shows how to connect clip to the BBB (on the P9 header), for SOIC-8 (clip: Pomona 5250): + +@verbatim +POMONA 5250 (correlate with the BBB guide) +=== RAM slots ==== + 18 - - 1 + 22 - - NC + NC - - 21 + 3.3V (PSU) - - 17 - this is pin 1 on the flash chip +=== slot where the AC jack is connected === +This is how you will connect. Numbers refer to pin numbers on the BBB, on the plugs near the DC jack. +@end verbatim + +@menu +* The procedure:: +@end menu + +@node The procedure +@section The procedure +@anchor{#the-procedure} +Remove @emph{all} screws, placing them in the order that you removed them:@* @image{../resources/images/t400/0001,,,,jpg} @image{../resources/images/t400/0002,,,,jpg} + +Remove those three screws then remove the rear bezel:@* @image{../resources/images/t400/0003,,,,jpg} @image{../resources/images/t400/0004,,,,jpg} @image{../resources/images/t400/0005,,,,jpg} @image{../resources/images/t400/0006,,,,jpg} + +Remove the speakers:@* @image{../resources/images/t400/0007,,,,jpg} @image{../resources/images/t400/0008,,,,jpg} @image{../resources/images/t400/0009,,,,jpg} @image{../resources/images/t400/0010,,,,jpg} @image{../resources/images/t400/0011,,,,jpg} + +Remove the wifi:@* @image{../resources/images/t400/0012,,,,jpg} @image{../resources/images/t400/0013,,,,jpg} + +Remove this cable:@* @image{../resources/images/t400/0014,,,,jpg} @image{../resources/images/t400/0015,,,,jpg} @image{../resources/images/t400/0016,,,,jpg} @image{../resources/images/t400/0017,,,,jpg} @image{../resources/images/t400/0018,,,,jpg} + +Unroute those antenna wires:@* @image{../resources/images/t400/0019,,,,jpg} @image{../resources/images/t400/0020,,,,jpg} @image{../resources/images/t400/0021,,,,jpg} @image{../resources/images/t400/0022,,,,jpg} @image{../resources/images/t400/0023,,,,jpg} + +Remove the LCD assembly:@* @image{../resources/images/t400/0024,,,,jpg} @image{../resources/images/t400/0025,,,,jpg} @image{../resources/images/t400/0026,,,,jpg} @image{../resources/images/t400/0027,,,,jpg} @image{../resources/images/t400/0028,,,,jpg} @image{../resources/images/t400/0029,,,,jpg} @image{../resources/images/t400/0030,,,,jpg} @image{../resources/images/t400/0031,,,,jpg} + +Disconnect the NVRAM battery:@* @image{../resources/images/t400/0033,,,,jpg} + +Disconnect the fan:@* @image{../resources/images/t400/0034,,,,jpg} + +Unscrew these:@* @image{../resources/images/t400/0035,,,,jpg} @image{../resources/images/t400/0036,,,,jpg} @image{../resources/images/t400/0037,,,,jpg} @image{../resources/images/t400/0038,,,,jpg} + +Unscrew the heatsink, then lift it off:@* @image{../resources/images/t400/0039,,,,jpg} @image{../resources/images/t400/0040,,,,jpg} + +Disconnect the power jack:@* @image{../resources/images/t400/0041,,,,jpg} @image{../resources/images/t400/0042,,,,jpg} + +Loosen this:@* @image{../resources/images/t400/0043,,,,jpg} + +Remove this:@* @image{../resources/images/t400/0044,,,,jpg} @image{../resources/images/t400/0045,,,,jpg} @image{../resources/images/t400/0046,,,,jpg} @image{../resources/images/t400/0047,,,,jpg} @image{../resources/images/t400/0048,,,,jpg} + +Unscrew these:@* @image{../resources/images/t400/0049,,,,jpg} @image{../resources/images/t400/0050,,,,jpg} + +Remove this:@* @image{../resources/images/t400/0051,,,,jpg} @image{../resources/images/t400/0052,,,,jpg} + +Unscrew this:@* @image{../resources/images/t400/0053,,,,jpg} + +Remove the motherboard (the cage is still attached) from the right hand side, then lift it out:@* @image{../resources/images/t400/0054,,,,jpg} @image{../resources/images/t400/0055,,,,jpg} @image{../resources/images/t400/0056,,,,jpg} + +Remove these screws, placing the screws in the same layout and marking each screw hole (so that you know what ones to put the screws back into later): @image{../resources/images/t400/0057,,,,jpg} @image{../resources/images/t400/0058,,,,jpg} @image{../resources/images/t400/0059,,,,jpg} @image{../resources/images/t400/0060,,,,jpg} @image{../resources/images/t400/0061,,,,jpg} @image{../resources/images/t400/0062,,,,jpg} + +Separate the motherboard:@* @image{../resources/images/t400/0063,,,,jpg} @image{../resources/images/t400/0064,,,,jpg} + +Connect your programmer, then connect GND and 3.3V@* @image{../resources/images/t400/0065,,,,jpg} @image{../resources/images/t400/0066,,,,jpg} @image{../resources/images/t400/0067,,,,jpg} @image{../resources/images/t400/0069,,,,jpg} @image{../resources/images/t400/0070,,,,jpg} @image{../resources/images/t400/0071,,,,jpg} + +A dedicated 3.3V PSU was used to create this guide, but at ATX PSU is also fine:@* @image{../resources/images/t400/0072,,,,jpg} + +Of course, make sure to turn on your PSU:@* @image{../resources/images/x200/disassembly/0013,,,,jpg} + +Now, you should be ready to install libreboot. + +Flashrom binaries for ARM (tested on a BBB) are distributed in libreboot_util. Alternatively, libreboot also distributes flashrom source code which can be built. + +Log in as root on your BBB, using the instructions in @uref{bbb_setup.html#bbb_access,bbb_setup.html#bbb_access}. + +Test that flashrom works:@* # @strong{./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512}@* In this case, the output was: + +@verbatim +flashrom v0.9.7-r1854 on Linux 3.8.13-bone47 (armv7l) +flashrom is free software, get the source code at http://www.flashrom.org +Calibrating delay loop... OK. +Found Macronix flash chip "MX25L6405(D)" (8192 kB, SPI) on linux_spi. +Found Macronix flash chip "MX25L6406E/MX25L6436E" (8192 kB, SPI) on linux_spi. +Found Macronix flash chip "MX25L6445E/MX25L6473E" (8192 kB, SPI) on linux_spi. +Multiple flash chip definitions match the detected chip(s): "MX25L6405(D)", "MX25L6406E/MX25L6436E", "MX25L6445E/MX25L6473E" +Please specify which chip definition to use with the -c <chipname> option. +@end verbatim + +How to backup factory.rom (change the -c option as neeed, for your flash chip):@* # @strong{./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -r factory.rom}@* # @strong{./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -r factory1.rom}@* # @strong{./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -r factory2.rom}@* Note: the @strong{-c} option is not required in libreboot's patched flashrom, because the redundant flash chip definitions in @emph{flashchips.c} have been removed.@* Now compare the 3 images:@* # @strong{sha512sum factory*.rom}@* If the hashes match, then just copy one of them (the factory.rom) to a safe place (on a drive connected to another system, not the BBB). This is useful for reverse engineering work, if there is a desirable behaviour in the original firmware that could be replicated in coreboot and libreboot. + +Follow the instructions at @uref{../hcl/gm45_remove_me.html#ich9gen,../hcl/gm45_remove_me.html#ich9gen} to change the MAC address inside the libreboot ROM image, before flashing it. Although there is a default MAC address inside the ROM image, this is not what you want. @strong{Make sure to always change the MAC address to one that is correct for your system.} + +Now flash it:@* # @strong{./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -w path/to/libreboot/rom/image.rom -V} + +@image{../resources/images/x200/disassembly/0015,,,,jpg} + +You might see errors, but if it says @strong{Verifying flash... VERIFIED} at the end, then it's flashed and should boot. If you see errors, try again (and again, and again); the message @strong{Chip content is identical to the requested image} is also an indication of a successful installation. + +Example output from running the command (see above): + +@verbatim +flashrom v0.9.7-r1854 on Linux 3.8.13-bone47 (armv7l) +flashrom is free software, get the source code at http://www.flashrom.org +Calibrating delay loop... OK. +Found Macronix flash chip "MX25L6405(D)" (8192 kB, SPI) on linux_spi. +Reading old flash chip contents... done. +Erasing and writing flash chip... FAILED at 0x00001000! Expected=0xff, Found=0x00, failed byte count from 0x00000000-0x0000ffff: 0xd716 +ERASE FAILED! +Reading current flash chip contents... done. Looking for another erase function. +Erase/write done. +Verifying flash... VERIFIED. +@end verbatim + +@ref{#pagetop,Back to top of page.} + +@node Thermal paste IMPORTANT +@chapter Thermal paste (IMPORTANT) +@anchor{#thermal-paste-important} +Because part of this procedure involved removing the heatsink, you will need to apply new paste. Arctic MX-4 is ok. You will also need isopropyl alcohol and an anti-static cloth to clean with. + +When re-installing the heatsink, you must first clean off all old paste with the alcohol/cloth. Then apply new paste. Arctic MX-4 is also much better than the default paste used on these systems. + +@image{../resources/images/t400/paste,,,,jpg} + +NOTE: the photo above is for illustration purposes only, and does not show how to properly apply the thermal paste. Other guides online detail the proper application procedure. + +@node Wifi +@chapter Wifi +@anchor{#wifi} +The T400 typically comes with an Intel wifi chipset, which does not work without proprietary software. For a list of wifi chipsets that work without proprietary software, see @uref{../hcl/index.html#recommended_wifi,../hcl/index.html#recommended_wifi}. + +Some T400 laptops might come with an Atheros chipset, but this is 802.11g only. + +It is recommended that you install a new wifi chipset. This can only be done after installing libreboot, because the original firmware has a whitelist of approved chips, and it will refuse to boot if you use an 'unauthorized' wifi card. + +The following photos show an Atheros AR5B95 being installed, to replace the Intel chip that this T400 came with:@* @image{../resources/images/t400/0012,,,,jpg} @image{../resources/images/t400/ar5b95,,,,jpg} + +@node WWAN +@chapter WWAN +@anchor{#wwan} +If you have a WWAN/3G card and/or sim card reader, remove them permanently. The WWAN-3G card has proprietary firmware inside; the technology is identical to what is used in mobile phones, so it can also track your movements. + +Not to be confused with wifi (wifi is fine). + +@node Memory +@chapter Memory +@anchor{#memory} +You need DDR3 SODIMM PC3-8500 RAM installed, in matching pairs (speed/size). Non-matching pairs won't work. You can also install a single module (meaning, one of the slots will be empty) in slot 0. + +Make sure that the RAM you buy is the 2Rx8 density. + +The following photo shows 8GiB (2x4GiB) of RAM installed:@* @image{../resources/images/t400/memory,,,,jpg} +@menu +* Boot it!:: +@end menu + +@node Boot it! +@section Boot it! +@anchor{#boot-it} +You should see something like this: + +@image{../resources/images/t400/boot0,,,,jpg} @image{../resources/images/t400/boot1,,,,jpg} + +Now @uref{../gnulinux/index.html,install GNU/Linux}. + +Copyright © 2015 Francis Rowe <info@@gluglug.org.uk>@* Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license can be found at @uref{../resources/licenses/gfdl-1.3.txt,gfdl-1.3.txt} + +Updated versions of the license (when available) can be found at @uref{https://www.gnu.org/licenses/licenses.html,https://www.gnu.org/licenses/licenses.html} + +UNLESS OTHERWISE SEPARATELY UNDERTAKEN BY THE LICENSOR, TO THE EXTENT POSSIBLE, THE LICENSOR OFFERS THE LICENSED MATERIAL AS-IS AND AS-AVAILABLE, AND MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND CONCERNING THE LICENSED MATERIAL, WHETHER EXPRESS, IMPLIED, STATUTORY, OR OTHER. THIS INCLUDES, WITHOUT LIMITATION, WARRANTIES OF TITLE, MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NON-INFRINGEMENT, ABSENCE OF LATENT OR OTHER DEFECTS, ACCURACY, OR THE PRESENCE OR ABSENCE OF ERRORS, WHETHER OR NOT KNOWN OR DISCOVERABLE. WHERE DISCLAIMERS OF WARRANTIES ARE NOT ALLOWED IN FULL OR IN PART, THIS DISCLAIMER MAY NOT APPLY TO YOU. + +TO THE EXTENT POSSIBLE, IN NO EVENT WILL THE LICENSOR BE LIABLE TO YOU ON ANY LEGAL THEORY (INCLUDING, WITHOUT LIMITATION, NEGLIGENCE) OR OTHERWISE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, CONSEQUENTIAL, PUNITIVE, EXEMPLARY, OR OTHER LOSSES, COSTS, EXPENSES, OR DAMAGES ARISING OUT OF THIS PUBLIC LICENSE OR USE OF THE LICENSED MATERIAL, EVEN IF THE LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH LOSSES, COSTS, EXPENSES, OR DAMAGES. WHERE A LIMITATION OF LIABILITY IS NOT ALLOWED IN FULL OR IN PART, THIS LIMITATION MAY NOT APPLY TO YOU. + +The disclaimer of warranties and limitation of liability provided above shall be interpreted in a manner that, to the extent possible, most closely approximates an absolute disclaimer and waiver of all liability. + +@bye diff --git a/docs/src/install/t500_external.texi b/docs/src/install/t500_external.texi new file mode 100644 index 0000000..bbb0871 --- /dev/null +++ b/docs/src/install/t500_external.texi @@ -0,0 +1,296 @@ +\input texinfo +@documentencoding UTF-8 + +@ifnottex +@paragraphindent 0 +@end ifnottex +@titlepage +@title ThinkPad T500: flashing tutorial (BeagleBone Black) +@end titlepage + +@node Top +@top ThinkPad T500: flashing tutorial (BeagleBone Black) + +@menu +* Flashing the T500 with a BeagleBone Black:: +* Libreboot T400:: +* LCD compatibly:: +* A note about CPUs:: +* A note about GPUs:: +* CPU paste required:: +* Flash chip size:: +* MAC address:: +* Initial BBB configuration:: +* Thermal paste IMPORTANT:: +* Wifi:: +* WWAN:: +* Memory:: +@end menu + +@node Flashing the T500 with a BeagleBone Black +@chapter Flashing the T500 with a BeagleBone Black +@anchor{#flashing-the-t500-with-a-beaglebone-black} +Initial flashing instructions for T500. + +This guide is for those who want libreboot on their ThinkPad T500 while they still have the original Lenovo BIOS present. This guide can also be followed (adapted) if you brick your T500, to know how to recover. + +@uref{index.html,Back to main index} + +@node Libreboot T400 +@chapter Libreboot T400 +@anchor{#libreboot-t400} +You may also be interested in the smaller, more portable @uref{t400_external.html,Libreboot T400}. +@menu +* Serial port:: +@end menu + +@node Serial port +@section Serial port +@anchor{#serial-port} +EHCI debug might not be needed. It has been reported that the docking station for this laptop has a serial port, so it might be possible to use that instead. + +@node LCD compatibly +@chapter LCD compatibly +@anchor{#lcd-compatibly} +Not all LCD panels are compatible yet. See @uref{../hcl/gm45_lcd.html,../hcl/gm45_lcd.html}. + +@node A note about CPUs +@chapter A note about CPUs +@anchor{#a-note-about-cpus} +@uref{http://www.thinkwiki.org/wiki/Category:T500,ThinkWiki} has a list of CPUs for this system. The Core 2 Duo P8400, P8600 and P8700 are believed to work in libreboot. The T9600 was also tested on the T400 and confirmed working, so the T9400/T9500/T9550 probably also work, but they are untested. +@menu +* Quad-core CPUs:: +@end menu + +@node Quad-core CPUs +@section Quad-core CPUs +@anchor{#quad-core-cpus} +Although blocked by lenovobios (as was reported), it is reported that there are quad-core CPUs for GM45. This laptop has socketed CPUs, so it might be possible to use them (they are untested in coreboot; support may have to be added). Core 2 Quad Q9000, Q9100 or QX9300. + +Look at this link:@* @uref{https://en.wikipedia.org/wiki/List_of_Intel_Core_2_microprocessors#Quad-Core_Notebook_processors,https://en.wikipedia.org/wiki/List_of_Intel_Core_2_microprocessors#Quad-Core_Notebook_processors} + +@node A note about GPUs +@chapter A note about GPUs +@anchor{#a-note-about-gpus} +Some models have an Intel GPU, while others have both an ATI and an Intel GPU; this is referred to as "switchable graphics". In the @emph{BIOS setup} program for lenovobios, you can specify that the system will use one or the other (but not both). + +Libreboot is known to work on systems with only the Intel GPU, using native graphics initialization. On systems with switchable graphics, the Intel GPU is used and the ATI GPU is disabled, so native graphics initialization works all the same. + +@node CPU paste required +@chapter CPU paste required +@anchor{#cpu-paste-required} +See @ref{#paste,#paste}. + +@node Flash chip size +@chapter Flash chip size +@anchor{#flash-chip-size} +Use this to find out:@* # @strong{dmidecode | grep ROM\ Size} + +@ref{#pagetop,Back to top of page.} + +@node MAC address +@chapter MAC address +@anchor{#mac-address} +On the T500, the MAC address for the onboard gigabit ethernet chipset is stored inside the flash chip, along with other configuration data. + +Keep a note of the MAC address before disassembly; this is very important, because you will need to insert this into the libreboot ROM image before flashing it. It will be written in one of these locations: + +@image{../resources/images/t400/macaddress0,,,,jpg} @image{../resources/images/t400/macaddress1,,,,jpg} @image{../resources/images/x200/disassembly/0001,,,,jpg} + +@node Initial BBB configuration +@chapter Initial BBB configuration +@anchor{#initial-bbb-configuration} +Refer to @uref{bbb_setup.html,bbb_setup.html} for how to configure the BBB for flashing. + +The following shows how to connect clip to the BBB (on the P9 header), for SOIC-16 (clip: Pomona 5252): + +@verbatim +POMONA 5252 (correlate with the BBB guide) +=== ethernet jack and VGA port ==== + NC - - 21 + 1 - - 17 + NC - - NC + NC - - NC + NC - - NC + NC - - NC + 18 - - 3.3V (PSU) + 22 - - NC - this is pin 1 on the flash chip +=== SATA port === +This is how you will connect. Numbers refer to pin numbers on the BBB, on the plugs near the DC jack. +@end verbatim + +The following shows how to connect clip to the BBB (on the P9 header), for SOIC-8 (clip: Pomona 5250): + +@verbatim +POMONA 5250 (correlate with the BBB guide) +=== RAM slots ==== + 18 - - 1 + 22 - - NC + NC - - 21 + 3.3V (PSU) - - 17 - this is pin 1 on the flash chip +=== slot where the AC jack is connected === +This is how you will connect. Numbers refer to pin numbers on the BBB, on the plugs near the DC jack. +@end verbatim + +@menu +* The procedure:: +@end menu + +@node The procedure +@section The procedure +@anchor{#the-procedure} +Remove all screws:@* @image{../resources/images/t500/0000,,,,jpg}@* It is also advisable to, throughout the disassembly, place any screws and/or components that you removed in the same layout or arrangement. The follow photos demonstrate this:@* @image{../resources/images/t500/0001,,,,jpg} @image{../resources/images/t500/0002,,,,jpg} + +Remove the HDD/SSD and optical drive:@* @image{../resources/images/t500/0003,,,,jpg} @image{../resources/images/t500/0004,,,,jpg} + +Remove the palm rest:@* @image{../resources/images/t500/0005,,,,jpg} @image{../resources/images/t500/0006,,,,jpg} + +Remove the keyboard and rear bezel:@* @image{../resources/images/t500/0007,,,,jpg} @image{../resources/images/t500/0008,,,,jpg} @image{../resources/images/t500/0009,,,,jpg} @image{../resources/images/t500/0010,,,,jpg} @image{../resources/images/t500/0011,,,,jpg} @image{../resources/images/t500/0012,,,,jpg} + +If you have a WWAN/3G card and/or sim card reader, remove them permanently. The WWAN-3G card has proprietary firmware inside; the technology is identical to what is used in mobile phones, so it can also track your movements:@* @image{../resources/images/t500/0013,,,,jpg} @image{../resources/images/t500/0017,,,,jpg} @image{../resources/images/t500/0018,,,,jpg} + +Remove this frame, and then remove the wifi chip:@* @image{../resources/images/t500/0014,,,,jpg} @image{../resources/images/t500/0015,,,,jpg} @image{../resources/images/t500/0016,,,,jpg} + +Remove the speakers:@* @image{../resources/images/t500/0019,,,,jpg} @image{../resources/images/t500/0020,,,,jpg} @image{../resources/images/t500/0021,,,,jpg} @image{../resources/images/t500/0022,,,,jpg} @image{../resources/images/t500/0023,,,,jpg} @image{../resources/images/t500/0024,,,,jpg} @image{../resources/images/t500/0025,,,,jpg} + +Remove the NVRAM battery (already removed in this photo):@* @image{../resources/images/t500/0026,,,,jpg} + +When you re-assemble, you will be replacing the wifi chip with another. These two screws don't hold anything together, but they are included in your system because the screw holes for half-height cards are a different size, so use these if you will be installing a half-height card:@* @image{../resources/images/t500/0027,,,,jpg} + +Unroute the antenna wires:@* @image{../resources/images/t500/0028,,,,jpg} @image{../resources/images/t500/0029,,,,jpg} @image{../resources/images/t500/0030,,,,jpg} @image{../resources/images/t500/0031,,,,jpg} + +Disconnect the LCD cable from the motherboard:@* @image{../resources/images/t500/0032,,,,jpg} @image{../resources/images/t500/0033,,,,jpg} + +Remove the LCD assembly hinge screws, and then remove the LCD assembly:@* @image{../resources/images/t500/0034,,,,jpg} @image{../resources/images/t500/0035,,,,jpg} @image{../resources/images/t500/0036,,,,jpg} + +Remove the fan and heatsink:@* @image{../resources/images/t500/0037,,,,jpg} @image{../resources/images/t500/0038,,,,jpg} @image{../resources/images/t500/0039,,,,jpg} + +Remove this screw:@* @image{../resources/images/t500/0040,,,,jpg} + +Remove these cables, keeping note of how and in what arrangement they are connected:@* @image{../resources/images/t500/0041,,,,jpg} @image{../resources/images/t500/0042,,,,jpg} @image{../resources/images/t500/0043,,,,jpg} @image{../resources/images/t500/0044,,,,jpg} @image{../resources/images/t500/0045,,,,jpg} @image{../resources/images/t500/0046,,,,jpg} @image{../resources/images/t500/0047,,,,jpg} @image{../resources/images/t500/0048,,,,jpg} @image{../resources/images/t500/0049,,,,jpg} + +Disconnect the power jack:@* @image{../resources/images/t500/0050,,,,jpg} @image{../resources/images/t500/0051,,,,jpg} + +Remove the motherboard and cage from the base (the marked hole is where those cables were routed through):@* @image{../resources/images/t500/0052,,,,jpg} @image{../resources/images/t500/0053,,,,jpg} + +Remove all screws, arranging them in the same layout when placing the screws on a surface and marking each screw hole (this is to reduce the possibility of putting them back in the wrong holes):@* @image{../resources/images/t500/0054,,,,jpg} @image{../resources/images/t500/0055,,,,jpg} + +Also remove this:@* @image{../resources/images/t500/0056,,,,jpg} @image{../resources/images/t500/0057,,,,jpg} + +Separate the motherboard from the cage:@* @image{../resources/images/t500/0058,,,,jpg} @image{../resources/images/t500/0059,,,,jpg} + +The flash chip is next to the memory slots. On this system, it was a SOIC-8 (4MiB or 32Mb) flash chip:@* @image{../resources/images/t500/0060,,,,jpg} + +Connect your programmer, then connect GND and 3.3V@* @image{../resources/images/t500/0061,,,,jpg}@* @image{../resources/images/t400/0067,,,,jpg} @image{../resources/images/t400/0069,,,,jpg} @image{../resources/images/t400/0070,,,,jpg} @image{../resources/images/t400/0071,,,,jpg} + +A dedicated 3.3V PSU was used to create this guide, but at ATX PSU is also fine:@* @image{../resources/images/t400/0072,,,,jpg} + +Of course, make sure to turn on your PSU:@* @image{../resources/images/x200/disassembly/0013,,,,jpg} + +Now, you should be ready to install libreboot. + +Flashrom binaries for ARM (tested on a BBB) are distributed in libreboot_util. Alternatively, libreboot also distributes flashrom source code which can be built. + +Log in as root on your BBB, using the instructions in @uref{bbb_setup.html#bbb_access,bbb_setup.html#bbb_access}. + +Test that flashrom works:@* # @strong{./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512}@* In this case, the output was: + +@verbatim +flashrom v0.9.7-r1854 on Linux 3.8.13-bone47 (armv7l) +flashrom is free software, get the source code at http://www.flashrom.org +Calibrating delay loop... OK. +Found Macronix flash chip "MX25L6405(D)" (8192 kB, SPI) on linux_spi. +Found Macronix flash chip "MX25L6406E/MX25L6436E" (8192 kB, SPI) on linux_spi. +Found Macronix flash chip "MX25L6445E/MX25L6473E" (8192 kB, SPI) on linux_spi. +Multiple flash chip definitions match the detected chip(s): "MX25L6405(D)", "MX25L6406E/MX25L6436E", "MX25L6445E/MX25L6473E" +Please specify which chip definition to use with the -c <chipname> option. +@end verbatim + +How to backup factory.rom (change the -c option as neeed, for your flash chip):@* # @strong{./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -r factory.rom}@* # @strong{./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -r factory1.rom}@* # @strong{./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -r factory2.rom}@* Note: the @strong{-c} option is not required in libreboot's patched flashrom, because the redundant flash chip definitions in @emph{flashchips.c} have been removed.@* Now compare the 3 images:@* # @strong{sha512sum factory*.rom}@* If the hashes match, then just copy one of them (the factory.rom) to a safe place (on a drive connected to another system, not the BBB). This is useful for reverse engineering work, if there is a desirable behaviour in the original firmware that could be replicated in coreboot and libreboot. + +Follow the instructions at @uref{../hcl/gm45_remove_me.html#ich9gen,../hcl/gm45_remove_me.html#ich9gen} to change the MAC address inside the libreboot ROM image, before flashing it. Although there is a default MAC address inside the ROM image, this is not what you want. @strong{Make sure to always change the MAC address to one that is correct for your system.} + +Now flash it:@* # @strong{./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -w path/to/libreboot/rom/image.rom -V} + +@image{../resources/images/x200/disassembly/0015,,,,jpg} + +You might see errors, but if it says @strong{Verifying flash... VERIFIED} at the end, then it's flashed and should boot. If you see errors, try again (and again, and again); the message @strong{Chip content is identical to the requested image} is also an indication of a successful installation. + +Example output from running the command (see above): + +@verbatim +flashrom v0.9.7-r1854 on Linux 3.8.13-bone47 (armv7l) +flashrom is free software, get the source code at http://www.flashrom.org +Calibrating delay loop... OK. +Found Macronix flash chip "MX25L6405(D)" (8192 kB, SPI) on linux_spi. +Reading old flash chip contents... done. +Erasing and writing flash chip... FAILED at 0x00001000! Expected=0xff, Found=0x00, failed byte count from 0x00000000-0x0000ffff: 0xd716 +ERASE FAILED! +Reading current flash chip contents... done. Looking for another erase function. +Erase/write done. +Verifying flash... VERIFIED. +@end verbatim + +@ref{#pagetop,Back to top of page.} + +@node Thermal paste IMPORTANT +@chapter Thermal paste (IMPORTANT) +@anchor{#thermal-paste-important} +Because part of this procedure involved removing the heatsink, you will need to apply new paste. Arctic MX-4 is ok. You will also need isopropyl alcohol and an anti-static cloth to clean with. + +When re-installing the heatsink, you must first clean off all old paste with the alcohol/cloth. Then apply new paste. Arctic MX-4 is also much better than the default paste used on these systems. + +@image{../resources/images/t400/paste,,,,jpg} + +NOTE: the photo above is for illustration purposes only, and does not show how to properly apply the thermal paste. Other guides online detail the proper application procedure. + +@node Wifi +@chapter Wifi +@anchor{#wifi} +The T500 typically comes with an Intel wifi chipset, which does not work without proprietary software. For a list of wifi chipsets that work without proprietary software, see @uref{../hcl/index.html#recommended_wifi,../hcl/index.html#recommended_wifi}. + +Some T500 laptops might come with an Atheros chipset, but this is 802.11g only. + +It is recommended that you install a new wifi chipset. This can only be done after installing libreboot, because the original firmware has a whitelist of approved chips, and it will refuse to boot if you use an 'unauthorized' wifi card. + +The following photos show an Atheros AR5B95 being installed, to replace the Intel chip that this T500 came with:@* @image{../resources/images/t400/0012,,,,jpg} @image{../resources/images/t400/ar5b95,,,,jpg} + +@node WWAN +@chapter WWAN +@anchor{#wwan} +If you have a WWAN/3G card and/or sim card reader, remove them permanently. The WWAN-3G card has DMA, and proprietary firmware inside; the technology is identical to what is used in mobile phones, so it can also track your movements. + +Not to be confused with wifi (wifi is fine). + +@node Memory +@chapter Memory +@anchor{#memory} +You need DDR3 SODIMM PC3-8500 RAM installed, in matching pairs (speed/size). Non-matching pairs won't work. You can also install a single module (meaning, one of the slots will be empty) in slot 0. + +Make sure that the RAM you buy is the 2Rx8 density. + +The following photo shows 8GiB (2x4GiB) of RAM installed:@* @image{../resources/images/t400/memory,,,,jpg} +@menu +* Boot it!:: +@end menu + +@node Boot it! +@section Boot it! +@anchor{#boot-it} +You should see something like this: + +@image{../resources/images/t500/0062,,,,jpg} + +Now @uref{../gnulinux/index.html,install GNU/Linux}. + +Copyright © 2015 Francis Rowe <info@@gluglug.org.uk>@* Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license can be found at @uref{../resources/licenses/gfdl-1.3.txt,gfdl-1.3.txt} + +Updated versions of the license (when available) can be found at @uref{https://www.gnu.org/licenses/licenses.html,https://www.gnu.org/licenses/licenses.html} + +UNLESS OTHERWISE SEPARATELY UNDERTAKEN BY THE LICENSOR, TO THE EXTENT POSSIBLE, THE LICENSOR OFFERS THE LICENSED MATERIAL AS-IS AND AS-AVAILABLE, AND MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND CONCERNING THE LICENSED MATERIAL, WHETHER EXPRESS, IMPLIED, STATUTORY, OR OTHER. THIS INCLUDES, WITHOUT LIMITATION, WARRANTIES OF TITLE, MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NON-INFRINGEMENT, ABSENCE OF LATENT OR OTHER DEFECTS, ACCURACY, OR THE PRESENCE OR ABSENCE OF ERRORS, WHETHER OR NOT KNOWN OR DISCOVERABLE. WHERE DISCLAIMERS OF WARRANTIES ARE NOT ALLOWED IN FULL OR IN PART, THIS DISCLAIMER MAY NOT APPLY TO YOU. + +TO THE EXTENT POSSIBLE, IN NO EVENT WILL THE LICENSOR BE LIABLE TO YOU ON ANY LEGAL THEORY (INCLUDING, WITHOUT LIMITATION, NEGLIGENCE) OR OTHERWISE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, CONSEQUENTIAL, PUNITIVE, EXEMPLARY, OR OTHER LOSSES, COSTS, EXPENSES, OR DAMAGES ARISING OUT OF THIS PUBLIC LICENSE OR USE OF THE LICENSED MATERIAL, EVEN IF THE LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH LOSSES, COSTS, EXPENSES, OR DAMAGES. WHERE A LIMITATION OF LIABILITY IS NOT ALLOWED IN FULL OR IN PART, THIS LIMITATION MAY NOT APPLY TO YOU. + +The disclaimer of warranties and limitation of liability provided above shall be interpreted in a manner that, to the extent possible, most closely approximates an absolute disclaimer and waiver of all liability. + +@bye diff --git a/docs/src/install/t60_unbrick.texi b/docs/src/install/t60_unbrick.texi new file mode 100644 index 0000000..7c94b40 --- /dev/null +++ b/docs/src/install/t60_unbrick.texi @@ -0,0 +1,152 @@ +\input texinfo +@documentencoding UTF-8 + +@ifnottex +@paragraphindent 0 +@end ifnottex +@titlepage +@title ThinkPad T60: Recovery guide +@end titlepage + +@node Top +@top ThinkPad T60: Recovery guide + +@menu +* ThinkPad T60 Recovery guide:: +* Brick type 1 bucts not reset:: +* bad rom or user error system won't boot:: +@end menu + +@node ThinkPad T60 Recovery guide +@chapter ThinkPad T60: Recovery guide +@anchor{#thinkpad-t60-recovery-guide} +This section documents how to recover from a bad flash that prevents your ThinkPad T60 from booting. + +@uref{index.html,Back to previous index} +@menu +* Table of Contents:: +@end menu + +@node Table of Contents +@section Table of Contents +@anchor{#table-of-contents} +@itemize +@item +Types of brick: +@itemize +@item +@ref{#bucts_brick,Brick type 1: bucts not reset} +@item +@ref{#recovery,Brick type 2: bad rom (or user error), system won't boot} +@end itemize + +@end itemize + +@node Brick type 1 bucts not reset +@chapter Brick type 1: bucts not reset. +@anchor{#brick-type-1-bucts-not-reset.} +You still have Lenovo BIOS, or you had libreboot running and you flashed another ROM; and you had bucts 1 set and the ROM wasn't dd'd.* or if Lenovo BIOS was present and libreboot wasn't flashed.@*@* In this case, unbricking is easy: reset BUC.TS to 0 by removing that yellow cmos coin (it's a battery) and putting it back after a minute or two:@* @image{../resources/images/t60_dev/0006,,,,JPG}@*@* *Those dd commands should be applied to all newly compiled T60 ROM images (the ROM images in libreboot binary archives already have this applied!):@* dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k@* dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump@* dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k conv=notrunc@* (doing this makes the ROM suitable for use when flashing a system that still has Lenovo BIOS running, using those instructions: @uref{http://www.coreboot.org/Board:lenovo/x60/Installation,http://www.coreboot.org/Board:lenovo/x60/Installation}. (it says x60, but instructions for t60 are identical) + +@node bad rom or user error system won't boot +@chapter bad rom (or user error), system won't boot +@anchor{#bad-rom-or-user-error-system-wont-boot} +In this scenario, you compiled a ROM that had an incorrect configuration, or there is an actual bug preventing your system from booting. Or, maybe, you set BUC.TS to 0 and shut down after first flash while Lenovo BIOS was running. In any case, your system is bricked and will not boot at all. + +"Unbricking" means flashing a known-good (working) ROM. The problem: you can't boot the system, making this difficult. In this situation, external hardware (see hardware requirements above) is needed which can flash the SPI chip (where libreboot resides). + +Remove those screws and remove the HDD:@* @image{../resources/images/t60_dev/0001,,,,JPG} @image{../resources/images/t60_dev/0002,,,,JPG} + +Lift off the palm rest:@* @image{../resources/images/t60_dev/0003,,,,JPG} + +Lift up the keyboard, pull it back a bit, flip it over like that and then disconnect it from the board:@* @image{../resources/images/t60_dev/0004,,,,JPG} @image{../resources/images/t60_dev/0005,,,,JPG} @image{../resources/images/t60_dev/0006,,,,JPG} + +Gently wedge both sides loose:@* @image{../resources/images/t60_dev/0007,,,,JPG} @image{../resources/images/t60_dev/0008,,,,JPG} + +Remove that cable from the position:@* @image{../resources/images/t60_dev/0009,,,,JPG} @image{../resources/images/t60_dev/0010,,,,JPG} + +Now remove that bezel. Remove wifi, nvram battery and speaker connector (also remove 56k modem, on the left of wifi):@* @image{../resources/images/t60_dev/0011,,,,JPG} + +Remove those screws:@* @image{../resources/images/t60_dev/0012,,,,JPG} + +Disconnect the power jack:@* @image{../resources/images/t60_dev/0013,,,,JPG} + +Remove nvram battery:@* @image{../resources/images/t60_dev/0014,,,,JPG} + +Disconnect cable (for 56k modem) and disconnect the other cable:@* @image{../resources/images/t60_dev/0015,,,,JPG} @image{../resources/images/t60_dev/0016,,,,JPG} + +Disconnect speaker cable:@* @image{../resources/images/t60_dev/0017,,,,JPG} + +Disconnect the other end of the 56k modem cable:@* @image{../resources/images/t60_dev/0018,,,,JPG} + +Make sure you removed it:@* @image{../resources/images/t60_dev/0019,,,,JPG} + +Unscrew those:@* @image{../resources/images/t60_dev/0020,,,,JPG} + +Make sure you removed those:@* @image{../resources/images/t60_dev/0021,,,,JPG} + +Disconnect LCD cable from board:@* @image{../resources/images/t60_dev/0022,,,,JPG} + +Remove those screws then remove the LCD assembly:@* @image{../resources/images/t60_dev/0023,,,,JPG} @image{../resources/images/t60_dev/0024,,,,JPG} @image{../resources/images/t60_dev/0025,,,,JPG} + +Once again, make sure you removed those:@* @image{../resources/images/t60_dev/0026,,,,JPG} + +Remove the shielding containing the motherboard, then flip it over. Remove these screws, placing them on a steady surface in the same layout as they were in before you removed them. Also, you should mark each screw hole after removing the screw (a permanent marker pen will do), this is so that you have a point of reference when re-assembling the system:@* @image{../resources/images/t60_dev/0027,,,,JPG} @image{../resources/images/t60_dev/0028,,,,JPG} @image{../resources/images/t60_dev/0029,,,,JPG} @image{../resources/images/t60_dev/0031,,,,JPG} @image{../resources/images/t60_dev/0032,,,,JPG} @image{../resources/images/t60_dev/0033,,,,JPG} + +Now wire up the BBB and the Pomona with your PSU.@* Refer to @uref{bbb_setup.html,bbb_setup.html} for how to setup the BBB for flashing.@* @strong{Note, the guide mentions a 3.3v DC PSU but you don't need this on the T60: if you don't have or don't want to use an external PSU, then make sure not to connect the 3.3v leads mentioned in the guide; instead, connect the AC adapter (the one that normally charges your battery) so that the board has power (but don't boot it up)}@* @image{../resources/images/t60_dev/0030,,,,JPG}@* Correlate the following with the BBB guide linked above: + +@verbatim +POMONA 5250: +=== DVD drive ==== + 18 - - 1 + 22 - - NC ---- RAM is on this end + NC - - 21 + 3.3V (PSU) - - 17 - this is pin 1 on the flash chip +=== audio jacks === +This is how you will connect. Numbers refer to pin numbers on the BBB, on the plugs near the DC jack. +@end verbatim + +Connect the pomona from the BBB to the flash chip. No pics unfortunately. (use the text diagram above). + +Flashrom binaries for ARM (tested on a BBB) are distributed in libreboot_util. Alternatively, libreboot also distributes flashrom source code which can be built. + +SSH'd into the BBB:@* # @strong{./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -w yourrom.rom} + +It should be @strong{Verifying flash... VERIFIED} at the end. If flashrom complains about multiple flash chip definitions detected, then choose one of them following the instructions in the output. + +Put those screws back:@* @image{../resources/images/t60_dev/0047,,,,JPG} + +Put it back into lower chassis:@* @image{../resources/images/t60_dev/0048,,,,JPG} + +Attach LCD and insert screws (also, attach the lcd cable to the board):@* @image{../resources/images/t60_dev/0049,,,,JPG} + +Insert those screws:@* @image{../resources/images/t60_dev/0050,,,,JPG} + +On the CPU (and there is another chip south-east to it, sorry forgot to take pic) clean off the old thermal paste (with the alcohol) and apply new (Artic Silver 5 is good, others are good too) you should also clean the heatsink the same way@* @image{../resources/images/t60_dev/0051,,,,JPG} + +Attach the heatsink and install the screws (also, make sure to install the AC jack as highlighted):@* @image{../resources/images/t60_dev/0052,,,,JPG} + +Reinstall that upper bezel:@* @image{../resources/images/t60_dev/0053,,,,JPG} + +Do that:@* @image{../resources/images/t60_dev/0054,,,,JPG} @image{../resources/images/t60_dev/0055,,,,JPG} + +Re-attach modem, wifi, (wwan?), and all necessary cables. Sorry, forgot to take pics. Look at previous removal steps to see where they go back to. + +Attach keyboard and install nvram battery:@* @image{../resources/images/t60_dev/0056,,,,JPG} @image{../resources/images/t60_dev/0057,,,,JPG} + +Place keyboard and (sorry, forgot to take pics) reinstall the palmrest and insert screws on the underside:@* @image{../resources/images/t60_dev/0058,,,,JPG} + +It lives!@* @image{../resources/images/t60_dev/0071,,,,JPG} @image{../resources/images/t60_dev/0072,,,,JPG} @image{../resources/images/t60_dev/0073,,,,JPG} + +Always stress test ('stress -c 2' and xsensors. below 90C is ok) when replacing cpu paste/heatsink:@* @image{../resources/images/t60_dev/0074,,,,JPG} + +Copyright © 2014, 2015 Francis Rowe <info@@gluglug.org.uk>@* Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license can be found at @uref{../resources/licenses/gfdl-1.3.txt,gfdl-1.3.txt} + +Updated versions of the license (when available) can be found at @uref{https://www.gnu.org/licenses/licenses.html,https://www.gnu.org/licenses/licenses.html} + +UNLESS OTHERWISE SEPARATELY UNDERTAKEN BY THE LICENSOR, TO THE EXTENT POSSIBLE, THE LICENSOR OFFERS THE LICENSED MATERIAL AS-IS AND AS-AVAILABLE, AND MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND CONCERNING THE LICENSED MATERIAL, WHETHER EXPRESS, IMPLIED, STATUTORY, OR OTHER. THIS INCLUDES, WITHOUT LIMITATION, WARRANTIES OF TITLE, MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NON-INFRINGEMENT, ABSENCE OF LATENT OR OTHER DEFECTS, ACCURACY, OR THE PRESENCE OR ABSENCE OF ERRORS, WHETHER OR NOT KNOWN OR DISCOVERABLE. WHERE DISCLAIMERS OF WARRANTIES ARE NOT ALLOWED IN FULL OR IN PART, THIS DISCLAIMER MAY NOT APPLY TO YOU. + +TO THE EXTENT POSSIBLE, IN NO EVENT WILL THE LICENSOR BE LIABLE TO YOU ON ANY LEGAL THEORY (INCLUDING, WITHOUT LIMITATION, NEGLIGENCE) OR OTHERWISE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, CONSEQUENTIAL, PUNITIVE, EXEMPLARY, OR OTHER LOSSES, COSTS, EXPENSES, OR DAMAGES ARISING OUT OF THIS PUBLIC LICENSE OR USE OF THE LICENSED MATERIAL, EVEN IF THE LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH LOSSES, COSTS, EXPENSES, OR DAMAGES. WHERE A LIMITATION OF LIABILITY IS NOT ALLOWED IN FULL OR IN PART, THIS LIMITATION MAY NOT APPLY TO YOU. + +The disclaimer of warranties and limitation of liability provided above shall be interpreted in a manner that, to the extent possible, most closely approximates an absolute disclaimer and waiver of all liability. + +@bye diff --git a/docs/src/install/x200_external.texi b/docs/src/install/x200_external.texi new file mode 100644 index 0000000..f148c6c --- /dev/null +++ b/docs/src/install/x200_external.texi @@ -0,0 +1,277 @@ +\input texinfo +@documentencoding UTF-8 + +@ifnottex +@paragraphindent 0 +@end ifnottex +@titlepage +@title ThinkPad X200: flashing tutorial (BeagleBone Black) +@end titlepage + +@node Top +@top ThinkPad X200: flashing tutorial (BeagleBone Black) + +@menu +* Flashing the X200 with a BeagleBone Black:: +* X200 laptops with libreboot pre-installed:: +* Flash chip size:: +* MAC address:: +* Initial BBB configuration:: +* Wifi:: +* WWAN:: +* Memory:: +@end menu + +@node Flashing the X200 with a BeagleBone Black +@chapter Flashing the X200 with a BeagleBone Black +@anchor{#flashing-the-x200-with-a-beaglebone-black} +Initial flashing instructions for X200. + +This guide is for those who want libreboot on their ThinkPad X200 while they still have the original Lenovo BIOS present. This guide can also be followed (adapted) if you brick your X200, to know how to recover. + +@itemize +@item +@ref{#preinstall,X200 laptops with libreboot pre-installed} +@item +@ref{#flashchips,Flash chips} +@item +@ref{#macaddress,MAC address} +@item +@ref{#clip,Initial BBB configuration and installation procedure} +@item +@ref{#boot,Boot it!} +@item +@ref{#wifi,Wifi} +@item +@ref{#wwan,wwan} +@item +@ref{#memory,Memory} +@item +@ref{#gpio33,X200S and X200 Tablet users: GPIO33 trick will not work.} +@end itemize + +@uref{index.html,Back to main index} + +@node X200 laptops with libreboot pre-installed +@chapter X200 laptops with libreboot pre-installed +@anchor{#x200-laptops-with-libreboot-pre-installed} +If you don't want to install libreboot yourself, companies exist that sell these laptops with libreboot pre-installed, along with a free GNU/Linux distribution. + +Check the @uref{../../suppliers,suppliers} page for more information. + +@node Flash chip size +@chapter Flash chip size +@anchor{#flash-chip-size} +Use this to find out:@* # @strong{dmidecode | grep ROM\ Size} + +The X200S and X200 Tablet will use a WSON-8 flash chip, on the bottom of the motherboard (this requires removal of the motherboard). @strong{Not all X200S/X200T are supported; see @uref{../hcl/x200.html#x200s,../hcl/x200.html#x200s}.} + +@ref{#pagetop,Back to top of page.} + +@node MAC address +@chapter MAC address +@anchor{#mac-address} +On the X200/X200S/X200T, the MAC address for the onboard gigabit ethernet chipset is stored inside the flash chip, along with other configuration data. + +Keep a note of the MAC address before disassembly; this is very important, because you will need to insert this into the libreboot ROM image before flashing it. It will be written in one of these locations: + +@image{../resources/images/x200/disassembly/0002,,,,jpg} @image{../resources/images/x200/disassembly/0001,,,,jpg} + +@node Initial BBB configuration +@chapter Initial BBB configuration +@anchor{#initial-bbb-configuration} +Refer to @uref{bbb_setup.html,bbb_setup.html} for how to set up the BBB for flashing. + +The following shows how to connect the clip to the BBB (on the P9 header), for SOIC-16 (clip: Pomona 5252): + +@verbatim +POMONA 5252 (correlate with the BBB guide) +=== front (display) on your X200 ==== + NC - - 21 + 1 - - 17 + NC - - NC + NC - - NC + NC - - NC + NC - - NC + 18 - - 3.3V (PSU) + 22 - - NC - this is pin 1 on the flash chip +=== back (palmrest) on your X200 === +This is how you will connect. Numbers refer to pin numbers on the BBB, on the plugs near the DC jack. +Here is a photo of the SOIC-16 flash chip. Pins are labelled: + +@end verbatim + +The following shows how to connect the clip to the BBB (on the P9 header), for SOIC-8 (clip: Pomona 5250): + +@verbatim +POMONA 5250 (correlate with the BBB guide) +=== left side of the X200 (where the VGA port is) ==== + 18 - - 1 + 22 - - NC + NC - - 21 + 3.3V (PSU) - - 17 - this is pin 1 on the flash chip. in front of it is the screen. +=== right side of the X200 (where the audio jacks are) === +This is how you will connect. Numbers refer to pin numbers on the BBB, on the plugs near the DC jack. +Here is a photo of the SOIC-8 flash chip. The pins are labelled: + + +Look at the pads in that photo, on the left and right. Those are for SOIC-16. Would it be possible to remove the SOIC-8 and solder a SOIC-16 +chip on those pins? +@end verbatim + +@strong{On the X200S and X200 Tablet the flash chip is underneath the board, in a WSON package. The pinout is very much the same as a SOIC-8, except you need to solder (there are no clips available).@* The following image shows how this is done:}@* @image{../resources/images/x200/wson_soldered,,,,jpg} @* In this image, a pin header was soldered onto the WSON. Another solution might be to de-solder the WSON-8 chip and put a SOIC-8 there instead. Check the list of SOIC-8 flash chips at @uref{../hcl/gm45_remove_me.html#flashchips,../hcl/gm45_remove_me.html#flashchips} but do note that these are only 4MiB (32Mb) chips. The only X200 SPI chips with 8MiB capacity are SOIC-16. For 8MiB capacity in this case, the X201 SOIC-8 flash chip (Macronix 25L6445E) might work. +@menu +* The procedure:: +@end menu + +@node The procedure +@section The procedure +@anchor{#the-procedure} +This section is for the X200. This does not apply to the X200S or X200 Tablet (for those systems, you have to remove the motherboard completely, since the flash chip is on the other side of the board). + +Remove these screws:@* @image{../resources/images/x200/disassembly/0003,,,,jpg} + +Push the keyboard forward, gently, then lift it off and disconnect it from the board:@* @image{../resources/images/x200/disassembly/0004,,,,jpg} @image{../resources/images/x200/disassembly/0005,,,,jpg} + +Pull the palm rest off, lifting from the left and right side at the back of the palm rest:@* @image{../resources/images/x200/disassembly/0006,,,,jpg} + +Lift back the tape that covers a part of the flash chip, and then connect the clip:@* @image{../resources/images/x200/disassembly/0007,,,,jpg} @image{../resources/images/x200/disassembly/0008,,,,jpg} + +On pin 2 of the BBB, where you have the ground (GND), connect the ground to your PSU:@* @image{../resources/images/x200/disassembly/0009,,,,jpg} @image{../resources/images/x200/disassembly/0010,,,,jpg} + +Connect the 3.3V supply from your PSU to the flash chip (via the clip):@* @image{../resources/images/x200/disassembly/0011,,,,jpg} @image{../resources/images/x200/disassembly/0012,,,,jpg} + +Of course, make sure that your PSU is also plugged in and turn on:@* @image{../resources/images/x200/disassembly/0013,,,,jpg} + +This tutorial tells you to use an ATX PSU, for the 3.3V DC supply. The PSU used when taking these photos is actually not an ATX PSU, but a PSU that is designed specifically for providing 3.3V DC (an ATX PSU will also work):@* @image{../resources/images/x200/disassembly/0014,,,,jpg} + +Now, you should be ready to install libreboot. + +Flashrom binaries for ARM (tested on a BBB) are distributed in libreboot_util. Alternatively, libreboot also distributes flashrom source code which can be built. + +Log in as root on your BBB, using the instructions in @uref{bbb_setup.html#bbb_access,bbb_setup.html#bbb_access}. + +Test that flashrom works:@* # @strong{./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512}@* In this case, the output was: + +@verbatim +flashrom v0.9.7-r1854 on Linux 3.8.13-bone47 (armv7l) +flashrom is free software, get the source code at http://www.flashrom.org +Calibrating delay loop... OK. +Found Macronix flash chip "MX25L6405(D)" (8192 kB, SPI) on linux_spi. +Found Macronix flash chip "MX25L6406E/MX25L6436E" (8192 kB, SPI) on linux_spi. +Found Macronix flash chip "MX25L6445E/MX25L6473E" (8192 kB, SPI) on linux_spi. +Multiple flash chip definitions match the detected chip(s): "MX25L6405(D)", "MX25L6406E/MX25L6436E", "MX25L6445E/MX25L6473E" +Please specify which chip definition to use with the -c <chipname> option. +@end verbatim + +How to backup factory.rom (change the -c option as neeed, for your flash chip):@* # @strong{./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -r factory.rom}@* # @strong{./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -r factory1.rom}@* # @strong{./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -r factory2.rom}@* Note: the @strong{-c} option is not required in libreboot's patched flashrom, because the redundant flash chip definitions in @emph{flashchips.c} have been removed.@* Now compare the 3 images:@* # @strong{sha512sum factory*.rom}@* If the hashes match, then just copy one of them (the factory.rom) to a safe place (on a drive connected to another system, not the BBB). This is useful for reverse engineering work, if there is a desirable behaviour in the original firmware that could be replicated in coreboot and libreboot. + +Follow the instructions at @uref{../hcl/gm45_remove_me.html#ich9gen,../hcl/gm45_remove_me.html#ich9gen} to change the MAC address inside the libreboot ROM image, before flashing it. Although there is a default MAC address inside the ROM image, this is not what you want. @strong{Make sure to always change the MAC address to one that is correct for your system.} + +Now flash it:@* # @strong{./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -w path/to/libreboot/rom/image.rom -V} + +@image{../resources/images/x200/disassembly/0015,,,,jpg} + +You might see errors, but if it says @strong{Verifying flash... VERIFIED} at the end, then it's flashed and should boot. If you see errors, try again (and again, and again); the message @strong{Chip content is identical to the requested image} is also an indication of a successful installation. + +Example output from running the command (see above): + +@verbatim +flashrom v0.9.7-r1854 on Linux 3.8.13-bone47 (armv7l) +flashrom is free software, get the source code at http://www.flashrom.org +Calibrating delay loop... OK. +Found Macronix flash chip "MX25L6405(D)" (8192 kB, SPI) on linux_spi. +Reading old flash chip contents... done. +Erasing and writing flash chip... FAILED at 0x00001000! Expected=0xff, Found=0x00, failed byte count from 0x00000000-0x0000ffff: 0xd716 +ERASE FAILED! +Reading current flash chip contents... done. Looking for another erase function. +Erase/write done. +Verifying flash... VERIFIED. +@end verbatim + +@ref{#pagetop,Back to top of page.} + +@node Wifi +@chapter Wifi +@anchor{#wifi} +The X200 typically comes with an Intel wifi chipset, which does not work without proprietary software. For a list of wifi chipsets that work without proprietary software, see @uref{../hcl/index.html#recommended_wifi,../hcl/index.html#recommended_wifi}. + +Some X200 laptops come with an Atheros chipset, but this is 802.11g only. + +It is recommended that you install a new wifi chipset. This can only be done after installing libreboot, because the original firmware has a whitelist of approved chips, and it will refuse to boot if you use an 'unauthorized' wifi card. + +The following photos show an Atheros AR5B95 being installed, to replace the Intel chip that this X200 came with:@* @image{../resources/images/x200/disassembly/0016,,,,jpg} @image{../resources/images/x200/disassembly/0017,,,,jpg} + +@node WWAN +@chapter WWAN +@anchor{#wwan} +If you have a WWAN/3G card and/or sim card reader, remove them permanently. The WWAN-3G card has proprietary firmware inside; the technology is identical to what is used in mobile phones, so it can also track your movements. + +Not to be confused with wifi (wifi is fine). + +@node Memory +@chapter Memory +@anchor{#memory} +You need DDR3 SODIMM PC3-8500 RAM installed, in matching pairs (speed/size). Non-matching pairs won't work. You can also install a single module (meaning, one of the slots will be empty) in slot 0. + +Make sure that the RAM you buy is the 2Rx8 density. + +In this photo, 8GiB of RAM (2x4GiB) is installed:@* @image{../resources/images/x200/disassembly/0018,,,,jpg} +@menu +* Boot it!:: +* X200S and X200 Tablet users GPIO33 trick will not work:: +@end menu + +@node Boot it! +@section Boot it! +@anchor{#boot-it} +You should see something like this: + +@image{../resources/images/x200/disassembly/0019,,,,jpg} + +Now @uref{../gnulinux/index.html,install GNU/Linux}. + +@node X200S and X200 Tablet users GPIO33 trick will not work +@section X200S and X200 Tablet users: GPIO33 trick will not work. +@anchor{#x200s-and-x200-tablet-users-gpio33-trick-will-not-work.} +sgsit found out about a pin called GPIO33, which can be grounded to disable the flashing protections by the descriptor and stop the ME from starting (which itself interferes with flashing attempts). The theory was proven correct; however, it is still useless in practise. + +Look just above the 7 in TP37 (that's GPIO33):@* @image{../hcl/../resources/images/x200/gpio33_location,,,,jpg} + +By default we would see this in lenovobios, when trying flashrom -p internal -w rom.rom: + +@verbatim +FREG0: Warning: Flash Descriptor region (0x00000000-0x00000fff) is read-only. +FREG2: Warning: Management Engine region (0x00001000-0x005f5fff) is locked. +@end verbatim + +With GPIO33 grounded during boot, this disabled the flash protections as set by descriptor, and stopped the ME from starting. The output changed to: + +@verbatim +The Flash Descriptor Override Strap-Pin is set. Restrictions implied by +the Master Section of the flash descriptor are NOT in effect. Please note +that Protected Range (PR) restrictions still apply. +@end verbatim + +The part in bold is what got us. This was still observed: + +@verbatim +PR0: Warning: 0x007e0000-0x01ffffff is read-only. +PR4: Warning: 0x005f8000-0x005fffff is locked. +@end verbatim + +It is actually possible to disable these protections. Lenovobios does, when updating the BIOS (proprietary one). One possible way to go about this would be to debug the BIOS update utility from Lenovo, to find out how it's disabling these protections. Some more research is available here: @uref{http://www.coreboot.org/Board:lenovo/x200/internal_flashing_research,http://www.coreboot.org/Board:lenovo/x200/internal_flashing_research} + +On a related note, libreboot has a utility that could help with investigating this: @uref{../hcl/gm45_remove_me.html#demefactory,../hcl/gm45_remove_me.html#demefactory} + +Copyright © 2014, 2015 Francis Rowe <info@@gluglug.org.uk>@* Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license can be found at @uref{../resources/licenses/gfdl-1.3.txt,gfdl-1.3.txt} + +Updated versions of the license (when available) can be found at @uref{https://www.gnu.org/licenses/licenses.html,https://www.gnu.org/licenses/licenses.html} + +UNLESS OTHERWISE SEPARATELY UNDERTAKEN BY THE LICENSOR, TO THE EXTENT POSSIBLE, THE LICENSOR OFFERS THE LICENSED MATERIAL AS-IS AND AS-AVAILABLE, AND MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND CONCERNING THE LICENSED MATERIAL, WHETHER EXPRESS, IMPLIED, STATUTORY, OR OTHER. THIS INCLUDES, WITHOUT LIMITATION, WARRANTIES OF TITLE, MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NON-INFRINGEMENT, ABSENCE OF LATENT OR OTHER DEFECTS, ACCURACY, OR THE PRESENCE OR ABSENCE OF ERRORS, WHETHER OR NOT KNOWN OR DISCOVERABLE. WHERE DISCLAIMERS OF WARRANTIES ARE NOT ALLOWED IN FULL OR IN PART, THIS DISCLAIMER MAY NOT APPLY TO YOU. + +TO THE EXTENT POSSIBLE, IN NO EVENT WILL THE LICENSOR BE LIABLE TO YOU ON ANY LEGAL THEORY (INCLUDING, WITHOUT LIMITATION, NEGLIGENCE) OR OTHERWISE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, CONSEQUENTIAL, PUNITIVE, EXEMPLARY, OR OTHER LOSSES, COSTS, EXPENSES, OR DAMAGES ARISING OUT OF THIS PUBLIC LICENSE OR USE OF THE LICENSED MATERIAL, EVEN IF THE LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH LOSSES, COSTS, EXPENSES, OR DAMAGES. WHERE A LIMITATION OF LIABILITY IS NOT ALLOWED IN FULL OR IN PART, THIS LIMITATION MAY NOT APPLY TO YOU. + +The disclaimer of warranties and limitation of liability provided above shall be interpreted in a manner that, to the extent possible, most closely approximates an absolute disclaimer and waiver of all liability. + +@bye diff --git a/docs/src/install/x60_unbrick.texi b/docs/src/install/x60_unbrick.texi new file mode 100644 index 0000000..e70e56c --- /dev/null +++ b/docs/src/install/x60_unbrick.texi @@ -0,0 +1,164 @@ +\input texinfo +@documentencoding UTF-8 + +@ifnottex +@paragraphindent 0 +@end ifnottex +@titlepage +@title ThinkPad X60: Recovery guide +@end titlepage + +@node Top +@top ThinkPad X60: Recovery guide + +@menu +* ThinkPad X60 Recovery guide:: +* Table of Contents:: +* Brick type 1 bucts not reset:: +* bad rom or user error system won't boot:: +@end menu + +@node ThinkPad X60 Recovery guide +@chapter ThinkPad X60: Recovery guide +@anchor{#thinkpad-x60-recovery-guide} +This section documents how to recover from a bad flash that prevents your ThinkPad X60 from booting. + +@uref{index.html,Back to previous index} + +@node Table of Contents +@chapter Table of Contents +@anchor{#table-of-contents} +@itemize +@item +Types of brick: +@itemize +@item +@ref{#bucts_brick,Brick type 1: bucts not reset} +@item +@ref{#recovery,Brick type 2: bad rom (or user error), system won't boot} +@end itemize + +@end itemize + +@node Brick type 1 bucts not reset +@chapter Brick type 1: bucts not reset. +@anchor{#brick-type-1-bucts-not-reset.} +You still have Lenovo BIOS, or you had libreboot running and you flashed another ROM; and you had bucts 1 set and the ROM wasn't dd'd.* or if Lenovo BIOS was present and libreboot wasn't flashed.@*@* In this case, unbricking is easy: reset BUC.TS to 0 by removing that yellow cmos coin (it's a battery) and putting it back after a minute or two:@* @image{../resources/images/x60_unbrick/0004,,,,jpg}@*@* *Those dd commands should be applied to all newly compiled X60 ROM images (the ROM images in libreboot binary archives already have this applied!):@* dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k@* dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump@* dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k conv=notrunc@* (doing this makes the ROM suitable for use when flashing a system that still has Lenovo BIOS running, using those instructions: @uref{http://www.coreboot.org/Board:lenovo/x60/Installation,http://www.coreboot.org/Board:lenovo/x60/Installation}. + +@node bad rom or user error system won't boot +@chapter bad rom (or user error), system won't boot +@anchor{#bad-rom-or-user-error-system-wont-boot} +In this scenario, you compiled a ROM that had an incorrect configuration, or there is an actual bug preventing your system from booting. Or, maybe, you set BUC.TS to 0 and shut down after first flash while Lenovo BIOS was running. In any case, your system is bricked and will not boot at all. + +"Unbricking" means flashing a known-good (working) ROM. The problem: you can't boot the system, making this difficult. In this situation, external hardware (see hardware requirements above) is needed which can flash the SPI chip (where libreboot resides). + +Remove those screws:@* @image{../resources/images/x60_unbrick/0000,,,,jpg} + +Push the keyboard forward (carefully):@* @image{../resources/images/x60_unbrick/0001,,,,jpg} + +Lift the keyboard up and disconnect it from the board:@* @image{../resources/images/x60_unbrick/0002,,,,jpg} + +Grab the right-hand side of the chassis and force it off (gently) and pry up the rest of the chassis:@* @image{../resources/images/x60_unbrick/0003,,,,jpg} + +You should now have this:@* @image{../resources/images/x60_unbrick/0004,,,,jpg} + +Disconnect the wifi antenna cables, the modem cable and the speaker:@* @image{../resources/images/x60_unbrick/0005,,,,jpg} + +Unroute the cables along their path, carefully lifting the tape that holds them in place. Then, disconnect the modem cable (other end) and power connection and unroute all the cables so that they dangle by the monitor hinge on the right-hand side:@* @image{../resources/images/x60_unbrick/0006,,,,jpg} + +Disconnect the monitor from the motherboard, and unroute the grey antenna cable, carefully lifting the tape that holds it into place:@* @image{../resources/images/x60_unbrick/0008,,,,jpg} + +Carefully lift the remaining tape and unroute the left antenna cable so that it is loose:@* @image{../resources/images/x60_unbrick/0009,,,,jpg} + +Remove the screw that is highlighted (do NOT remove the other one; it holds part of the heatsink (other side) into place):@* @image{../resources/images/x60_unbrick/0011,,,,jpg} + +Remove those screws:@* @image{../resources/images/x60_unbrick/0012,,,,jpg} + +Carefully remove the plate, like so:@* @image{../resources/images/x60_unbrick/0013,,,,jpg} + +Remove the SATA connector:@* @image{../resources/images/x60_unbrick/0014,,,,jpg} + +Now remove the motherboard (gently) and cast the lcd/chassis aside:@* @image{../resources/images/x60_unbrick/0015,,,,jpg} + +Lift back that tape and hold it with something. Highlighted is the SPI flash chip:@* @image{../resources/images/x60_unbrick/0016,,,,jpg} + +Now wire up the BBB and the Pomona with your PSU.@* Refer to @uref{bbb_setup.html,bbb_setup.html} for how to setup the BBB for flashing.@* @strong{Note, the guide mentions a 3.3v DC PSU but you don't need this on the X60: if you don't have or don't want to use an external PSU, then make sure not to connect the 3.3v leads mentioned in the guide; instead, connect the AC adapter (the one that normally charges your battery) so that the board has power (but don't boot it up)} @image{../resources/images/x60_unbrick/0017,,,,jpg}@* Correlate the following with the BBB guide linked above: + +@verbatim +POMONA 5250: +=== golden finger and wifi switch ==== + 18 - - 1 + 22 - - NC ---------- audio jacks are on this end + NC - - 21 + 3.3V (PSU) - - 17 - this is pin 1 on the flash chip +=== CPU fan === +This is how you will connect. Numbers refer to pin numbers on the BBB, on the plugs near the DC jack. +@end verbatim + +Connecting the BBB and pomona (in this image, an external 3.3v DC PSU was used):@* @image{../resources/images/x60/th_bbb_flashing,,,,jpg} + +Flashrom binaries for ARM (tested on a BBB) are distributed in libreboot_util. Alternatively, libreboot also distributes flashrom source code which can be built. + +SSH'd into the BBB:@* # @strong{./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -w yourrom.rom} + +It should be @strong{Verifying flash... VERIFIED} at the end. If flashrom complains about multiple flash chip definitions detected, then choose one of them following the instructions in the output. + +Remove the programmer and put it away somewhere. Put back the tape and press firmly over it:@* @image{../resources/images/x60_unbrick/0026,,,,jpg} + +Your empty chassis:@* @image{../resources/images/x60_unbrick/0027,,,,jpg} + +Put the motherboard back in:@* @image{../resources/images/x60_unbrick/0028,,,,jpg} + +Reconnect SATA:@* @image{../resources/images/x60_unbrick/0029,,,,jpg} + +Put the plate back and re-insert those screws:@* @image{../resources/images/x60_unbrick/0030,,,,jpg} + +Re-route that antenna cable around the fan and apply the tape:@* @image{../resources/images/x60_unbrick/0031,,,,jpg} + +Route the cable here and then (not shown, due to error on my part) reconnect the monitor cable to the motherboard and re-insert the screws:@* @image{../resources/images/x60_unbrick/0032,,,,jpg} + +Re-insert that screw:@* @image{../resources/images/x60_unbrick/0033,,,,jpg} + +Route the black antenna cable like so:@* @image{../resources/images/x60_unbrick/0034,,,,jpg} + +Tuck it in neatly like so:@* @image{../resources/images/x60_unbrick/0035,,,,jpg} + +Route the modem cable like so:@* @image{../resources/images/x60_unbrick/0036,,,,jpg} + +Connect modem cable to board and tuck it in neatly like so:@* @image{../resources/images/x60_unbrick/0037,,,,jpg} + +Route the power connection and connect it to the board like so:@* @image{../resources/images/x60_unbrick/0038,,,,jpg} + +Route the antenna and modem cables neatly like so:@* @image{../resources/images/x60_unbrick/0039,,,,jpg} + +Connect the wifi antenna cables. At the start of the tutorial, this system had an Intel wifi chip. Here you see I've replaced it with an Atheros AR5B95 (supports 802.11n and can be used without blobs):@* @image{../resources/images/x60_unbrick/0040,,,,jpg} + +Connect the modem cable:@* @image{../resources/images/x60_unbrick/0041,,,,jpg} + +Connect the speaker:@* @image{../resources/images/x60_unbrick/0042,,,,jpg} + +You should now have this:@* @image{../resources/images/x60_unbrick/0043,,,,jpg} + +Re-connect the upper chassis:@* @image{../resources/images/x60_unbrick/0044,,,,jpg} + +Re-connect the keyboard:@* @image{../resources/images/x60_unbrick/0045,,,,jpg} + +Re-insert the screws that you removed earlier:@* @image{../resources/images/x60_unbrick/0046,,,,jpg} + +Power on!@* @image{../resources/images/x60_unbrick/0047,,,,jpg} + +Trisquel live USB menu (using the GRUB ISOLINUX parser):@* @image{../resources/images/x60_unbrick/0048,,,,jpg} + +Trisquel live desktop:@* @image{../resources/images/x60_unbrick/0049,,,,jpg} + +Copyright © 2014, 2015 Francis Rowe <info@@gluglug.org.uk>@* Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license can be found at @uref{../resources/licenses/gfdl-1.3.txt,gfdl-1.3.txt} + +Updated versions of the license (when available) can be found at @uref{https://www.gnu.org/licenses/licenses.html,https://www.gnu.org/licenses/licenses.html} + +UNLESS OTHERWISE SEPARATELY UNDERTAKEN BY THE LICENSOR, TO THE EXTENT POSSIBLE, THE LICENSOR OFFERS THE LICENSED MATERIAL AS-IS AND AS-AVAILABLE, AND MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND CONCERNING THE LICENSED MATERIAL, WHETHER EXPRESS, IMPLIED, STATUTORY, OR OTHER. THIS INCLUDES, WITHOUT LIMITATION, WARRANTIES OF TITLE, MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NON-INFRINGEMENT, ABSENCE OF LATENT OR OTHER DEFECTS, ACCURACY, OR THE PRESENCE OR ABSENCE OF ERRORS, WHETHER OR NOT KNOWN OR DISCOVERABLE. WHERE DISCLAIMERS OF WARRANTIES ARE NOT ALLOWED IN FULL OR IN PART, THIS DISCLAIMER MAY NOT APPLY TO YOU. + +TO THE EXTENT POSSIBLE, IN NO EVENT WILL THE LICENSOR BE LIABLE TO YOU ON ANY LEGAL THEORY (INCLUDING, WITHOUT LIMITATION, NEGLIGENCE) OR OTHERWISE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, CONSEQUENTIAL, PUNITIVE, EXEMPLARY, OR OTHER LOSSES, COSTS, EXPENSES, OR DAMAGES ARISING OUT OF THIS PUBLIC LICENSE OR USE OF THE LICENSED MATERIAL, EVEN IF THE LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH LOSSES, COSTS, EXPENSES, OR DAMAGES. WHERE A LIMITATION OF LIABILITY IS NOT ALLOWED IN FULL OR IN PART, THIS LIMITATION MAY NOT APPLY TO YOU. + +The disclaimer of warranties and limitation of liability provided above shall be interpreted in a manner that, to the extent possible, most closely approximates an absolute disclaimer and waiver of all liability. + +@bye diff --git a/docs/src/install/x60tablet_unbrick.texi b/docs/src/install/x60tablet_unbrick.texi new file mode 100644 index 0000000..90e19ce --- /dev/null +++ b/docs/src/install/x60tablet_unbrick.texi @@ -0,0 +1,112 @@ +\input texinfo +@documentencoding UTF-8 + +@ifnottex +@paragraphindent 0 +@end ifnottex +@titlepage +@title ThinkPad X60 Tablet: Recovery guide +@end titlepage + +@node Top +@top ThinkPad X60 Tablet: Recovery guide + +@menu +* ThinkPad X60 Tablet Recovery guide:: +* Brick type 1 bucts not reset:: +* bad rom or user error system won't boot:: +@end menu + +@node ThinkPad X60 Tablet Recovery guide +@chapter ThinkPad X60 Tablet: Recovery guide +@anchor{#thinkpad-x60-tablet-recovery-guide} +This section documents how to recover from a bad flash that prevents your ThinkPad X60 Tablet from booting. + +@uref{index.html,Back to previous index} +@menu +* Table of Contents:: +@end menu + +@node Table of Contents +@section Table of Contents +@anchor{#table-of-contents} +@itemize +@item +Types of brick: +@itemize +@item +@ref{#bucts_brick,Brick type 1: bucts not reset} +@item +@ref{#recovery,Brick type 2: bad rom (or user error), system won't boot} +@end itemize + +@end itemize + +@node Brick type 1 bucts not reset +@chapter Brick type 1: bucts not reset. +@anchor{#brick-type-1-bucts-not-reset.} +You still have Lenovo BIOS, or you had libreboot running and you flashed another ROM; and you had bucts 1 set and the ROM wasn't dd'd.* or if Lenovo BIOS was present and libreboot wasn't flashed.@*@* In this case, unbricking is easy: reset BUC.TS to 0 by removing that yellow cmos coin (it's a battery) and putting it back after a minute or two:@* @image{../resources/images/x60t_unbrick/0008,,,,JPG}@*@* *Those dd commands should be applied to all newly compiled X60 ROM images (the ROM images in libreboot binary archives already have this applied!):@* dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k@* dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump@* dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k conv=notrunc@* (doing this makes the ROM suitable for use when flashing a system that still has Lenovo BIOS running, using those instructions: @uref{http://www.coreboot.org/Board:lenovo/x60/Installation,http://www.coreboot.org/Board:lenovo/x60/Installation}. + +@node bad rom or user error system won't boot +@chapter bad rom (or user error), system won't boot +@anchor{#bad-rom-or-user-error-system-wont-boot} +In this scenario, you compiled a ROM that had an incorrect configuration, or there is an actual bug preventing your system from booting. Or, maybe, you set BUC.TS to 0 and shut down after first flash while Lenovo BIOS was running. In any case, your system is bricked and will not boot at all. + +"Unbricking" means flashing a known-good (working) ROM. The problem: you can't boot the system, making this difficult. In this situation, external hardware (see hardware requirements above) is needed which can flash the SPI chip (where libreboot resides). + +@image{../resources/images/x60t_unbrick/0000,,,,JPG} + +Remove those screws:@* @image{../resources/images/x60t_unbrick/0001,,,,JPG} + +Remove the HDD:@* @image{../resources/images/x60t_unbrick/0002,,,,JPG} + +Push keyboard forward to loosen it:@* @image{../resources/images/x60t_unbrick/0003,,,,JPG} + +Lift:@* @image{../resources/images/x60t_unbrick/0004,,,,JPG} + +Remove those:@* @image{../resources/images/x60t_unbrick/0005,,,,JPG} + +@image{../resources/images/x60t_unbrick/0006,,,,JPG} + +Also remove that (marked) and unroute the antenna cables:@* @image{../resources/images/x60t_unbrick/0007,,,,JPG} + +For some X60T laptops, you have to unroute those too:@* @image{../resources/images/x60t_unbrick/0010,,,,JPG} + +Remove the LCD extend board screws. Also remove those screws (see blue marks) and remove/unroute the cables and remove the metal plate:@* @image{../resources/images/x60t_unbrick/0008,,,,JPG} + +Remove that screw and then remove the board:@* @image{../resources/images/x60t_unbrick/0009,,,,JPG} + +Now wire up the BBB and the Pomona with your PSU.@* Refer to @uref{bbb_setup.html,bbb_setup.html} for how to setup the BBB for flashing.@* @strong{Note, the guide mentions a 3.3v DC PSU but you don't need this on the X60 Tablet: if you don't have or don't want to use an external PSU, then make sure not to connect the 3.3v leads mentioned in the guide; instead, connect the AC adapter (the one that normally charges your battery) so that the board has power (but don't boot it up)} @image{../resources/images/x60t_unbrick/0011,,,,JPG}@* Correlate the following with the BBB guide linked above: + +@verbatim +POMONA 5250: +=== golden finger and wifi switch ==== + 18 - - 1 + 22 - - NC ---------- audio jacks are on this end + NC - - 21 + 3.3V (PSU) - - 17 - this is pin 1 on the flash chip +=== CPU fan === +This is how you will connect. Numbers refer to pin numbers on the BBB, on the plugs near the DC jack. +@end verbatim + +Connecting the BBB and pomona (in this image, an external 3.3v DC PSU was used):@* @image{../resources/images/x60/th_bbb_flashing,,,,jpg} + +Flashrom binaries for ARM (tested on a BBB) are distributed in libreboot_util. Alternatively, libreboot also distributes flashrom source code which can be built. + +SSH'd into the BBB:@* # @strong{./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -w yourrom.rom} + +It should be @strong{Verifying flash... VERIFIED} at the end. If flashrom complains about multiple flash chip definitions detected, then choose one of them following the instructions in the output. + +Reverse the steps to re-assemble your system. + +Copyright © 2014, 2015 Francis Rowe <info@@gluglug.org.uk>@* Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license can be found at @uref{../resources/licenses/gfdl-1.3.txt,gfdl-1.3.txt} + +Updated versions of the license (when available) can be found at @uref{https://www.gnu.org/licenses/licenses.html,https://www.gnu.org/licenses/licenses.html} + +UNLESS OTHERWISE SEPARATELY UNDERTAKEN BY THE LICENSOR, TO THE EXTENT POSSIBLE, THE LICENSOR OFFERS THE LICENSED MATERIAL AS-IS AND AS-AVAILABLE, AND MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND CONCERNING THE LICENSED MATERIAL, WHETHER EXPRESS, IMPLIED, STATUTORY, OR OTHER. THIS INCLUDES, WITHOUT LIMITATION, WARRANTIES OF TITLE, MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NON-INFRINGEMENT, ABSENCE OF LATENT OR OTHER DEFECTS, ACCURACY, OR THE PRESENCE OR ABSENCE OF ERRORS, WHETHER OR NOT KNOWN OR DISCOVERABLE. WHERE DISCLAIMERS OF WARRANTIES ARE NOT ALLOWED IN FULL OR IN PART, THIS DISCLAIMER MAY NOT APPLY TO YOU. + +TO THE EXTENT POSSIBLE, IN NO EVENT WILL THE LICENSOR BE LIABLE TO YOU ON ANY LEGAL THEORY (INCLUDING, WITHOUT LIMITATION, NEGLIGENCE) OR OTHERWISE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, CONSEQUENTIAL, PUNITIVE, EXEMPLARY, OR OTHER LOSSES, COSTS, EXPENSES, OR DAMAGES ARISING OUT OF THIS PUBLIC LICENSE OR USE OF THE LICENSED MATERIAL, EVEN IF THE LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH LOSSES, COSTS, EXPENSES, OR DAMAGES. WHERE A LIMITATION OF LIABILITY IS NOT ALLOWED IN FULL OR IN PART, THIS LIMITATION MAY NOT APPLY TO YOU. + +The disclaimer of warranties and limitation of liability provided above shall be interpreted in a manner that, to the extent possible, most closely approximates an absolute disclaimer and waiver of all liability. + +@bye |