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-rw-r--r--docs/src/hcl/c201.texi161
-rw-r--r--docs/src/hcl/gm45_lcd.texi298
-rw-r--r--docs/src/hcl/gm45_remove_me.texi437
-rw-r--r--docs/src/hcl/index.texi543
-rw-r--r--docs/src/hcl/kfsn4-dre.texi88
-rw-r--r--docs/src/hcl/kgpe-d16.texi326
-rw-r--r--docs/src/hcl/r400.texi70
-rw-r--r--docs/src/hcl/r500.texi190
-rw-r--r--docs/src/hcl/t400.texi88
-rw-r--r--docs/src/hcl/t500.texi98
-rw-r--r--docs/src/hcl/x200.texi220
11 files changed, 2519 insertions, 0 deletions
diff --git a/docs/src/hcl/c201.texi b/docs/src/hcl/c201.texi
new file mode 100644
index 0000000..28ed66e
--- /dev/null
+++ b/docs/src/hcl/c201.texi
@@ -0,0 +1,161 @@
+\input texinfo
+@documentencoding UTF-8
+
+@ifnottex
+@paragraphindent 0
+@end ifnottex
+@titlepage
+@title ASUS Chromebook C201
+@end titlepage
+
+@node Top
+@top ASUS Chromebook C201
+
+@menu
+* ASUS Chromebook C201::
+* Google's intent with CrOS devices::
+* Considerations about ChromeOS and free operating systems::
+* Caution Video acceleration requires a non-free blob software rendering can be used instead::
+* Caution WiFi requires a non-free blob a USB dongle can be used instead::
+* EC firmware is free software!::
+* No microcode!::
+* Depthcharge payload::
+* Flash chip write protection the screw::
+@end menu
+
+@node ASUS Chromebook C201
+@chapter ASUS Chromebook C201
+@anchor{#asus-chromebook-c201}
+This is a Chromebook, using the Rockchip RK3288 SoC. It uses an ARM CPU, and has free EC firmware (unlike some other laptops). More RK3288-based laptops will be added to libreboot at a later date.
+
+Paul Kocialkowski, a @uref{http://www.replicant.us/,Replicant} developer, ported this laptop to libreboot. Thank you, Paul!
+
+@strong{NOTE: This board is unsupported in libreboot 20150518. To use it in libreboot, for now, you must build for it from source using the libreboot git repository. Note that we recommend building for it from an x86 host, until libreboot's build system is modified accordingly.}
+
+@strong{More info will be added later, including build/installation instructions. The board is supported in libreboot, however, and has been confirmed to work.}
+
+Flashing instructions can be found at @uref{../install/index.html#flashrom,../install/index.html#flashrom}
+
+@uref{index.html,Back to previous index}.
+
+@itemize
+@item
+@ref{#googlesintent,Google's intent with CrOS devices}
+@item
+@ref{#os,Considerations about ChromeOS and free operating systems}
+@item
+@ref{#videoblobs,Caution: Video acceleration requires a non-free blob, software rendering can be used instead.}
+@item
+@ref{#wifiblobs,Caution: WiFi requires a non-free blob, a USB dongle can be used instead.}
+@item
+@ref{#ec,EC firmware is free software!}
+@item
+@ref{#microcode,No microcode!}
+@item
+@ref{#depthcharge,Depthcharge payload}
+@item
+@ref{#thescrew,Flash chip write protection: the screw}
+@end itemize
+
+@node Google's intent with CrOS devices
+@chapter Google's intent with CrOS devices
+@anchor{#googles-intent-with-cros-devices}
+CrOS (Chromium OS/Chrome OS) devices, such as Chromebooks, were not designed with the intent of bringing more freedom to users. However, they run with a lot of free software at the boot software and embedded controller levels, since free software gives Google enough flexibility to optimize various aspects such as boot time and most importantly, to implement the CrOS security system, that involves various aspects of the software. Google does hire a lot of Coreboot developers, who are generally friendly to the free software movement and try to be good members of the free software community, by contributing code back.
+
+CrOS devices are designed (from the factory) to actually coax the user into using @uref{https://www.gnu.org/philosophy/who-does-that-server-really-serve.en.html,proprietary web services} (SaaSS) that invade the user's privacy (ChromeOS is literally just the Google Chrome browser when you boot up, itself proprietary and comes with proprietary add-ons like flash. It's only intended for SaaSS, not actual, real computing). Google is even a member of the @emph{PRISM} program, as outlined by Edward Snowden. See notes about ChromeOS below. The libreboot project recommends that the user replace the default @emph{ChromeOS} with a distribution that can be used in freedom, without invading the user's privacy.
+
+We also use a similar argument for the MacBook and the ThinkPads that are supported in libreboot. Those laptops are supported, in spite of Apple and Lenovo, companies which are actually @emph{hostile} to the free software movement.
+
+@ref{#pagetop,Back to top of page}.
+
+@node Considerations about ChromeOS and free operating systems
+@chapter Considerations about ChromeOS and free operating systems
+@anchor{#considerations-about-chromeos-and-free-operating-systems}
+This laptop comes preinstalled (from the factory) with Google ChromeOS. This is a GNU/Linux distribution, but it's not general purpose and it comes with proprietary software. It's designed for @emph{@uref{https://www.gnu.org/philosophy/who-does-that-server-really-serve.en.html,SaaSS}}. Libreboot recommends that users of this laptop replace it with another distribution.
+@menu
+* No FSF-endorsed distros available::
+@end menu
+
+@node No FSF-endorsed distros available
+@section No FSF-endorsed distros available
+@anchor{#no-fsf-endorsed-distros-available}
+The FSF has a @uref{https://www.gnu.org/distros/free-distros.html,list of distributions} that are 100% free software. None of these are confirmed to work on ARM CrOS devices yet. Parabola looks hopeful: @uref{https://www.parabola.nu/news/parabola-supports-armv7/,https://www.parabola.nu/news/parabola-supports-armv7/}
+
+The libreboot project would like to see all FSF-endorsed distro projects port to these laptops. This includes Trisquel, GuixSD and others. And ProteanOS. Maybe even LibreCMC. The more the merrier. We need them, badly.
+
+@strong{We need these distributions to be ported as soon as possible.}
+
+@ref{#pagetop,Back to top of page}.
+
+@node Caution Video acceleration requires a non-free blob software rendering can be used instead
+@chapter Caution: Video acceleration requires a non-free blob, software rendering can be used instead.
+@anchor{#caution-video-acceleration-requires-a-non-free-blob-software-rendering-can-be-used-instead.}
+The lima driver source code for the onboard Mali GPU is not released. The developer withheld it for personal reasons. Until that is released, the only way to use video (in freedom) on this laptop is to not have video acceleration, by making sure not to install the relevant blob. Most tasks can still be performed without video acceleration, without any noticeable performance penalty.
+
+In practise, this means that certain things like games, blender and GNOME shell (or other fancy desktops) won't work well. The libreboot project recommends a lightweight desktop which does not need video acceleration, such as @emph{XFCE} or @emph{LXDE}.
+
+The lima developer wrote this blog post, which sheds light on the story: @uref{http://libv.livejournal.com/27461.html,http://libv.livejournal.com/27461.html}
+
+@ref{#pagetop,Back to top of page}.
+
+@node Caution WiFi requires a non-free blob a USB dongle can be used instead
+@chapter Caution: WiFi requires a non-free blob, a USB dongle can be used instead.
+@anchor{#caution-wifi-requires-a-non-free-blob-a-usb-dongle-can-be-used-instead.}
+These laptops have non-removeable (soldered on) WiFi chips, which require non-free firmware in the Linux kernel in order to work.
+
+The libreboot project recommends using an external USB wifi dongle that works with free software. See @uref{index.html#recommended_wifi,index.html#recommended_wifi}.
+
+There are 2 companies (endorsed by the Free Software Foundation, under their @emph{Respects your Freedom} guidelines), that sell USB WiFi dongles guaranteed to work with free software (i.e. linux-libre kernel):
+
+@itemize
+@item
+@uref{https://www.thinkpenguin.com/gnu-linux/penguin-wireless-n-usb-adapter-gnu-linux-tpe-n150usb,ThinkPenguin sells them} (company based in USA)
+@item
+@uref{https://tehnoetic.com/tehnoetic-wireless-adapter-gnu-linux-libre-tet-n150,Tehnoetic sells them} (company based in Europe)
+@end itemize
+
+These wifi dongles use the AR9271 (atheros) chipset, supported by the free @emph{ath9k_htc} driver in the Linux kernel. They work in @emph{linux-libre} too.
+
+@node EC firmware is free software!
+@chapter EC firmware is free software!
+@anchor{#ec-firmware-is-free-software}
+It's free software. Google provides the source. Build scripts will be added later, with EC sources provided in libreboot, and builds of the EC firmware.
+
+This is unlike the other current libreboot laptops (Intel based). In practise, you can (if you do without the video/wifi blobs, and replace ChromeOS with a distribution that respects your freedom) be more free when using one of these laptops.
+
+The libreboot FAQ briefly describes what an @emph{EC} is: @uref{http://libreboot.org/faq/#firmware-ec,http://libreboot.org/faq/#firmware-ec}
+
+@node No microcode!
+@chapter No microcode!
+@anchor{#no-microcode}
+Unlike x86 (e.g. Intel/AMD) CPUs, ARM CPUs do not use microcode, not even built in. On the Intel/AMD based libreboot systems, there is still microcode in the CPU (not considered problematic by the FSF, provided that it is reasonably trusted to not be malicious, since it's part of the hardware and read-only), but we exclude microcode updates (volatile updates which are uploaded at boot time by the boot firmware, if present), which are proprietary software.
+
+On ARM CPUs, the instruction set is implemented in circuitry, without microcode.
+
+@ref{#pagetop,Back to top of page}.
+
+@node Depthcharge payload
+@chapter Depthcharge payload
+@anchor{#depthcharge-payload}
+These systems do not use the GRUB payload. Instead, they use a payload called depthcharge, which is common on CrOS devices. This is free software, maintained by Google.
+
+@node Flash chip write protection the screw
+@chapter Flash chip write protection: the screw
+@anchor{#flash-chip-write-protection-the-screw}
+It's next to the flash chip. Unscrew it, and the flash chip is read-write. Screw it back in, and the flash chip is read-only. It's called the screw.
+
+@emph{The screw} is accessible by removing other screws and gently prying off the upper shell, where the flash chip and the screw are then directly accessible. User flashing from software is possible, without having to externally re-flash, but the flash chip is SPI (SOIC-8 form factor) so you can also externally re-flash if you want to. In practise, you only need to externally re-flash if you brick the laptop; read @uref{../install/bbb_setup.html,../install/bbb_setup.html} for an example of how to set up an SPI programmer.
+
+Write protection is useful, because it prevents the firmware from being re-flashed by any malicious software that might become executed on your GNU/Linux system, as root. In other words, it can prevent a firmware-level @emph{evil maid} attack. It's possible to write protect on all current libreboot systems, but CrOS devices make it easy. The screw is such a stupidly simple idea, which all designs should implement.
+
+Copyright © 2015 Francis Rowe <info@@gluglug.org.uk>@* Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license can be found at @uref{../resources/licenses/gfdl-1.3.txt,gfdl-1.3.txt}
+
+Updated versions of the license (when available) can be found at @uref{https://www.gnu.org/licenses/licenses.html,https://www.gnu.org/licenses/licenses.html}
+
+UNLESS OTHERWISE SEPARATELY UNDERTAKEN BY THE LICENSOR, TO THE EXTENT POSSIBLE, THE LICENSOR OFFERS THE LICENSED MATERIAL AS-IS AND AS-AVAILABLE, AND MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND CONCERNING THE LICENSED MATERIAL, WHETHER EXPRESS, IMPLIED, STATUTORY, OR OTHER. THIS INCLUDES, WITHOUT LIMITATION, WARRANTIES OF TITLE, MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NON-INFRINGEMENT, ABSENCE OF LATENT OR OTHER DEFECTS, ACCURACY, OR THE PRESENCE OR ABSENCE OF ERRORS, WHETHER OR NOT KNOWN OR DISCOVERABLE. WHERE DISCLAIMERS OF WARRANTIES ARE NOT ALLOWED IN FULL OR IN PART, THIS DISCLAIMER MAY NOT APPLY TO YOU.
+
+TO THE EXTENT POSSIBLE, IN NO EVENT WILL THE LICENSOR BE LIABLE TO YOU ON ANY LEGAL THEORY (INCLUDING, WITHOUT LIMITATION, NEGLIGENCE) OR OTHERWISE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, CONSEQUENTIAL, PUNITIVE, EXEMPLARY, OR OTHER LOSSES, COSTS, EXPENSES, OR DAMAGES ARISING OUT OF THIS PUBLIC LICENSE OR USE OF THE LICENSED MATERIAL, EVEN IF THE LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH LOSSES, COSTS, EXPENSES, OR DAMAGES. WHERE A LIMITATION OF LIABILITY IS NOT ALLOWED IN FULL OR IN PART, THIS LIMITATION MAY NOT APPLY TO YOU.
+
+The disclaimer of warranties and limitation of liability provided above shall be interpreted in a manner that, to the extent possible, most closely approximates an absolute disclaimer and waiver of all liability.
+
+@bye
diff --git a/docs/src/hcl/gm45_lcd.texi b/docs/src/hcl/gm45_lcd.texi
new file mode 100644
index 0000000..e1e87e1
--- /dev/null
+++ b/docs/src/hcl/gm45_lcd.texi
@@ -0,0 +1,298 @@
+\input texinfo
+@documentencoding UTF-8
+
+@ifnottex
+@paragraphindent 0
+@end ifnottex
+@titlepage
+@title LCD compatibility on GM45 laptops
+@end titlepage
+
+@node Top
+@top LCD compatibility on GM45 laptops
+
+@menu
+* LCD compatibility on GM45 laptops::
+* The problem::
+* Current workaround::
+* Differences in dmesg kernel parameter added ::
+@end menu
+
+@node LCD compatibility on GM45 laptops
+@chapter LCD compatibility on GM45 laptops
+@anchor{#lcd-compatibility-on-gm45-laptops}
+On the T400 and T500 (maybe others), some of the higher resolution panels (e.g. 1440x900, 1680x1050, 1920x1200) fail in libreboot.
+
+It is currently unknown, whether there exist any compatibility issues on the ThinkPad R500.
+
+@strong{All X200/X200S/X200T LCD panels are believed to be compatible.}
+
+@uref{index.html,Back to previous index}.
+
+@node The problem
+@chapter The problem
+@anchor{#the-problem}
+In some cases, backlight turns on during boot, sometimes not. In all cases, no display is shown in GRUB, nor in GNU/Linux.
+
+@node Current workaround
+@chapter Current workaround:
+@anchor{#current-workaround}
+Libreboot (git, and releases after 20150518) now automatically detect whether to use single or dual link LVDS configuration. If you're using an older version, use the instructions below. In practise, this means that you'll get a visual display when booting GNU/Linux, but not in GRUB (payload).
+
+The i915 module in the Linux kernel also provides an option to set the LVDS link configuration. i915.lvds_channel_mode:Specify LVDS channel mode (0=probe BIOS [default], 1=single-channel, 2=dual-channel) (int) - from /sbin/modinfo i915 - use @strong{i915.lvds_channel_mode=2} as a kernel option in grub.cfg.
+
+@node Differences in dmesg kernel parameter added
+@chapter Differences in dmesg (kernel parameter added: )
+@anchor{#differences-in-dmesg-kernel-parameter-added}
+@uref{https://01.org/linuxgraphics/documentation/how-report-bugs,https://01.org/linuxgraphics/documentation/how-report-bugs}
+
+These panels all work in the original firmware, so the idea is to see what differences there are in how coreboot handles them.
+
+@uref{http://www.coreboot.org/pipermail/coreboot/attachments/20150712/d2e214bb/attachment-0002.txt,dmesg with coreboot-libre} (coreboot) - See: @emph{[drm:intel_lvds_init] detected single-link lvds configuration}
+
+@uref{http://www.coreboot.org/pipermail/coreboot/attachments/20150712/d2e214bb/attachment-0003.txt,dmesg with lenovobios} (lenovobios) - For the same line, it says dual-channel lvds configuration.
+@menu
+* EDID::
+@end menu
+
+@node EDID
+@section EDID
+@anchor{#edid}
+One T500 had a screen (1920x1200) that is currently incompatible. Working to fix it. EDID:
+
+@verbatim
+user@user-ThinkPad-T500:~/Desktop$ sudo i2cdump -y 2 0x50
+No size specified (using byte-data access)
+ 0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef
+00: XX ff ff ff ff ff ff 00 30 ae 55 40 00 00 00 00 X.......0?U@....
+10: 00 11 01 03 80 21 15 78 ea ba 70 98 59 52 8c 28 .????!?x??p?YR?(
+20: 25 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01 %PT...??????????
+30: 01 01 01 01 01 01 e7 3a 80 8c 70 b0 14 40 1e 50 ???????:??p??@?P
+40: 24 00 4b cf 10 00 00 19 16 31 80 8c 70 b0 14 40 $.K??..??1??p??@
+50: 1e 50 24 00 4b cf 10 00 00 19 00 00 00 0f 00 d1 ?P$.K??..?...?.?
+60: 0a 32 d1 0a 28 11 01 00 32 0c 00 00 00 00 00 fe ?2??(??.2?.....?
+70: 00 4c 50 31 35 34 57 55 31 2d 54 4c 42 31 00 9a .LP154WU1-TLB1.?
+80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
+90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
+a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
+b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
+c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
+d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
+e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
+f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
+@end verbatim
+
+What happens: backlight turns on at boot, then turns off. At no point is there a working visual display.
+
+Another incompatible screen (EDID) 1680 x 1050 with the same issue:
+
+@verbatim
+EDID:
+00 ff ff ff ff ff ff 00 30 ae 53 40 00 00 00 00
+00 11 01 03 80 21 15 78 ea cd 75 91 55 4f 8b 26
+21 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01
+01 01 01 01 01 01 a8 2f 90 e0 60 1a 10 40 20 40
+13 00 4b cf 10 00 00 19 b7 27 90 e0 60 1a 10 40
+20 40 13 00 4b cf 10 00 00 19 00 00 00 0f 00 b3
+0a 32 b3 0a 28 14 01 00 4c a3 50 33 00 00 00 fe
+00 4c 54 4e 31 35 34 50 33 2d 4c 30 32 0a 00 7e
+Extracted contents:
+header: 00 ff ff ff ff ff ff 00
+serial number: 30 ae 53 40 00 00 00 00 00 11
+version: 01 03
+basic params: 80 21 15 78 ea
+chroma info: cd 75 91 55 4f 8b 26 21 50 54
+established: 00 00 00
+standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
+descriptor 1: a8 2f 90 e0 60 1a 10 40 20 40 13 00 4b cf 10 00 00 19
+descriptor 2: b7 27 90 e0 60 1a 10 40 20 40 13 00 4b cf 10 00 00 19
+descriptor 3: 00 00 00 0f 00 b3 0a 32 b3 0a 28 14 01 00 4c a3 50 33
+descriptor 4: 00 00 00 fe 00 4c 54 4e 31 35 34 50 33 2d 4c 30 32 0a
+extensions: 00
+checksum: 7e
+
+Manufacturer: LEN Model 4053 Serial Number 0
+Made week 0 of 2007
+EDID version: 1.3
+Digital display
+Maximum image size: 33 cm x 21 cm
+Gamma: 220%
+Check DPMS levels
+DPMS levels: Standby Suspend Off
+Supported color formats: RGB 4:4:4, YCrCb 4:2:2
+First detailed timing is preferred timing
+Established timings supported:
+Standard timings supported:
+Detailed timings
+Hex of detail: a82f90e0601a1040204013004bcf10000019
+Did detailed timing
+Detailed mode (IN HEX): Clock 122000 KHz, 14b mm x cf mm
+ 0690 06b0 06f0 0770 hborder 0
+ 041a 041b 041e 042a vborder 0
+ -hsync -vsync
+Hex of detail: b72790e0601a1040204013004bcf10000019
+Detailed mode (IN HEX): Clock 122000 KHz, 14b mm x cf mm
+ 0690 06b0 06f0 0770 hborder 0
+ 041a 041b 041e 042a vborder 0
+ -hsync -vsync
+Hex of detail: 0000000f00b30a32b30a281401004ca35033
+Manufacturer-specified data, tag 15
+Hex of detail: 000000fe004c544e31353450332d4c30320a
+ASCII string: LTN154P3-L02
+Checksum
+Checksum: 0x7e (valid)
+WARNING: EDID block does NOT fully conform to EDID 1.3.
+ Missing name descriptor
+ Missing monitor ranges
+bringing up panel at resolution 1680 x 1050
+Borders 0 x 0
+Blank 224 x 16
+Sync 64 x 3
+Front porch 32 x 1
+Spread spectrum clock
+Single channel
+Polarities 1, 1
+Data M1=2132104, N1=8388608
+Link frequency 270000 kHz
+Link M1=236900, N1=524288
+Pixel N=9, M1=24, M2=8, P1=1
+Pixel clock 243809 kHz
+waiting for panel powerup
+panel powered up
+@end verbatim
+
+Another incompatible (T400) screen:
+
+@verbatim
+No size specified (using byte-data access)
+ 0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef
+00: XX ff ff ff ff ff ff 00 30 ae 33 40 00 00 00 00 X.......0?3@....
+10: 00 0f 01 03 80 1e 13 78 ea cd 75 91 55 4f 8b 26 .??????x??u?UO?&
+20: 21 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01 !PT...??????????
+30: 01 01 01 01 01 01 b0 27 a0 60 51 84 2d 30 30 20 ???????'?`Q?-00
+40: 36 00 2f be 10 00 00 19 d5 1f a0 40 51 84 1a 30 6./??..????@Q??0
+50: 30 20 36 00 2f be 10 00 00 19 00 00 00 0f 00 90 0 6./??..?...?.?
+60: 0a 32 90 0a 28 14 01 00 4c a3 42 44 00 00 00 fe ?2??(??.L?BD...?
+70: 00 4c 54 4e 31 34 31 57 44 2d 4c 30 35 0a 00 32 .LTN141WD-L05?.2
+80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
+90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
+a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
+b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
+c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
+d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
+e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
+f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
+@end verbatim
+
+For comparison, here is a working display (T400 screen, but was connected to a T500. Some T500 displays also work, but no EDID available on this page yet):
+
+@verbatim
+EDID:
+00 ff ff ff ff ff ff 00 30 ae 31 40 00 00 00 00
+00 12 01 03 80 1e 13 78 ea b3 85 95 58 53 8a 28
+25 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01
+01 01 01 01 01 01 26 1b 00 7d 50 20 16 30 30 20
+36 00 30 be 10 00 00 18 8b 16 00 7d 50 20 16 30
+30 20 36 00 30 be 10 00 00 18 00 00 00 0f 00 81
+0a 32 81 0a 28 14 01 00 30 e4 28 01 00 00 00 fe
+00 4c 50 31 34 31 57 58 33 2d 54 4c 52 31 00 d8
+Extracted contents:
+header: 00 ff ff ff ff ff ff 00
+serial number: 30 ae 31 40 00 00 00 00 00 12
+version: 01 03
+basic params: 80 1e 13 78 ea
+chroma info: b3 85 95 58 53 8a 28 25 50 54
+established: 00 00 00
+standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
+descriptor 1: 26 1b 00 7d 50 20 16 30 30 20 36 00 30 be 10 00 00 18
+descriptor 2: 8b 16 00 7d 50 20 16 30 30 20 36 00 30 be 10 00 00 18
+descriptor 3: 00 00 00 0f 00 81 0a 32 81 0a 28 14 01 00 30 e4 28 01
+descriptor 4: 00 00 00 fe 00 4c 50 31 34 31 57 58 33 2d 54 4c 52 31
+extensions: 00
+checksum: d8
+
+Manufacturer: LEN Model 4031 Serial Number 0
+Made week 0 of 2008
+EDID version: 1.3
+Digital display
+Maximum image size: 30 cm x 19 cm
+Gamma: 220%
+Check DPMS levels
+DPMS levels: Standby Suspend Off
+Supported color formats: RGB 4:4:4, YCrCb 4:2:2
+First detailed timing is preferred timing
+Established timings supported:
+Standard timings supported:
+Detailed timings
+Hex of detail: 261b007d502016303020360030be10000018
+Did detailed timing
+Detailed mode (IN HEX): Clock 69500 KHz, 130 mm x be mm
+ 0500 0530 0550 057d hborder 0
+ 0320 0323 0329 0336 vborder 0
+ -hsync -vsync
+Hex of detail: 8b16007d502016303020360030be10000018
+Detailed mode (IN HEX): Clock 69500 KHz, 130 mm x be mm
+ 0500 0530 0550 057d hborder 0
+ 0320 0323 0329 0336 vborder 0
+ -hsync -vsync
+Hex of detail: 0000000f00810a32810a2814010030e42801
+Manufacturer-specified data, tag 15
+Hex of detail: 000000fe004c503134315758332d544c5231
+ASCII string: LP141WX3-TLR1
+Checksum
+Checksum: 0xd8 (valid)
+WARNING: EDID block does NOT fully conform to EDID 1.3.
+ Missing name descriptor
+ Missing monitor ranges
+bringing up panel at resolution 1280 x 800
+Borders 0 x 0
+Blank 125 x 22
+Sync 32 x 6
+Front porch 48 x 3
+Spread spectrum clock
+Single channel
+Polarities 1, 1
+Data M1=1214600, N1=8388608
+Link frequency 270000 kHz
+Link M1=134955, N1=524288
+Pixel N=10, M1=14, M2=11, P1=1
+Pixel clock 138857 kHz
+waiting for panel powerup
+panel powered up
+@end verbatim
+
+Another compatible T400 screen:
+
+@verbatim
+trisquel@trisquel:~$ sudo i2cdump -y 2 0x50
+No size specified (using byte-data access)
+ 0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef
+00: 00 ff ff ff ff ff ff 00 30 ae 31 40 00 00 00 00 ........0?1@....
+10: 00 12 01 03 80 1e 13 78 ea b3 85 95 58 53 8a 28 .??????x????XS?(
+20: 25 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01 %PT...??????????
+30: 01 01 01 01 01 01 26 1b 00 7d 50 20 16 30 30 20 ??????&?.}P ?00
+40: 36 00 30 be 10 00 00 18 8b 16 00 7d 50 20 16 30 6.0??..???.}P ?0
+50: 30 20 36 00 30 be 10 00 00 18 00 00 00 0f 00 81 0 6.0??..?...?.?
+60: 0a 32 81 0a 28 14 01 00 30 e4 28 01 00 00 00 fe ?2??(??.0?(?...?
+70: 00 4c 50 31 34 31 57 58 33 2d 54 4c 52 31 00 d8 .LP141WX3-TLR1.?
+80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
+90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
+a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
+b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
+c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
+d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
+e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
+f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
+@end verbatim
+
+Copyright © 2015 Francis Rowe <info@@gluglug.org.uk>@* Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license can be found at @uref{../resources/licenses/gfdl-1.3.txt,gfdl-1.3.txt}
+
+Updated versions of the license (when available) can be found at @uref{https://www.gnu.org/licenses/licenses.html,https://www.gnu.org/licenses/licenses.html}
+
+UNLESS OTHERWISE SEPARATELY UNDERTAKEN BY THE LICENSOR, TO THE EXTENT POSSIBLE, THE LICENSOR OFFERS THE LICENSED MATERIAL AS-IS AND AS-AVAILABLE, AND MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND CONCERNING THE LICENSED MATERIAL, WHETHER EXPRESS, IMPLIED, STATUTORY, OR OTHER. THIS INCLUDES, WITHOUT LIMITATION, WARRANTIES OF TITLE, MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NON-INFRINGEMENT, ABSENCE OF LATENT OR OTHER DEFECTS, ACCURACY, OR THE PRESENCE OR ABSENCE OF ERRORS, WHETHER OR NOT KNOWN OR DISCOVERABLE. WHERE DISCLAIMERS OF WARRANTIES ARE NOT ALLOWED IN FULL OR IN PART, THIS DISCLAIMER MAY NOT APPLY TO YOU.
+
+TO THE EXTENT POSSIBLE, IN NO EVENT WILL THE LICENSOR BE LIABLE TO YOU ON ANY LEGAL THEORY (INCLUDING, WITHOUT LIMITATION, NEGLIGENCE) OR OTHERWISE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, CONSEQUENTIAL, PUNITIVE, EXEMPLARY, OR OTHER LOSSES, COSTS, EXPENSES, OR DAMAGES ARISING OUT OF THIS PUBLIC LICENSE OR USE OF THE LICENSED MATERIAL, EVEN IF THE LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH LOSSES, COSTS, EXPENSES, OR DAMAGES. WHERE A LIMITATION OF LIABILITY IS NOT ALLOWED IN FULL OR IN PART, THIS LIMITATION MAY NOT APPLY TO YOU.
+
+The disclaimer of warranties and limitation of liability provided above shall be interpreted in a manner that, to the extent possible, most closely approximates an absolute disclaimer and waiver of all liability.
+
+@bye
diff --git a/docs/src/hcl/gm45_remove_me.texi b/docs/src/hcl/gm45_remove_me.texi
new file mode 100644
index 0000000..27c4e6e
--- /dev/null
+++ b/docs/src/hcl/gm45_remove_me.texi
@@ -0,0 +1,437 @@
+\input texinfo
+@documentencoding UTF-8
+
+@macro textstrikeout{text}
+~~\text\~~
+@end macro
+
+@ifnottex
+@paragraphindent 0
+@end ifnottex
+@titlepage
+@title GM45 chipsets: remove the ME (manageability engine)
+@end titlepage
+
+@node Top
+@top GM45 chipsets: remove the ME (manageability engine)
+
+@menu
+* GM45 chipsets remove the ME manageability engine::
+* ICH9 gen utility::
+* ICH9 deblob utility::
+* demefactory utility::
+@end menu
+
+@node GM45 chipsets remove the ME manageability engine
+@chapter GM45 chipsets: remove the ME (manageability engine)
+@anchor{#gm45-chipsets-remove-the-me-manageability-engine}
+This sections relates to disabling and removing the ME (Intel @strong{M}anagement @strong{E}ngine) on GM45. This was originally done on the ThinkPad X200, and later adapted for the ThinkPad R400/T400/T500. It can in principle be done on any GM45 or GS45 system.
+
+The ME is a blob that typically must be left inside the flash chip (in the ME region, as outlined by the default descriptor). On GM45, it is possible to remove it without any ill effects. All other parts of coreboot on GM45 systems (provided GMA MHD4500 / Intel graphics) can be blob-free, so removing the ME was the last obstacle to make GM45 a feasible target in libreboot (the systems can also work without the microcode blobs).
+
+The ME is removed and disabled in libreboot by modifying the descriptor. More info about this can be found in the ich9deblob/ich9gen source code in resources/utilities/ich9deblob/ in libreboot, or more generally on this page.
+
+More information about the ME can be found at @uref{http://www.coreboot.org/Intel_Management_Engine,http://www.coreboot.org/Intel_Management_Engine} and @uref{http://me.bios.io/Main_Page,http://me.bios.io/Main_Page}.
+
+Another project recently found: @uref{http://io.smashthestack.org/me/,http://io.smashthestack.org/me/}
+
+@uref{index.html,Back to previous index}.
+
+@node ICH9 gen utility
+@chapter ICH9 gen utility
+@anchor{#ich9-gen-utility}
+It is no longer necessary to use @ref{#ich9deblob,ich9deblob} to generate a deblobbed descriptor+gbe image for GM45 targets. ich9gen is a small utility within ich9deblob that can generate them from scratch, without a factory.bin dump.
+
+ich9gen executables can be found under ./ich9deblob/ statically compiled in libreboot_util. If you are using src or git, build ich9gen from source with:@* $ @strong{./build module ich9deblob}@* The executable will appear under resources/utilities/ich9deblob/
+
+Run:@* $ @strong{./ich9gen}
+
+Running ich9gen this way (without any arguments) generates a default descriptor+gbe image with a generic MAC address. You probably don't want to use the generic one; the ROM images in libreboot contain a descriptor+gbe image by default (already inserted) just to prevent or mitigate the risk of bricking your laptop, but with the generic MAC address (the libreboot project does not know what your real MAC address is).
+
+You can find out your MAC address from @strong{ip addr} or @strong{ifconfig} in GNU/Linux. Alternatively, if you are running libreboot already (with the correct MAC address in your ROM), dump it (flashrom -r) and read the first 6 bytes from position 0x1000 (or 0x2000) in a hex editor (or, rename it to factory.rom and run it in ich9deblob: in the newly created mkgbe.c will be the individual bytes of your MAC address). If you are currently running the stock firmware and haven't installed libreboot yet, you can also run that through ich9deblob to get the mac address.
+
+An even simpler way to get the MAC address would be to read what's on the little sticker on the bottom/base of the laptop.
+
+On GM45 laptops that use flash descriptors, the MAC address or the onboard ethernet chipset is flashed (inside the ROM image). You should generate a descriptor+gbe image with your own MAC address inside (with the Gbe checksum updated to match). Run:@* $ @strong{./ich9gen --macaddress XX:XX:XX:XX:XX:XX}@* (replace the XX chars with the hexadecimal chars in the MAC address that you want)
+
+Two new files will be created:
+
+@itemize
+@item
+@strong{ich9fdgbe_4m.bin}: this is for GM45 laptops with the 4MB flash chip.
+@item
+@strong{ich9fdgbe_8m.bin}: this is for GM45 laptops with the 8MB flash chip.
+@end itemize
+
+Two other files will also be created, for the ThinkPad R500 which has a different NIC and, therefore, no GbE region (for this laptop, it is not necessary to change the MAC address in the flash chip, because it's burned into the NIC):
+
+@itemize
+@item
+@strong{ich9fdnogbe_4m.bin}: this is for ThinkPad R500 laptops with the 4MB flash chip, where no GbE region is to be defined.
+@item
+@strong{ich9fdnogbe_8m.bin}: this is for ThinkPad R500 laptops with the 8MB flash chip, where no GbE region is to be defined - @strong{NOTE: No actual R500 laptops with 8MiB are believed to exist. It is believed, that all R500 laptops have 4MiB flash chips}.
+@end itemize
+
+Assuming that your libreboot image is named @strong{libreboot.rom}, copy the file to where @strong{libreboot.rom} is located and then insert the descriptor+gbe file into the ROM image. For 8MiB flash chips:@* $ @strong{dd if=ich9fdgbe_8m.bin of=libreboot.rom bs=1 count=12k conv=notrunc}@* For 4MiB flash chips:@* $ @strong{dd if=ich9fdgbe_4m.bin of=libreboot.rom bs=1 count=12k conv=notrunc}@*
+
+@strong{For the ThinkPad R500, do this instead:}@* For 8MiB flash chips (@strong{highly unlikely on the ThinkPad R500)}:@* $ @strong{dd if=ich9fdnogbe_8m.bin of=libreboot.rom bs=1 count=4k conv=notrunc}@* For 4MiB flash chips (@strong{You probably have this)}:@* $ @strong{dd if=ich9fdnogbe_4m.bin of=libreboot.rom bs=1 count=4k conv=notrunc}@* NOTE: This shouldn't be necessary. Libreboot ROM images already contain a descriptor embedded inside the ROM images for GM45, generated by the ich9gen utility. It's only desirable to re-insert your own when changing the MAC address, which is unnecessary (actually impossible) on the R500, because on that laptop, as already stated, the NIC already has the correct MAC address burned in, along with along configuration data.
+
+Your libreboot.rom image is now ready to be flashed on the system. Refer back to @uref{../install/index.html#flashrom,../install/index.html#flashrom} for how to flash it.
+@menu
+* Write-protecting the flash chip::
+@end menu
+
+@node Write-protecting the flash chip
+@section Write-protecting the flash chip
+@anchor{#write-protecting-the-flash-chip}
+Look in @emph{resources/utilities/ich9deblob/src/descriptor/descriptor.c} for the following lines in the @emph{descriptorHostRegionsUnlocked} function:
+
+@verbatim
+ descriptorStruct.masterAccessSection.flMstr1.fdRegionWriteAccess = 0x1;
+ descriptorStruct.masterAccessSection.flMstr1.biosRegionWriteAccess = 0x1;
+ descriptorStruct.masterAccessSection.flMstr1.meRegionWriteAccess = 0x1;
+ descriptorStruct.masterAccessSection.flMstr1.gbeRegionWriteAccess = 0x1;
+ descriptorStruct.masterAccessSection.flMstr1.pdRegionWriteAccess = 0x1;
+@end verbatim
+
+Also look in @emph{resources/utilities/ich9deblob/src/ich9gen/mkdescriptor.c} for the following lines:
+
+@verbatim
+ descriptorStruct.masterAccessSection.flMstr1.fdRegionWriteAccess = 0x1; /* see ../descriptor/descriptor.c */
+ descriptorStruct.masterAccessSection.flMstr1.biosRegionWriteAccess = 0x1; /* see ../descriptor/descriptor.c */
+ descriptorStruct.masterAccessSection.flMstr1.meRegionWriteAccess = 0x1; /* see ../descriptor/descriptor.c */
+ descriptorStruct.masterAccessSection.flMstr1.gbeRegionWriteAccess = 0x1; /* see ../descriptor/descriptor.c */
+ descriptorStruct.masterAccessSection.flMstr1.pdRegionWriteAccess = 0x1; /* see ../descriptor/descriptor.c */
+@end verbatim
+
+NOTE: When you write-protect the flash chip, re-flashing is no longer possible unless you use dedicated external equipment, which also means disassembling the laptop. The same equipment can also be used to remove the write-protection later on, if you choose to do so. *Only* write-protect the chip if you have the right equipment for external flashing later on; for example, see @uref{../install/bbb_setup.html,../install/bbb_setup.html}.
+
+Change them all to 0x0, then re-compile ich9gen. After you have done that, follow the notes in @ref{#ich9gen,#ich9gen} to generate a new descriptor+gbe image and insert that into your ROM image, then flash it. The next time you boot, the flash chip will be read-only in software (hardware re-flashing will still work, which you will need for re-flashing the chip after write-protecting it, to clear the write protection or to flash yet another ROM image with write protection set in the descriptor).
+
+Flashrom will tell you that you can still forcefully re-flash, using @emph{-p internal:ich_spi_force=yes} but this won't actually work; it'll just brick your laptop.
+
+For external flashing guides, refer to @uref{../install/index.html,../install/index.html}.
+
+@node ICH9 deblob utility
+@chapter ICH9 deblob utility
+@anchor{#ich9-deblob-utility}
+@strong{This is no longer strictly necessary. Libreboot ROM images for GM45 systems now contain the 12KiB descriptor+gbe generated from ich9gen, by default.}
+
+This was the tool originally used to disable the ME on X200 (later adapted for other systems that use the GM45 chipset). @ref{#ich9gen,ich9gen} now supersedes it; ich9gen is better because it does not rely on dumping the factory.rom image (whereas, ich9deblob does).
+
+This is what you will use to generate the deblobbed descriptor+gbe regions for your libreboot ROM image.
+
+If you are working with libreboot_src (or git), you can find the source under resources/utilities/ich9deblob/ and will already be compiled if you ran @strong{./build module all} or @strong{./build module ich9deblob} from the main directory (./), otherwise you can build it like so:@* $ @strong{./build module ich9deblob}@* An executable file named @strong{ich9deblob} will now appear under resources/utilities/ich9deblob/
+
+If you are working with libreboot_util release archive, you can find the utility included, statically compiled (for i686 and x86_64 on GNU/Linux) under ./ich9deblob/.
+
+Place the factory.rom from your system (can be obtained using the external flashing guides for GM45 targets linked @uref{../install/index.html,../install/index.html}) in the directory where you have your ich9deblob executable, then run the tool:@* $ @strong{./ich9deblob}
+
+A 12kiB file named @strong{deblobbed_descriptor.bin} will now appear. @strong{Keep this and the factory.rom stored in a safe location!} The first 4KiB contains the descriptor data region for your system, and the next 8KiB contains the gbe region (config data for your gigabit NIC). These 2 regions could actually be separate files, but they are joined into 1 file in this case.
+
+A 4KiB file named @strong{deblobbed_4kdescriptor.bin} will alternatively appear, if no GbE region was detected inside the ROM image. This is usually the case, when a discrete NIC is used (eg Broadcom) instead of Intel. Only the Intel NICs need a GbE region in the flash chip.
+
+Assuming that your libreboot image is named @strong{libreboot.rom}, copy the @strong{deblobbed_descriptor.bin} file to where @strong{libreboot.rom} is located and then run:@* $ @strong{dd if=deblobbed_descriptor.bin of=libreboot.rom bs=1 count=12k conv=notrunc}
+
+Alternatively, if you got a the @strong{deblobbed_4kdescriptor.bin} file (no GbE defined), do this: $ @strong{dd if=deblobbed_4kdescriptor.bin of=libreboot.rom bs=1 count=4k conv=notrunc}
+
+The utility will also generate 4 additional files:
+
+@itemize
+@item
+mkdescriptor.c
+@item
+mkdescriptor.h
+@item
+mkgbe.c
+@item
+mkgbe.h
+@end itemize
+
+These are C source files that can re-generate the very same Gbe and Descriptor structs (from ich9deblob/ich9gen). To use these, place them in src/ich9gen/ in ich9deblob, then re-build. The newly built @strong{ich9gen} executable will be able to re-create the very same 12KiB file from scratch, based on the C structs, this time @strong{without} the need for a factory.rom dump!
+
+You should now have a @strong{libreboot.rom} image containing the correct 4K descriptor and 8K gbe regions, which will then be safe to flash. Refer back to @uref{../install/index.html#flashrom,../install/index.html#flashrom} for how to flash it.
+
+@node demefactory utility
+@chapter demefactory utility
+@anchor{#demefactory-utility}
+This takes a factory.rom dump and disables the ME/TPM, but leaves the region intact. It also sets all regions read-write.
+
+The ME interferes with flash read/write in flashrom, and the default descriptor locks some regions. The idea is that doing this will remove all of those restrictions.
+
+Simply run (with factory.rom in the same directory):@* $ @strong{./demefactory}
+
+It will generate a 4KiB descriptor file (only the descriptor, no GbE). Insert that into a factory.rom image (NOTE: do this on a copy of it. Keep the original factory.rom stored safely somewhere):@* $ @strong{dd if=demefactory_4kdescriptor.bin of=factory_nome.rom bs=1 count=4k conv=notrunc}
+
+TODO: test this.@* TODO: lenovobios (GM45 thinkpads) still write-protects parts of the flash. Modify the assembly code inside. Note: the factory.rom (BIOS region) from lenovobios is in a compressed format, which you have to extract. bios_extract upstream won't work, but the following was said in #coreboot on freenode IRC:
+
+@verbatim
+<roxfan> fchmmr: try bios_extract with ffv patch http://patchwork.coreboot.org/patch/3444/
+<roxfan> or https://github.com/coreboot/bios_extract/blob/master/phoenix_extract.py
+<roxfan> what are you looking for specifically, btw?
+
+0x74: 0x9fff03e0 PR0: Warning: 0x003e0000-0x01ffffff is read-only.
+0x84: 0x81ff81f8 PR4: Warning: 0x001f8000-0x001fffff is locked.
+@end verbatim
+
+Use-case: a factory.rom image modified in this way would theoretically have no flash protections whatsoever, making it easy to quickly switch between factory/libreboot in software, without ever having to disassemble and re-flash externally unless you brick the device.
+
+demefactory is part of the ich9deblob src, found at @emph{resources/utilities/ich9deblob/}
+
+The sections below are adapted from (mostly) IRC logs related to early development getting the ME removed on GM45. They are useful for background information. This could not have been done without sgsit's help.
+@menu
+* Early notes::
+* Flash chips::
+* Early development notes::
+* GBE gigabit ethernet region in SPI flash::
+* Flash descriptor region::
+* platform data partition in boot flash factoryrom / lenovo bios::
+@end menu
+
+@node Early notes
+@section Early notes
+@anchor{#early-notes}
+@itemize
+@item
+@uref{http://www.intel.co.uk/content/dam/doc/datasheet/io-controller-hub-10-family-datasheet.pdf,http://www.intel.co.uk/content/dam/doc/datasheet/io-controller-hub-10-family-datasheet.pdf} page 230 mentions about descriptor and non-descriptor mode (which wipes out gbe and ME/AMT).
+@item
+@textstrikeout{@strong{See reference to HDA_SDO (disable descriptor security)}} strap connected GPIO33 pin is it on ICH9-M (X200). HDA_SDO applies to later chipsets (series 6 or higher). Disabling descriptor security also disables the ethernet according to sgsit. sgsit's method involves use of 'soft straps' (see IRC logs below) instead of disabling the descriptor.
+@item
+@strong{and the location of GPIO33 on the x200s: (was an external link. Putting it here instead)} @uref{../resources/images/x200/gpio33_location.jpg,../resources/images/x200/gpio33_location.jpg} - it's above the number 7 on TP37 (which is above the big intel chip at the bottom)
+@item
+The ME datasheet may not be for the mobile chipsets but it doesn't vary that much. This one gives some detail and covers QM67 which is what the X201 uses: @uref{http://www.intel.co.uk/content/dam/www/public/us/en/documents/datasheets/6-chipset-c200-chipset-datasheet.pdf,http://www.intel.co.uk/content/dam/www/public/us/en/documents/datasheets/6-chipset-c200-chipset-datasheet.pdf}
+@end itemize
+
+@node Flash chips
+@section Flash chips
+@anchor{#flash-chips}
+@itemize
+@item
+Schematics for X200 laptop: @uref{http://pdf.datasheetarchive.com/indexerfiles/Datasheets-USER/DSAUPLD00006075.pdf,http://pdf.datasheetarchive.com/indexerfiles/Datasheets-USER/DSAUPLD00006075.pdf} @strong{@textstrikeout{- Page 20 and page 9 refer to SDA_HDO or SDA_HDOUT}} only on series 6 or higher chipsets. ICH9-M (X200) does it with a strap connected to GPIO33 pin (see IRC notes below)@* - According to page 29, the X200 can have any of the following flash chips:
+@itemize
+@item
+ATMEL AT26DF321-SU 72.26321.A01 - this is a 32Mb (4MiB) chip
+@item
+MXIC (Macronix?) MX25L3205DM2I-12G 72.25325.A01 - another 32Mb (4MiB) chip
+@item
+MXIC (Macronix?) MX25L6405DMI-12G 41R0820AA - this is a 64Mb (8MiB) chip
+@item
+Winbond W25X64VSFIG 41R0820BA - another 64Mb (8MiB) chip
+@end itemize
+
+sgsit says that the X200s with the 64Mb flash chips are (probably) the ones with AMT (alongside the ME), whereas the 32Mb chips contain only the ME.
+@item
+Schematics for X200s laptop: @uref{http://pdf.datasheetarchive.com/indexerfiles/Datasheets-USER/DSAUPLD00006104.pdf,http://pdf.datasheetarchive.com/indexerfiles/Datasheets-USER/DSAUPLD00006104.pdf}.
+@end itemize
+
+@node Early development notes
+@section Early development notes
+@anchor{#early-development-notes}
+
+@verbatim
+
+Start (hex) End (hex) Length (hex) Area Name
+----------- --------- ------------ ---------
+00000000 003FFFFF 00400000 Flash Image
+
+00000000 00000FFF 00001000 Descriptor Region
+00000004 0000000F 0000000C Descriptor Map
+00000010 0000001B 0000000C Component Section
+00000040 0000004F 00000010 Region Section
+00000060 0000006B 0000000C Master Access Section
+00000060 00000063 00000004 CPU/BIOS
+00000064 00000067 00000004 Manageability Engine (ME)
+00000068 0000006B 00000004 GbE LAN
+00000100 00000103 00000004 ICH Strap 0
+00000104 00000107 00000004 ICH Strap 1
+00000200 00000203 00000004 MCH Strap 0
+00000EFC 00000EFF 00000004 Descriptor Map 2
+00000ED0 00000EF7 00000028 ME VSCC Table
+00000ED0 00000ED7 00000008 Flash device 1
+00000ED8 00000EDF 00000008 Flash device 2
+00000EE0 00000EE7 00000008 Flash device 3
+00000EE8 00000EEF 00000008 Flash device 4
+00000EF0 00000EF7 00000008 Flash device 5
+00000F00 00000FFF 00000100 OEM Section
+00001000 001F5FFF 001F5000 ME Region
+001F6000 001F7FFF 00002000 GbE Region
+001F8000 001FFFFF 00008000 PDR Region
+00200000 003FFFFF 00200000 BIOS Region
+
+Start (hex) End (hex) Length (hex) Area Name
+----------- --------- ------------ ---------
+00000000 003FFFFF 00400000 Flash Image
+
+00000000 00000FFF 00001000 Descriptor Region
+00000004 0000000F 0000000C Descriptor Map
+00000010 0000001B 0000000C Component Section
+00000040 0000004F 00000010 Region Section
+00000060 0000006B 0000000C Master Access Section
+00000060 00000063 00000004 CPU/BIOS
+00000064 00000067 00000004 Manageability Engine (ME)
+00000068 0000006B 00000004 GbE LAN
+00000100 00000103 00000004 ICH Strap 0
+00000104 00000107 00000004 ICH Strap 1
+00000200 00000203 00000004 MCH Strap 0
+00000ED0 00000EF7 00000028 ME VSCC Table
+00000ED0 00000ED7 00000008 Flash device 1
+00000ED8 00000EDF 00000008 Flash device 2
+00000EE0 00000EE7 00000008 Flash device 3
+00000EE8 00000EEF 00000008 Flash device 4
+00000EF0 00000EF7 00000008 Flash device 5
+00000EFC 00000EFF 00000004 Descriptor Map 2
+00000F00 00000FFF 00000100 OEM Section
+00001000 00002FFF 00002000 GbE Region
+00003000 00202FFF 00200000 BIOS Region
+
+Build Settings
+--------------
+Flash Erase Size = 0x1000
+
+@end verbatim
+
+It's a utility called 'Flash Image Tool' for ME 4.x that was used for this. You drag a complete image into in and the utility decomposes the various components, allowing you to set soft straps.
+
+This tool is proprietary, for Windows only, but was used to deblob the X200. End justified means, and the utility is no longer needed since the ich9deblob utility (documented on this page) can now be used to create deblobbed descriptors.
+
+@node GBE gigabit ethernet region in SPI flash
+@section GBE (gigabit ethernet) region in SPI flash
+@anchor{#gbe-gigabit-ethernet-region-in-spi-flash}
+Of the 8K, about 95% is 0xFF. The data is the gbe region is fully documented in this public datasheet: @uref{http://www.intel.co.uk/content/dam/doc/application-note/i-o-controller-hub-9m-82567lf-lm-v-nvm-map-appl-note.pdf,http://www.intel.co.uk/content/dam/doc/application-note/i-o-controller-hub-9m-82567lf-lm-v-nvm-map-appl-note.pdf}
+
+The only actual content found was:
+
+@verbatim
+
+00 1F 1F 1F 1F 1F 00 08 FF FF 83 10 FF FF FF FF
+08 10 FF FF C3 10 EE 20 AA 17 F5 10 86 80 00 00
+01 0D 00 00 00 00 05 06 20 30 00 0A 00 00 8B 8D
+02 06 40 2B 43 00 00 00 F5 10 AD BA F5 10 BF 10
+AD BA CB 10 AD BA AD BA 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 01 00 40 28 12 07 40 FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF D9 F0
+20 60 1F 00 02 00 13 00 00 80 1D 00 FF 00 16 00
+DD CC 18 00 11 20 17 00 DD DD 18 00 12 20 17 00
+00 80 1D 00 00 00 1F
+@end verbatim
+
+The first part is the MAC address set to all 0x1F. It's repeated haly way through the 8K area, and the rest is all 0xFF. This is all documented in the datasheet.
+
+The GBe region starts at 0x20A000 bytes from the *end* of a factory image and is 0x2000 bytes long. In libreboot (deblobbed) the descriptor is set to put gbe directly after the initial 4K flash descriptor. So the first 4K of the ROM is the descriptor, and then the next 8K is the gbe region.
+@menu
+* GBE region change MAC address::
+@end menu
+
+@node GBE region change MAC address
+@subsection GBE region: change MAC address
+@anchor{#gbe-region-change-mac-address}
+According to the datasheet, it's supposed to add up to 0xBABA but can actually be others on the X200. @uref{https://communities.intel.com/community/wired/blog/2010/10/14/how-to-basic-eeprom-checksums,https://communities.intel.com/community/wired/blog/2010/10/14/how-to-basic-eeprom-checksums}
+
+@emph{"One of those engineers loves classic rock music, so they selected 0xBABA"}
+
+In honour of the song @emph{Baba O'Reilly} by @emph{The Who} apparently. We're not making this stuff up...
+
+0x3ABA, 0x34BA, 0x40BA and more have been observed in the main Gbe regions on the X200 factory.rom dumps. The checksums of the backup regions match BABA, however.
+
+By default, the X200 (as shipped by Lenovo) actually has an invalid main gbe checksum. The backup gbe region is correct, and is what these systems default to. Basically, you should do what you need on the *backup* gbe region, and then correct the main one by copying from the backup.
+
+Look at resources/utilities/ich9deblob/ich9deblob.c.
+
+@itemize
+@item
+Add the first 0x3F 16bit numbers (unsigned) of the GBe descriptor together (this includes the checksum value) and that has to add up to 0xBABA. In other words, the checksum is 0xBABA minus the total of the first 0x3E 16bit numbers (unsigned), ignoring any overflow.
+@end itemize
+
+@node Flash descriptor region
+@section Flash descriptor region
+@anchor{#flash-descriptor-region}
+@uref{http://www.intel.co.uk/content/dam/doc/datasheet/io-controller-hub-9-datasheet.pdf,http://www.intel.co.uk/content/dam/doc/datasheet/io-controller-hub-9-datasheet.pdf} from page 850 onwards. This explains everything that is in the flash descriptor, which can be used to understand what libreboot is doing about modifying it.
+
+How to deblob:
+
+@itemize
+@item
+patch the number of regions present in the descriptor from 5 - 3
+@item
+originally descriptor + bios + me + gbe + platform
+@item
+modified = descriptor + bios + gbe
+@item
+the next stage is to patch the part of the descriptor which defines the start and end point of each section
+@item
+then cut out the gbe region and insert it just after the region
+@item
+all this can be substantiated with public docs (ICH9 datasheet)
+@item
+the final part is flipping 2 bits. Halting the ME via 1 MCH soft strap and 1 ICH soft strap
+@item
+the part of the descriptor described there gives the base address and length of each region (bits 12:24 of each address)
+@item
+to disable a region, you set the base address to 0xFFF and the length to 0
+@item
+and you change the number of regions from 4 (zero based) to 2
+@end itemize
+
+There's an interesting parameter called 'ME Alternate disable', which allows the ME to only handle hardware errata in the southbridge, but disables any other functionality. This is similar to the 'ignition' in the 5 series and higher but using the standard firmware instead of a small 128K version. Useless for libreboot, though.
+
+To deblob GM45, you chop out the platform and ME regions and correct the addresses in flReg1-4. Then you set meDisable to 1 in ICHSTRAP0 and MCHSTRAP0.
+
+How to patch the descriptor from the factory.rom dump
+
+@itemize
+@item
+map the first 4k into the struct (minus the gbe region)
+@item
+set NR in FLMAP0 to 2 (from 4)
+@item
+adjust BASE and LIMIT in flReg1,2,3,4 to reflect the new location of each region (or remove them in the case of Platform and ME)
+@item
+set meDisable to 1/true in ICHSTRAP0 and MCHSTRAP0
+@item
+extract the 8k GBe region and append that to the end of the 4k descriptor
+@item
+output the 12k concatenated chunk
+@item
+Then it can be dd'd into the first 12K part of a coreboot image.
+@item
+the GBe region always starts 0x20A000 bytes from the end of the ROM
+@end itemize
+
+This means that libreboot's descriptor region will simply define the following regions:
+
+@itemize
+@item
+descriptor (4K)
+@item
+gbe (8K)
+@item
+bios (rest of flash chip. CBFS also set to occupy this whole size)
+@end itemize
+
+The data in the descriptor region is little endian, and it represents bits 24:12 of the address (bits 12-24, written this way since bit 24 is nearer to left than bit 12 in the binary representation).
+
+So, @emph{x << 12 = address}
+
+If it's in descriptor mode, then the first 4 bytes will be 5A A5 F0 0F.
+
+@node platform data partition in boot flash factoryrom / lenovo bios
+@section platform data partition in boot flash (factory.rom / lenovo bios)
+@anchor{#platform-data-partition-in-boot-flash-factory.rom-lenovo-bios}
+Basically useless for libreboot, since it appears to be a blob. Removing it didn't cause any issues in libreboot.
+
+This is a 32K region from the factory image. It could be data (non-functional) that the original Lenovo BIOS used, but we don't know.
+
+It has only a 448 byte fragment different from 0x00 or 0xFF.
+
+Copyright © 2014, 2015 Francis Rowe <info@@gluglug.org.uk>@* Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license can be found at @uref{../resources/licenses/gfdl-1.3.txt,gfdl-1.3.txt}
+
+Updated versions of the license (when available) can be found at @uref{https://www.gnu.org/licenses/licenses.html,https://www.gnu.org/licenses/licenses.html}
+
+UNLESS OTHERWISE SEPARATELY UNDERTAKEN BY THE LICENSOR, TO THE EXTENT POSSIBLE, THE LICENSOR OFFERS THE LICENSED MATERIAL AS-IS AND AS-AVAILABLE, AND MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND CONCERNING THE LICENSED MATERIAL, WHETHER EXPRESS, IMPLIED, STATUTORY, OR OTHER. THIS INCLUDES, WITHOUT LIMITATION, WARRANTIES OF TITLE, MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NON-INFRINGEMENT, ABSENCE OF LATENT OR OTHER DEFECTS, ACCURACY, OR THE PRESENCE OR ABSENCE OF ERRORS, WHETHER OR NOT KNOWN OR DISCOVERABLE. WHERE DISCLAIMERS OF WARRANTIES ARE NOT ALLOWED IN FULL OR IN PART, THIS DISCLAIMER MAY NOT APPLY TO YOU.
+
+TO THE EXTENT POSSIBLE, IN NO EVENT WILL THE LICENSOR BE LIABLE TO YOU ON ANY LEGAL THEORY (INCLUDING, WITHOUT LIMITATION, NEGLIGENCE) OR OTHERWISE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, CONSEQUENTIAL, PUNITIVE, EXEMPLARY, OR OTHER LOSSES, COSTS, EXPENSES, OR DAMAGES ARISING OUT OF THIS PUBLIC LICENSE OR USE OF THE LICENSED MATERIAL, EVEN IF THE LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH LOSSES, COSTS, EXPENSES, OR DAMAGES. WHERE A LIMITATION OF LIABILITY IS NOT ALLOWED IN FULL OR IN PART, THIS LIMITATION MAY NOT APPLY TO YOU.
+
+The disclaimer of warranties and limitation of liability provided above shall be interpreted in a manner that, to the extent possible, most closely approximates an absolute disclaimer and waiver of all liability.
+
+@bye
diff --git a/docs/src/hcl/index.texi b/docs/src/hcl/index.texi
new file mode 100644
index 0000000..b8558f8
--- /dev/null
+++ b/docs/src/hcl/index.texi
@@ -0,0 +1,543 @@
+\input texinfo
+@documentencoding UTF-8
+
+@ifnottex
+@paragraphindent 0
+@end ifnottex
+@titlepage
+@title Hardware compatibility list
+@end titlepage
+
+@node Top
+@top Hardware compatibility list
+
+@menu
+* Hardware compatibility list::
+@end menu
+
+@node Hardware compatibility list
+@chapter Hardware compatibility list
+@anchor{#hardware-compatibility-list}
+This sections relates to known hardware compatibility in libreboot.
+
+@itemize
+@item
+@ref{#supported_list,List of supported hardware}
+@itemize
+@item
+@ref{#supported_workstations_x86amd,Servers/workstations}
+@item
+@ref{#supported_laptops_arm,Laptops (ARM)}
+@item
+@ref{#supported_laptops_x86intel,Laptops (Intel, x86)}
+@end itemize
+
+@item
+@ref{#recommended_wifi,Recommended wifi chipsets}
+@end itemize
+
+@uref{../index.html,Back to previous index}.
+@menu
+* List of supported hardware::
+* Recommended wifi chipsets::
+* List of supported ThinkPad X60s::
+* List of supported ThinkPad X60 Tablets::
+* Supported T60 list::
+* ThinkPad T60 ATI GPU and ThinkPad T60 Intel GPU differences::
+* Information about the macbook11::
+* Information about the macbook21::
+@end menu
+
+@node List of supported hardware
+@section List of supported hardware
+@anchor{#list-of-supported-hardware}
+Libreboot supports the following systems in this release:
+@menu
+* Servers/workstations AMD x86::
+* Laptops ARM::
+* Laptops Intel x86::
+@end menu
+
+@node Servers/workstations AMD x86
+@subsection Servers/workstations (AMD, x86)
+@anchor{#serversworkstations-amd-x86}
+@itemize
+@item
+@uref{kfsn4-dre.html,ASUS KFSN4-DRE motherboard}
+@item
+@uref{kgpe-d16.html,ASUS KGPE-D16 motherboard}
+@end itemize
+
+@node Laptops ARM
+@subsection Laptops (ARM)
+@anchor{#laptops-arm}
+@itemize
+@item
+@uref{c201.html,ASUS Chromebook C201}
+@end itemize
+
+@node Laptops Intel x86
+@subsection Laptops (Intel, x86)
+@anchor{#laptops-intel-x86}
+@itemize
+@item
+@ref{#supported_x60_list,Lenovo ThinkPad X60/X60s}
+@item
+@ref{#supported_x60t_list,Lenovo ThinkPad X60 Tablet}
+@item
+@ref{#supported_t60_list,Lenovo ThinkPad T60} (there are exceptions. see link)
+@item
+@uref{x200.html,Lenovo ThinkPad X200}
+@item
+@uref{r400.html,Lenovo ThinkPad R400}
+@item
+@uref{r500.html,Lenovo ThinkPad R500}
+@item
+@uref{t400.html,Lenovo ThinkPad T400}
+@item
+@uref{t500.html,Lenovo ThinkPad T500}
+@item
+@ref{#macbook11,Apple MacBook1,1}
+@item
+@ref{#macbook21,Apple MacBook2,1}
+@end itemize
+
+'Supported' means that the build scripts know how to build ROM images for these systems, and that the systems have been tested (confirmed working). There may be exceptions; in other words, this is a list of 'officially' supported systems.
+
+It is also possible to build ROM images (from source) for other systems (and virtual systems, e.g. QEMU).
+
+@ref{#pagetop,Back to top of page}
+
+@node Recommended wifi chipsets
+@section Recommended wifi chipsets
+@anchor{#recommended-wifi-chipsets}
+The following are known to work well:
+
+@itemize
+@item
+@uref{http://h-node.org/search/results/en/1/search/wifi/ar9285,Atheros AR5B95} (chipset: Atheros AR9285); mini PCI-E. Most of these are half-height, so you will need a half>full height mini PCI express adapter/bracket.
+@item
+@uref{http://h-node.org/wifi/view/en/116/Atheros-Communications-Inc--AR928X-Wireless-Network-Adapter--PCI-Express---rev-01-,Atheros AR928X} chipset; mini PCI-E. Most of these are half-height, so you will need a half>full height mini PCI express adapter/bracket
+@item
+Unex DNUA-93F (chipset: @uref{http://h-node.org/search/results/en/1/search/wifi/ar9271,Atheros AR9271}); USB.
+@item
+Any of the chipsets listed at @uref{https://www.fsf.org/resources/hw/endorsement/respects-your-freedom,https://www.fsf.org/resources/hw/endorsement/respects-your-freedom}
+@item
+Any of the chipsets listed at @uref{http://h-node.org/wifi/catalogue/en/1/1/undef/undef/yes?,http://h-node.org/wifi/catalogue/en/1/1/undef/undef/yes?}
+@end itemize
+
+The following was mentioned (on IRC), but it's unknown to the libreboot project if these work with linux-libre kernel (TODO: test):
+
+@itemize
+@item
+ar5bhb116 ar9382 ABGN
+@item
+[0200]: Qualcomm Atheros AR242x / AR542x Wireless Network Adapter (PCI-Express) [168c:001c]
+@end itemize
+
+@ref{#pagetop,Back to top of page}
+
+@node List of supported ThinkPad X60s
+@section List of supported ThinkPad X60s
+@anchor{#list-of-supported-thinkpad-x60s}
+Native gpu initialization ('native graphics') which replaces the proprietary VGA Option ROM ('@uref{https://en.wikipedia.org/wiki/Video_BIOS,Video BIOS}' or 'VBIOS'), all known LCD panels are currently compatible:
+
+To find what LCD panel you have, see: @uref{../misc/index.html#get_edid_panelname,../misc/index.html#get_edid_panelname}.
+
+@itemize
+@item
+TMD-Toshiba LTD121ECHB: #
+@item
+CMO N121X5-L06: #
+@item
+Samsung LTN121XJ-L07: #
+@item
+BOE-Hydis HT121X01-101: #
+@end itemize
+
+You can remove an X61/X61s motherboard from the chassis and install an X60/X60s motherboard in it's place (for flashing libreboot). The chassis is mostly identical and the motherboards are the same shape/size.
+
+The X60 typically comes with an Intel wifi chipset which does not work at all without proprietary firmware, and while Lenovo BIOS is running the system will refuse to boot if you replace the card. Fortunately it is very easily replaced; just remove the card and install another one @strong{after} libreboot is installed. See @ref{#recommended_wifi,#recommended_wifi} for replacements.
+
+@ref{#pagetop,Back to top of page.}
+
+@node List of supported ThinkPad X60 Tablets
+@section List of supported ThinkPad X60 Tablets
+@anchor{#list-of-supported-thinkpad-x60-tablets}
+Native gpu initialization ('native graphics') which replaces the proprietary VGA Option ROM ('@uref{https://en.wikipedia.org/wiki/Video_BIOS,Video BIOS}' or 'VBIOS').
+
+To find what LCD panel you have, see: @uref{../misc/index.html#get_edid_panelname,../misc/index.html#get_edid_panelname}.
+
+There are 5 known LCD panels for the X60 Tablet:
+
+@itemize
+@item
+@strong{X60T XGA (1024x768):}
+@itemize
+@item
+BOE-Hydis HV121X03-100 (works)
+@item
+Samsung LTN121XP01 (does not work. blank screen)
+@item
+BOE-Hydis HT12X21-351 (does not work. blank screen)
+@end itemize
+
+@item
+@strong{X60T SXGA+ (1400x1050):}
+@itemize
+@item
+BOE-Hydis HV121P01-100 (works)
+@item
+BOE-Hydis HV121P01-101 (works)
+@end itemize
+
+@end itemize
+
+Most X60Ts only have digitizer (pen), but some have finger (touch) aswell as pen; finger/multitouch doesn't work, only digitizer (pen) does.
+
+You can remove an X61/X61s motherboard from the chassis and install an X60/X60s motherboard in its place (for flashing libreboot). The chassis is mostly identical and the motherboards are the same shape/size. @strong{It is unknown if the same applies between the X60 Tablet and the X61 Tablet}.
+
+The X60 Tablet typically comes with an Intel wifi chipset which does not work at all without proprietary firmware, and while Lenovo BIOS is running the system will refuse to boot if you replace the card. Fortunately it is very easily replaced; just remove the card and install another one @strong{after} libreboot is installed. See @ref{#recommended_wifi,#recommended_wifi} for replacements.
+
+A user with a X60T that has digitizer+finger support, reported that they could get finger input working. They used linuxwacom at git tag 0.25.99.2 and had the following in their xorg.conf:
+
+@verbatim
+# Now, for some reason (probably a bug in linuxwacom),
+# the 'Touch=on' directive gets reset to 'off'.
+# So you'll need to do
+# $ xsetwacom --set WTouch Touch on
+#
+# tested with linuxwacom git 42a42b2a8636abc9e105559e5dea467163499de7
+
+Section "Monitor"
+ Identifier "<default monitor>"
+ DisplaySize 245 184
+EndSection
+
+Section "Screen"
+ Identifier "Default Screen Section"
+ Monitor "<default monitor<"
+EndSection
+
+Section "InputDevice"
+ Identifier "WTouch"
+ Driver "wacom"
+ Option "Device" "/dev/ttyS0"
+# Option "DebugLevel" "12"
+ Option "BaudRate" "38400"
+ Option "Type" "touch"
+ Option "Touch" "on"
+ Option "Gesture" "on"
+ Option "ForceDevice" "ISDV4"
+# Option "KeepShape" "on"
+ Option "Mode" "Absolute"
+ Option "RawSample" "2"
+# Option "TPCButton" "off"
+ Option "TopX" "17"
+ Option "TopY" "53"
+ Option "BottomX" "961"
+ Option "BottomY" "985"
+EndSection
+
+Section "ServerLayout"
+ Identifier "Default Layout"
+ Screen "Default Screen Section"
+ InputDevice "WTouch" "SendCoreEvents"
+EndSection
+@end verbatim
+
+@ref{#pagetop,Back to top of page.}
+
+@node Supported T60 list
+@section Supported T60 list
+@anchor{#supported-t60-list}
+Native gpu initialization ('native graphics') which replaces the proprietary VGA Option ROM ('@uref{https://en.wikipedia.org/wiki/Video_BIOS,Video BIOS}' or 'VBIOS').
+
+To find what LCD panel you have, see: @uref{../misc/index.html#get_edid_panelname,../misc/index.html#get_edid_panelname}.
+
+@strong{Some T60s have ATI GPUs, and all T60P laptops have ATI GPUs These are incompatible! See @ref{#t60_ati_intel,#t60_ati_intel} for how to remedy this.}
+
+How to dump the EDID:@*
+
+Tested LCD panels: @strong{working(compatible)}
+
+@itemize
+@item
+TMD-Toshiba LTD141EN9B (14.1" 1400x1050) (FRU P/N 41W1478 recommended for the inverter board)
+@item
+Samsung LTN141P4-L02 (14.1" 1400x1050) (FRU P/N 41W1478 recommended for the inverter board)
+@item
+LG-Philips LP150E05-A2K1 (15.1" 1400x1050) (P/N 42T0078 FRU 42T0079 or P/N 41W1338 recommended for the inverter board)
+@item
+Samsung LTN150P4-L01 (15.1" 1400x1050) (P/N 42T0078 FRU 42T0079 or P/N 41W1338 recommended for the inverter board) (not a T60 screen afaik, but it works)
+@item
+BOE-Hydis HV150UX1-100 (15.1" 1600x1200) (P/N 42T0078 FRU 42T0079 or P/N 41W1338 recommended for the inverter board)
+@end itemize
+
+Tested LCD panels: @strong{not working yet (incompatible; see @uref{../future/index.html#lcd_i945_incompatibility,../future/index.html#lcd_i945_incompatibility})}
+
+@itemize
+@item
+Samsung LTN141XA-L01 (14.1" 1024x768)
+@item
+LG-Philips LP150X09 (15.1" 1024x768)
+@item
+Samsung LTN150XG (15.1" 1024x768)
+@item
+LG-Philips LP150E06-A5K4 (15.1" 1400x1050) (also, not an official T60 screen)
+@item
+Samsung LTN154X3-L0A (15.4" 1280x800)
+@item
+IDtech IAQX10N (15.1" 2048x1536) (no display in GRUB, display in GNU/Linux is temperamental) (P/N 42T0078 FRU 42T0079 or P/N 41W1338 recommended for the inverter board)
+@item
+IDtech N150U3-L01 (15.1" 1600x1200) (no display in GRUB, display in GNU/Linux works) (P/N 42T0078 FRU 42T0079 or P/N 41W1338 recommended for the inverter board)
+@end itemize
+
+@emph{The following LCD panels are @strong{UNTESTED}. If you have one of these panels then please submit a report!}:
+
+@itemize
+@item
+CMO(IDtech?) N141XC (14.1" 1024x768)
+@item
+BOE-Hydis HT14X14 (14.1" 1024x768)
+@item
+TMD-Toshiba LTD141ECMB (14.1" 1024x768)
+@item
+Boe-Hydis HT14P12 (14.1" 1400x1050) (FRU P/N 41W1478 recommended for the inverter board)
+@item
+CMO (IDtech?) 13N7068 (15.1" 1024x768)
+@item
+CMO (IDtech?) 13N7069 (15.1" 1024x768)
+@item
+BOE-Hydis HV150P01-100 (15.1" 1400x1050) (P/N 42T0078 FRU 42T0079 or P/N 41W1338 recommended for the inverter board)
+@item
+BOE-Hydis HV150UX1-102 (15.1" 1600x1200) (P/N 42T0078 FRU 42T0079 or P/N 41W1338 recommended for the inverter board)
+@item
+IDtech IAQX10S (15.1" 2048x1536) (P/N 42T0078 FRU 42T0079 or P/N 41W1338 recommended for the inverter board)
+@item
+Samsung LTN154P2-L05 (42X4641 42T0329) (15.4" 1680x1050)
+@item
+LG-Philips LP154W02-TL10 (13N7020 42T0423) (15.4" 1680x1050)
+@item
+LG-Philips LP154WU1-TLB1 (42T0361) (15.4" 1920x1200) @strong{(for T61p but it might work in T60. Unknown!)}
+@item
+Samsung LTN154U2-L05 (42T0408 42T0574) (15.4" 1920x1200) @strong{(for T61p but it might work in T60. Unknown!)}
+@end itemize
+
+It is unknown whether the 1680x1050 (15.4") and 1920x1200 (15.4") panels use a different inverter board than the 1280x800 panels.
+
+The T60 typically comes with an Intel wifi chipset which does not work at all without proprietary firmware, and while Lenovo BIOS is running the system will refuse to boot if you replace the card. Fortunately it is very easily replaced; just remove the card and install another one @strong{after} libreboot is installed. See @ref{#recommended_wifi,#recommended_wifi} for replacements.
+
+@ref{#pagetop,Back to top of page.}
+
+@node ThinkPad T60 ATI GPU and ThinkPad T60 Intel GPU differences
+@section ThinkPad T60 (ATI GPU) and ThinkPad T60 (Intel GPU) differences.
+@anchor{#thinkpad-t60-ati-gpu-and-thinkpad-t60-intel-gpu-differences.}
+If your T60 is a 14.1" or 15.1" model with an ATI GPU, it won't work with libreboot by default but you can replace the motherboard with another T60 motherboard that has an Intel GPU, and then libreboot should work.
+
+As far as I know, 14.1" (Intel GPU) and 15.1" (Intel GPU) T60 motherboards are the same, where 'spacers' are used on the 15.1" T60. In any case, it makes sense to find one that is guaranteed to fit in your chassis.
+
+There is also a 15.4" T60 with Intel GPU.
+
+Note: the T60@strong{p} laptops all have ATI graphics. The T60p laptops cannot be used with libreboot under any circumstances.
+
+The following T60 motherboard (see area highlighted in white) shows an empty space where the ATI GPU would be (this particular motherboard has an Intel GPU):@*@* @image{../resources/images/t60_dev/t60_unbrick,,,,jpg}
+
+The reason that the ATI GPU on T60 is unsupported is due to the VBIOS (Video BIOS) which is non-free. The VBIOS for the Intel GPU on X60/T60 has been reverse engineered, and replaced with Free Software and so will work in libreboot.
+
+The 'Video BIOS' is what initializes graphics.
+
+See: @uref{https://en.wikipedia.org/wiki/Video_BIOS,https://en.wikipedia.org/wiki/Video_BIOS}.@* In fact, lack of free VBIOS in general is a big problem in coreboot, and is one reason (among others) why many ports for coreboot are unsuitable for libreboot's purpose.
+
+Theoretically, the ThinkPad T60 with ATI GPU can work with libreboot and have ROM images compiled for it, however in practise it would not be usable as a laptop because there would be no visual display at all. That being said, such a configuration is acceptable for use in a 'headless' server setup (with serial and/or ssh console as the display).
+
+@ref{#pagetop,Back to top of page.}
+
+@node Information about the macbook11
+@section Information about the macbook1,1
+@anchor{#information-about-the-macbook11}
+There is an Apple laptop called the macbook1,1 from 2006 which uses the same i945 chipset as the ThinkPad X60/T60. A developer ported the @ref{#macbook21,MacBook2,1} to coreboot, the ROM images also work on the macbook1,1.
+
+You can refer to @ref{#macbook21,#macbook21} for most of this. Macbook2,1 laptops come with Core 2 Duo processors which support 64-bit operating systems (and 32-bit). The MacBook1,1 uses Core Duo processors (supports 32-bit OS but not 64-bit), and it is believed that this is the only difference.
+
+It is believed that all models are compatible, listed here:
+
+@itemize
+@item
+@uref{http://www.everymac.com/ultimate-mac-lookup/?search_keywords=MacBook1,1,http://www.everymac.com/ultimate-mac-lookup/?search_keywords=MacBook1,1}
+@end itemize
+
+@menu
+* Compatible models::
+@end menu
+
+@node Compatible models
+@subsection Compatible models
+@anchor{#compatible-models}
+Specifically (Order No. / Model No. / CPU):
+
+@itemize
+@item
+MA255LL/A / A1181 (EMC 2092) / Core Duo T2500 @strong{(tested - working)}
+@item
+MA254LL/A / A1181 (EMC 2092) / Core Duo T2400 (untested)
+@item
+MA472LL/A / A1181 (EMC 2092) / Core Duo T2500 (untested)
+@end itemize
+
+Also of interest: @uref{../git/index.html#config_macbook21,../git/index.html#config_macbook21}.
+
+Unbricking: @uref{https://www.ifixit.com/Device/MacBook_Core_2_Duo,this page shows disassembly guides} and mono's page (see @ref{#macbook21,#macbook21}) shows the location of the SPI flash chip on the motherboard. @uref{https://www.ifixit.com/Guide/MacBook+Core+2+Duo+PRAM+Battery+Replacement/529,How to remove the motherboard}.
+
+No method is yet known for flashing in GNU/Linux while the Apple firmware is running. You will need to disassemble the system and flash externally. Reading from flash seems to work. For external flashing, refer to @uref{../install/bbb_setup.html,../install/bbb_setup.html}.
+
+@ref{#pagetop,Back to top of page.}
+
+@node Information about the macbook21
+@section Information about the macbook2,1
+@anchor{#information-about-the-macbook21}
+There is an Apple laptop called the macbook2,1 from late 2006 or early 2007 that uses the same i945 chipset as the ThinkPad X60 and ThinkPad T60. A developer ported coreboot to their macbook2,1, and now libreboot can run on it.
+
+Mono Moosbart is the person who wrote the port for macbook2,1. Referenced below are copies (up to date at the time of writing, 20140630) of the pages that this person wrote when porting coreboot to the macbook2,1. They are included here in case the main site goes down for whatever reason, since they include a lot of useful information.
+
+Backups created using wget:@* @strong{$ wget -m -p -E -k -K -np http://macbook.donderklumpen.de/}@* @strong{$ wget -m -p -E -k -K -np http://macbook.donderklumpen.de/coreboot/}@* Use @strong{-e robots=off} if using this trick for other sites and the site restricts using robots.txt
+
+@strong{Links to wget backups (and the backups themselves) of Mono's pages (see above) removed temporarily. Mono has given me permission to distribute them, but I need to ask this person to tell me what license these works fall under first. Otherwise, the above URLs should be fine. NOTE TO SELF: REMOVE THIS WHEN DONE}
+@menu
+* Installing GNU/Linux distributions on Apple EFI firmware::
+* Information about coreboot::
+* coreboot wiki page::
+* Compatible models::
+@end menu
+
+@node Installing GNU/Linux distributions on Apple EFI firmware
+@subsection Installing GNU/Linux distributions (on Apple EFI firmware)
+@anchor{#installing-gnulinux-distributions-on-apple-efi-firmware}
+@itemize
+@item
+@ref{#,Parabola GNU/Linux installation on a macbook2,1 with Apple EFI firmware} (this is a copy of Mono's page, see above)
+@end itemize
+
+How to boot an ISO: burn it to a CD (like you would normally) and hold down the Alt/Control key while booting. The bootloader will detect the GNU/Linux CD as 'Windows' (because Apple doesn't think GNU/Linux exists). Install it like you normally would. When you boot up again, hold Alt/Control once more. The installation (on the HDD) will once again be seen as 'Windows'. (it's not actually Windows, but Apple likes to think that Apple and Microsoft are all that exist.) Now to install libreboot, follow @uref{../install/index.html#flashrom_macbook21,../install/index.html#flashrom_macbook21}.
+
+@node Information about coreboot
+@subsection Information about coreboot
+@anchor{#information-about-coreboot}
+@itemize
+@item
+@ref{#,Coreboot on the macbook2,1} (this is a copy of Mono's page, see above)
+@end itemize
+
+@node coreboot wiki page
+@subsection coreboot wiki page
+@anchor{#coreboot-wiki-page}
+@itemize
+@item
+@uref{http://www.coreboot.org/Board:apple/macbook21,http://www.coreboot.org/Board:apple/macbook21}
+@end itemize
+
+@node Compatible models
+@subsection Compatible models
+@anchor{#compatible-models-1}
+It is believed that all models are compatible, listed here:
+
+@itemize
+@item
+@uref{http://www.everymac.com/ultimate-mac-lookup/?search_keywords=MacBook2,1,http://www.everymac.com/ultimate-mac-lookup/?search_keywords=MacBook2,1}
+@end itemize
+
+Specifically (Order No. / Model No. / CPU):
+
+@itemize
+@item
+MA699LL/A / A1181 (EMC 2121) / Intel Core 2 Duo T5600 @strong{(tested - working)}
+@item
+MA701LL/A / A1181 (EMC 2121) / Intel Core 2 Duo T7200 @strong{(tested - working)}
+@item
+MB061LL/A / A1181 (EMC 2139) / Intel Core 2 Duo T7200 (untested)
+@item
+MA700LL/A / A1181 (EMC 2121) / Intel Core 2 Duo T7200 @strong{(tested - working)}
+@item
+MB063LL/A / A1181 (EMC 2139) / Intel Core 2 Duo T7400 (untested)
+@item
+MB062LL/A / A1181 (EMC 2139) / Intel Core 2 Duo T7400 @strong{(tested - working)}
+@end itemize
+
+Also of interest: @uref{../git/index.html#config_macbook21,../git/index.html#config_macbook21}.
+
+Unbricking: @uref{https://www.ifixit.com/Device/MacBook_Core_2_Duo,this page shows disassembly guides} and mono's page (see above) shows the location of the SPI flash chip on the motherboard. @uref{https://www.ifixit.com/Guide/MacBook+Core+2+Duo+PRAM+Battery+Replacement/529,How to remove the motherboard}.
+
+For external flashing, refer to @uref{../install/bbb_setup.html,../install/bbb_setup.html}.
+
+You need to replace OS X with GNU/Linux before flashing libreboot. (OSX won't run at all in libreboot).
+
+There are some issues with this system (compared to other computers that libreboot supports):
+
+This is an apple laptop, so it comes with OS X: it has an Apple keyboard, which means that certain keys are missing: insert, del, home, end, pgup, pgdown. There is also one mouse button only. Battery life is poor compared to X60/T60 (for now). It also has other issues: for example, the Apple logo on the back is a hole, exposing the backlight, which means that it glows. You should cover it up.
+
+The system does get a bit hotter compared to when running the original firmware. It is certainly hotter than an X60/T60. The heat issues have been partially fixed by the following patch (now merged in libreboot): @uref{http://review.coreboot.org/#/c/7923/,http://review.coreboot.org/#/c/7923/}.
+
+@strong{The MacBook2,1 comes with a webcam, which does not work without proprietary software. Also, webcams are a security risk; cover it up! Or remove it.}
+
+A user reported that they could get better response from the touchpad with the following in their xorg.conf:
+
+@verbatim
+Section "InputClass"
+ Identifier "Synaptics Touchpad"
+ Driver "synaptics"
+ MatchIsTouchpad "on"
+ MatchDevicePath "/dev/input/event*"
+ Driver "synaptics"
+# The next two values determine how much pressure one needs
+# for tapping, moving the cursor and other events.
+ Option "FingerLow" "10"
+ Option "FingerHigh" "15"
+# Do not emulate mouse buttons in the touchpad corners.
+ Option "RTCornerButton" "0"
+ Option "RBCornerButton" "0"
+ Option "LTCornerButton" "0"
+ Option "LBCornerButton" "0"
+# One finger tap = left-click
+ Option "TapButton1" "1"
+# Two fingers tap = right-click
+ Option "TapButton2" "3"
+# Three fingers tap = middle-mouse
+ Option "TapButton3" "2"
+# Try to not count the palm of the hand landing on the touchpad
+# as a tap. Not sure if helps.
+ Option "PalmDetect" "1"
+# The following modifies how long and how fast scrolling continues
+# after lifting the finger when scrolling
+ Option "CoastingSpeed" "20"
+ Option "CoastingFriction" "200"
+# Smaller number means that the finger has to travel less distance
+# for it to count as cursor movement. Larger number prevents cursor
+# shaking.
+ Option "HorizHysteresis" "10"
+ Option "VertHysteresis" "10"
+# Prevent two-finger scrolling. Very jerky movement
+ Option "HorizTwoFingerScroll" "0"
+ Option "VertTwoFingerScroll" "0"
+# Use edge scrolling
+ Option "HorizEdgeScroll" "1"
+ Option "VertEdgeScroll" "1"
+EndSection
+@end verbatim
+
+A user reported that the above is only for linux kernel 3.15 or lower. For newer kernels, the touchpad works fine out of the box, except middle tapping.
+
+A user submitted a utility to enable 3-finger tap on this laptop. It's available at @emph{resources/utilities/macbook21-three-finger-tap} in the libreboot git repository. The script is for GNOME, confirmed to work in Trisquel 7.
+
+@ref{#pagetop,Back to top of page.}
+
+Copyright © 2014, 2015 Francis Rowe <info@@gluglug.org.uk>@* Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license can be found at @uref{../resources/licenses/gfdl-1.3.txt,gfdl-1.3.txt}
+
+Updated versions of the license (when available) can be found at @uref{https://www.gnu.org/licenses/licenses.html,https://www.gnu.org/licenses/licenses.html}
+
+UNLESS OTHERWISE SEPARATELY UNDERTAKEN BY THE LICENSOR, TO THE EXTENT POSSIBLE, THE LICENSOR OFFERS THE LICENSED MATERIAL AS-IS AND AS-AVAILABLE, AND MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND CONCERNING THE LICENSED MATERIAL, WHETHER EXPRESS, IMPLIED, STATUTORY, OR OTHER. THIS INCLUDES, WITHOUT LIMITATION, WARRANTIES OF TITLE, MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NON-INFRINGEMENT, ABSENCE OF LATENT OR OTHER DEFECTS, ACCURACY, OR THE PRESENCE OR ABSENCE OF ERRORS, WHETHER OR NOT KNOWN OR DISCOVERABLE. WHERE DISCLAIMERS OF WARRANTIES ARE NOT ALLOWED IN FULL OR IN PART, THIS DISCLAIMER MAY NOT APPLY TO YOU.
+
+TO THE EXTENT POSSIBLE, IN NO EVENT WILL THE LICENSOR BE LIABLE TO YOU ON ANY LEGAL THEORY (INCLUDING, WITHOUT LIMITATION, NEGLIGENCE) OR OTHERWISE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, CONSEQUENTIAL, PUNITIVE, EXEMPLARY, OR OTHER LOSSES, COSTS, EXPENSES, OR DAMAGES ARISING OUT OF THIS PUBLIC LICENSE OR USE OF THE LICENSED MATERIAL, EVEN IF THE LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH LOSSES, COSTS, EXPENSES, OR DAMAGES. WHERE A LIMITATION OF LIABILITY IS NOT ALLOWED IN FULL OR IN PART, THIS LIMITATION MAY NOT APPLY TO YOU.
+
+The disclaimer of warranties and limitation of liability provided above shall be interpreted in a manner that, to the extent possible, most closely approximates an absolute disclaimer and waiver of all liability.
+
+@bye
diff --git a/docs/src/hcl/kfsn4-dre.texi b/docs/src/hcl/kfsn4-dre.texi
new file mode 100644
index 0000000..08876b2
--- /dev/null
+++ b/docs/src/hcl/kfsn4-dre.texi
@@ -0,0 +1,88 @@
+\input texinfo
+@documentencoding UTF-8
+
+@ifnottex
+@paragraphindent 0
+@end ifnottex
+@titlepage
+@title ASUS KFSN4-DRE server/workstation board
+@end titlepage
+
+@node Top
+@top ASUS KFSN4-DRE server/workstation board
+
+@menu
+* ASUS KFSN4-DRE server/workstation board::
+* Form factor::
+* Flash chips::
+* Native graphics initialization::
+* Memory::
+* Hex-core CPUs::
+* Current issues::
+* Other information::
+@end menu
+
+@node ASUS KFSN4-DRE server/workstation board
+@chapter ASUS KFSN4-DRE server/workstation board
+@anchor{#asus-kfsn4-dre-serverworkstation-board}
+This is a server board using AMD hardware (Fam10h). It can also be used for building a high-powered workstation. Powered by libreboot.
+
+@strong{NOTE: This board is unsupported in libreboot 20150518. To use it in libreboot, for now, you must build for it from source using the libreboot git repository.}
+
+Flashing instructions can be found at @uref{../install/index.html#flashrom,../install/index.html#flashrom}
+
+@uref{index.html,Back to previous index}.
+
+@node Form factor
+@chapter Form factor
+@anchor{#form-factor}
+These boards use the SSI EEB 3.61 form factor; make sure that your case supports this. This form factor is similar to E-ATX in that the size is identical, but the position of the screws are different.
+
+@node Flash chips
+@chapter Flash chips
+@anchor{#flash-chips}
+These boards use LPC flash (not SPI), in a PLCC socket. The default flash size 1MiB (8Mbits), and can be upgraded to 2MiB (16Mbits). SST49LF080A is the default that the board uses. SST49LF016C is an example of a 2MiB (16Mbits) chip, which might work. It is believed that 2MiB (16Mbits) is the maximum size available for the flash chip.
+
+@strong{DO NOT hot-swap the chip with your bare hands. Use a PLCC chip extractor. These can be found online. See @uref{http://www.coreboot.org/Developer_Manual/Tools#Chip_removal_tools,http://www.coreboot.org/Developer_Manual/Tools#Chip_removal_tools}}
+
+@node Native graphics initialization
+@chapter Native graphics initialization
+@anchor{#native-graphics-initialization}
+Native graphics initialization exists (XGI Z9s) for this board. Framebuffer- and text-mode both work. A serial port is also available.
+
+@node Memory
+@chapter Memory
+@anchor{#memory}
+DDR2 533/667 Registered ECC. 16 slots. Total capacity up to 64GiB.
+
+@node Hex-core CPUs
+@chapter Hex-core CPUs
+@anchor{#hex-core-cpus}
+PCB revision 1.05G is the best version of this board (the revision number will be printed on the board), because it can use dual hex-core CPUs (Opteron 2400/8400 series). Other revisions are believed to only support dual quad-core CPUs.
+
+@node Current issues
+@chapter Current issues
+@anchor{#current-issues}
+@itemize
+@item
+There seems to be a 30 second bootblock delay (observed by tpearson); the system otherwise boots and works as expected. See @uref{../resources/text/kfsn4-dre/bootlog.txt,kfsn4-dre/bootlog.txt} - this uses the 'simple' bootblock, while tpearson uses the 'normal' bootblock, which tpearson suspects may be a possible cause. This person says that they will look into it. @uref{http://review.coreboot.org/gitweb?p=board-status.git;a=blob;f=asus/kfsn4-dre/4.0-10101-g039edeb/2015-06-27T03:59:16Z/config.txt;h=4742905c185a93fbda8eb14322dd82c70641aef0;hb=055f5df4e000a97453dfad6c91c2d06ea22b8545,This config} doesn't have the issue.
+@item
+Text-mode is a bit jittery (but still usable). (the jitter disappears if using KMS, once the kernel starts. The jitter will remain, if booting the kernel in text-mode).
+@end itemize
+
+@node Other information
+@chapter Other information
+@anchor{#other-information}
+@uref{ftp://ftp.sgi.com/public/Technical%20Support/Pdf%20files/Asus/kfsn4-dre.pdf,specifications}
+
+Copyright © 2015 Francis Rowe <info@@gluglug.org.uk>@* Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license can be found at @uref{../resources/licenses/gfdl-1.3.txt,gfdl-1.3.txt}
+
+Updated versions of the license (when available) can be found at @uref{https://www.gnu.org/licenses/licenses.html,https://www.gnu.org/licenses/licenses.html}
+
+UNLESS OTHERWISE SEPARATELY UNDERTAKEN BY THE LICENSOR, TO THE EXTENT POSSIBLE, THE LICENSOR OFFERS THE LICENSED MATERIAL AS-IS AND AS-AVAILABLE, AND MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND CONCERNING THE LICENSED MATERIAL, WHETHER EXPRESS, IMPLIED, STATUTORY, OR OTHER. THIS INCLUDES, WITHOUT LIMITATION, WARRANTIES OF TITLE, MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NON-INFRINGEMENT, ABSENCE OF LATENT OR OTHER DEFECTS, ACCURACY, OR THE PRESENCE OR ABSENCE OF ERRORS, WHETHER OR NOT KNOWN OR DISCOVERABLE. WHERE DISCLAIMERS OF WARRANTIES ARE NOT ALLOWED IN FULL OR IN PART, THIS DISCLAIMER MAY NOT APPLY TO YOU.
+
+TO THE EXTENT POSSIBLE, IN NO EVENT WILL THE LICENSOR BE LIABLE TO YOU ON ANY LEGAL THEORY (INCLUDING, WITHOUT LIMITATION, NEGLIGENCE) OR OTHERWISE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, CONSEQUENTIAL, PUNITIVE, EXEMPLARY, OR OTHER LOSSES, COSTS, EXPENSES, OR DAMAGES ARISING OUT OF THIS PUBLIC LICENSE OR USE OF THE LICENSED MATERIAL, EVEN IF THE LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH LOSSES, COSTS, EXPENSES, OR DAMAGES. WHERE A LIMITATION OF LIABILITY IS NOT ALLOWED IN FULL OR IN PART, THIS LIMITATION MAY NOT APPLY TO YOU.
+
+The disclaimer of warranties and limitation of liability provided above shall be interpreted in a manner that, to the extent possible, most closely approximates an absolute disclaimer and waiver of all liability.
+
+@bye
diff --git a/docs/src/hcl/kgpe-d16.texi b/docs/src/hcl/kgpe-d16.texi
new file mode 100644
index 0000000..14782f1
--- /dev/null
+++ b/docs/src/hcl/kgpe-d16.texi
@@ -0,0 +1,326 @@
+\input texinfo
+@documentencoding UTF-8
+
+@ifnottex
+@paragraphindent 0
+@end ifnottex
+@titlepage
+@title ASUS KGPE-D16 server/workstation board
+@end titlepage
+
+@node Top
+@top ASUS KGPE-D16 server/workstation board
+
+@menu
+* ASUS KGPE-D16 server/workstation board::
+* Board status compatibility::
+* Form factor::
+* IPMI iKVM module add-on::
+* Flash chips::
+* Native graphics initialization::
+* Current issues::
+@end menu
+
+@node ASUS KGPE-D16 server/workstation board
+@chapter ASUS KGPE-D16 server/workstation board
+@anchor{#asus-kgpe-d16-serverworkstation-board}
+This is a server board using AMD hardware (Fam10h @strong{and Fam15h} CPUs available). It can also be used for building a high-powered workstation. Powered by libreboot. The coreboot port was done by Timothy Pearson of @uref{https://raptorengineeringinc.com/,Raptor Engineering Inc.} and, working with Timothy (and sponsoring the work) merged into libreboot.
+
+@strong{NOTE: This board is unsupported in libreboot 20150518. To use it in libreboot, for now, you must build for it from source using the libreboot git repository.}
+
+Flashing instructions can be found at @uref{../install/index.html#flashrom,../install/index.html#flashrom} - note that external flashing is required (e.g. BBB), if the proprietary (ASUS) firmware is currently installed. If you already have libreboot, by default it is possible to re-flash using software running in GNU/Linux on the KGPE-D16, without using external hardware.
+
+@uref{index.html,Back to previous index}.
+
+@node Board status compatibility
+@chapter Board status (compatibility)
+@anchor{#board-status-compatibility}
+See @uref{https://raptorengineeringinc.com/coreboot/kgpe-d16-status.php,https://raptorengineeringinc.com/coreboot/kgpe-d16-status.php}.
+
+@node Form factor
+@chapter Form factor
+@anchor{#form-factor}
+These boards use the SSI EEB 3.61 form factor; make sure that your case supports this. This form factor is similar to E-ATX in that the size is identical, but the position of the screws are different.
+
+@node IPMI iKVM module add-on
+@chapter IPMI iKVM module add-on
+@anchor{#ipmi-ikvm-module-add-on}
+Don't use it. It uses proprietary firmware and adds a backdoor (remote out-of-band management chip, similar to the @uref{http://libreboot.org/faq/#intelme,Intel Management Engine}. Fortunately, the firmware is unsigned (possibly to replace) and physically separate from the mainboard since it's on the add-on module, which you don't have to install.
+
+@node Flash chips
+@chapter Flash chips
+@anchor{#flash-chips}
+2MiB flash chips are included by default, on these boards. It's on a P-DIP 8 slot (SPI chip). The flash chip can be upgraded to higher sizes: 4MiB, 8MiB or 16MiB. With at least 8MiB, you could feasibly fit a compressed linux+initramfs image (BusyBox+Linux system) into CBFS and boot that, loading it into memory.
+
+Libreboot has configs for 2, 4, 8 and 16 MiB flash chip sizes (default flash chip is 2MiB).
+
+@strong{DO NOT hot-swap the chip with your bare hands. Use a P-DIP 8 chip extractor. These can be found online. See @uref{http://www.coreboot.org/Developer_Manual/Tools#Chip_removal_tools,http://www.coreboot.org/Developer_Manual/Tools#Chip_removal_tools}}
+
+@node Native graphics initialization
+@chapter Native graphics initialization
+@anchor{#native-graphics-initialization}
+Only text-mode is known to work, but linux(kernel) can initialize the framebuffer display (if it has KMS - kernel mode setting).
+
+@node Current issues
+@chapter Current issues
+@anchor{#current-issues}
+@itemize
+@item
+RDIMM memory modules untested, according to tpearson (they'll probably work)
+@item
+LRDIMM memory modules are currently incompatible
+@item
+SAS (via PIKE 2008 module) requires non-free option ROM (and SeaBIOS) to boot from it (theoretically possible to replace, but you can put a kernel in CBFS or on SATA and use that to boot GNU, which can be on a SAS drive. The linux kernel can use those SAS drives (via PIKE module) without an option ROM).
+@item
+IPMI iKVM module (optional add-on card) uses proprietary firmware. Since it's for remote out-of-band management, it's theoretically a backdoor similar to the Intel Management Engine. Fortunately, unlike the ME, this firmware is unsigned which means that a free replacement is theoretically possible. For now, the libreboot project recommends not installing the module. @uref{https://github.com/facebook/openbmc,This project} might be interesting to derive from, for those who want to work on a free replacement. In practise, out-of-band management isn't very useful anyway (or at the very least, it's not a major inconvenience to not have it).
+@item
+Graphics: only text-mode works. See @ref{#graphics,#graphics}
+@end itemize
+
+@menu
+* Hardware specifications::
+@end menu
+
+@node Hardware specifications
+@section Hardware specifications
+@anchor{#hardware-specifications}
+The information here is adapted, from the ASUS website.
+@menu
+* Processor / system bus::
+* Core logic::
+* Memory compatibility with libreboot::
+* Expansion slots::
+* Form factor::
+* ASUS features::
+* Storage::
+* Networking::
+* Graphics::
+* On board I/O::
+* Back I/O ports::
+* Environment::
+* Monitoring::
+* Note::
+@end menu
+
+@node Processor / system bus
+@subsection Processor / system bus
+@anchor{#processor-system-bus}
+@itemize
+@item
+2 CPU sockets (G34 compatible)
+@item
+HyperTransport™ Technology 3.0
+@item
+CPUs supported (not provided by Minifree, yet):
+@itemize
+@item
+AMD Opteron 6100 series (Fam10h. No IOMMU support. @strong{Not} recommended)
+@item
+AMD Opteron 6200 series (Fam15h, with full IOMMU support in libreboot)
+@item
+AMD Opteron 6300 series (Fam15h, with full IOMMU support in libreboot. @strong{Recommended}
+@end itemize
+
+@item
+6.4 GT/s per link (triple link)
+@end itemize
+
+@node Core logic
+@subsection Core logic
+@anchor{#core-logic}
+@itemize
+@item
+AMD SR5690
+@item
+AMD SP5100
+@end itemize
+
+@node Memory compatibility with libreboot
+@subsection Memory compatibility (with libreboot)
+@anchor{#memory-compatibility-with-libreboot}
+@itemize
+@item
+@strong{Total Slots:} 16 (4-channel per CPU, 8 DIMM per CPU), ECC
+@item
+@strong{Capacity:} Maximum up to 256GB RDIMM
+@item
+@strong{Memory Type that is compatible:}
+@itemize
+@item
+DDR3 1600/1333/1066/800 UDIMM*
+@item
+DDR3 1600/1333/1066/800 RDIMM*
+@end itemize
+
+@item
+@strong{Compatible sizes per memory module:}
+@itemize
+@item
+16GB, 8GB, 4GB, 3GB, 2GB, 1GB RDIMM
+@item
+8GB, 4GB, 2GB, 1GB UDIMM
+@end itemize
+
+@end itemize
+
+@node Expansion slots
+@subsection Expansion slots
+@anchor{#expansion-slots}
+@itemize
+@item
+@strong{Total slot:} 6
+@item
+@strong{Slot Location 1:} PCI 32bit/33MHz
+@item
+@strong{Slot Location 2:} PCI-E x16 (Gen2 X8 Link)
+@item
+@strong{Slot Location 3:} PCI-E x16 (Gen2 X16 Link), Auto switch to x8 link if slot 2 is occupied
+@item
+@strong{Slot Location 4:} PCI-E x8 (Gen2 X4 Link)
+@item
+@strong{Slot Location 5:} PCI-E x16 (Gen2 X16 Link)
+@item
+@strong{Slot Location 6:} PCI-E x16 (Gen2 X16 Link), Auto turn off if slot 5 is occupied, For 1U FH/FL Card, MIO supported
+@item
+@strong{Additional Slot 1:} PIKE slot (for SAS drives. See notes above)
+@item
+Follow SSI Location#
+@end itemize
+
+@node Form factor
+@subsection Form factor
+@anchor{#form-factor-1}
+@itemize
+@item
+SSI EEB 3.61 (12"x13")
+@end itemize
+
+@node ASUS features
+@subsection ASUS features
+@anchor{#asus-features}
+@itemize
+@item
+Fan Speed Control
+@item
+Rack Ready (Rack and Pedestal dual use)
+@end itemize
+
+@node Storage
+@subsection Storage
+@anchor{#storage}
+@itemize
+@item
+@strong{SATA controller:}
+@itemize
+@item
+AMD SP5100
+@item
+6 x SATA2 300MB/s
+@end itemize
+
+@item
+@strong{SAS/SATA Controller:}
+@itemize
+@item
+ASUS PIKE2008 3Gbps 8-port SAS card included
+@end itemize
+
+@end itemize
+
+@node Networking
+@subsection Networking
+@anchor{#networking}
+@itemize
+@item
+2 x Intel® 82574L + 1 x Mgmt LAN
+@end itemize
+
+@node Graphics
+@subsection Graphics
+@anchor{#graphics}
+@itemize
+@item
+Aspeed AST2050 with 8MB VRAM
+@end itemize
+
+@node On board I/O
+@subsection On board I/O
+@anchor{#on-board-io}
+@itemize
+@item
+1 x PSU Power Connector (24-pin SSI power connector + 8-pin SSI 12V + 8-pin SSI 12V power connector)
+@item
+1 x Management Connector , Onboard socket for management card
+@item
+3 x USB pin header , Up to 6 Devices
+@item
+1 x Internal A Type USB Port
+@item
+8 x Fan Header , 4pin (3pin/4pin fan dual support)
+@item
+2 x SMBus
+@item
+1 x Serial Port Header
+@item
+1 x TPM header
+@item
+1 x PS/2 KB/MS port
+@end itemize
+
+@node Back I/O ports
+@subsection Back I/O ports
+@anchor{#back-io-ports}
+@itemize
+@item
+1 x External Serial Port
+@item
+2 x External USB Port
+@item
+1 x VGA Port
+@item
+2 x RJ-45
+@item
+1 x PS/2 KB/Mouse
+@end itemize
+
+@node Environment
+@subsection Environment
+@anchor{#environment}
+@itemize
+@item
+@strong{Operation temperature:} 10C ~ 35C
+@item
+@strong{Non operation temperature:} -40C ~ 70C
+@item
+@strong{Non operation humidity:} 20% ~ 90% ( Non condensing)
+@end itemize
+
+@node Monitoring
+@subsection Monitoring
+@anchor{#monitoring}
+@itemize
+@item
+CPU temperatures
+@item
+Fan speed (RPM)
+@end itemize
+
+@node Note
+@subsection Note:
+@anchor{#note}
+@itemize
+@item
+* DDR3 1600 can only be supported with AMD Opteron 6300/6200 series processor
+@end itemize
+
+Copyright © 2015 Francis Rowe <info@@gluglug.org.uk>@* Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license can be found at @uref{../resources/licenses/gfdl-1.3.txt,gfdl-1.3.txt}
+
+Updated versions of the license (when available) can be found at @uref{https://www.gnu.org/licenses/licenses.html,https://www.gnu.org/licenses/licenses.html}
+
+UNLESS OTHERWISE SEPARATELY UNDERTAKEN BY THE LICENSOR, TO THE EXTENT POSSIBLE, THE LICENSOR OFFERS THE LICENSED MATERIAL AS-IS AND AS-AVAILABLE, AND MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND CONCERNING THE LICENSED MATERIAL, WHETHER EXPRESS, IMPLIED, STATUTORY, OR OTHER. THIS INCLUDES, WITHOUT LIMITATION, WARRANTIES OF TITLE, MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NON-INFRINGEMENT, ABSENCE OF LATENT OR OTHER DEFECTS, ACCURACY, OR THE PRESENCE OR ABSENCE OF ERRORS, WHETHER OR NOT KNOWN OR DISCOVERABLE. WHERE DISCLAIMERS OF WARRANTIES ARE NOT ALLOWED IN FULL OR IN PART, THIS DISCLAIMER MAY NOT APPLY TO YOU.
+
+TO THE EXTENT POSSIBLE, IN NO EVENT WILL THE LICENSOR BE LIABLE TO YOU ON ANY LEGAL THEORY (INCLUDING, WITHOUT LIMITATION, NEGLIGENCE) OR OTHERWISE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, CONSEQUENTIAL, PUNITIVE, EXEMPLARY, OR OTHER LOSSES, COSTS, EXPENSES, OR DAMAGES ARISING OUT OF THIS PUBLIC LICENSE OR USE OF THE LICENSED MATERIAL, EVEN IF THE LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH LOSSES, COSTS, EXPENSES, OR DAMAGES. WHERE A LIMITATION OF LIABILITY IS NOT ALLOWED IN FULL OR IN PART, THIS LIMITATION MAY NOT APPLY TO YOU.
+
+The disclaimer of warranties and limitation of liability provided above shall be interpreted in a manner that, to the extent possible, most closely approximates an absolute disclaimer and waiver of all liability.
+
+@bye
diff --git a/docs/src/hcl/r400.texi b/docs/src/hcl/r400.texi
new file mode 100644
index 0000000..73332ea
--- /dev/null
+++ b/docs/src/hcl/r400.texi
@@ -0,0 +1,70 @@
+\input texinfo
+@documentencoding UTF-8
+
+@ifnottex
+@paragraphindent 0
+@end ifnottex
+@titlepage
+@title ThinkPad R400
+@end titlepage
+
+@node Top
+@top ThinkPad R400
+
+@menu
+* ThinkPad R400::
+* LCD compatibly::
+@end menu
+
+@node ThinkPad R400
+@chapter ThinkPad R400
+@anchor{#thinkpad-r400}
+It is believed that all or most R400 laptops are compatible. See notes about @uref{../install/r400_external.html#cpu_compatibility,CPU compatibility} for potential incompatibilities.
+
+There are two possible flash chip sizes for the R400: 4MiB (32Mbit) or 8MiB (64Mbit). This can be identified by the type of flash chip below the palmrest: 4MiB is SOIC-8, 8MiB is SOIC-16.
+
+@strong{The R400 laptops come with the ME (and sometimes AMT in addition) before flashing libreboot. Libreboot disables and removes it by using a modified descriptor: see @uref{gm45_remove_me.html,gm45_remove_me.html}} (contains notes, plus instructions)
+
+Flashing instructions can be found at @uref{../install/index.html#flashrom,../install/index.html#flashrom}
+
+@uref{index.html,Back to previous index}.
+@menu
+* Compatibility without blobs::
+@end menu
+
+@node Compatibility without blobs
+@section Compatibility (without blobs)
+@anchor{#compatibility-without-blobs}
+@menu
+* Hardware virtualization vt-x::
+@end menu
+
+@node Hardware virtualization vt-x
+@subsection Hardware virtualization (vt-x)
+@anchor{#hardware-virtualization-vt-x}
+The R400, when run without CPU microcode updates in coreboot, currently kernel panics if running QEMU with vt-x enabled on 2 cores for the guest. With a single core enabled for the guest, the guest panics (but the host is fine). Working around this in QEMU might be possible; if not, software virtualization should work fine (it's just slower).
+
+On GM45 hardware (with libreboot), make sure that the @emph{kvm} and @emph{kvm_intel} kernel modules are not loaded, when using QEMU.
+
+The following errata datasheet from Intel might help with investigation: @uref{http://download.intel.com/design/mobile/specupdt/320121.pdf,http://download.intel.com/design/mobile/specupdt/320121.pdf}
+
+The R400 is almost identical to the X200, code-wise. See @uref{x200.html,x200.html}.
+
+TODO: put hardware register logs here like on the @uref{x200.html,X200} and @uref{t400.html,T400} page.
+
+@node LCD compatibly
+@chapter LCD compatibly
+@anchor{#lcd-compatibly}
+Not all LCD panels are compatible yet. See @uref{gm45_lcd.html,gm45_lcd.html}.
+
+Copyright © 2014, 2015 Francis Rowe <info@@gluglug.org.uk>@* Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license can be found at @uref{../resources/licenses/gfdl-1.3.txt,gfdl-1.3.txt}
+
+Updated versions of the license (when available) can be found at @uref{https://www.gnu.org/licenses/licenses.html,https://www.gnu.org/licenses/licenses.html}
+
+UNLESS OTHERWISE SEPARATELY UNDERTAKEN BY THE LICENSOR, TO THE EXTENT POSSIBLE, THE LICENSOR OFFERS THE LICENSED MATERIAL AS-IS AND AS-AVAILABLE, AND MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND CONCERNING THE LICENSED MATERIAL, WHETHER EXPRESS, IMPLIED, STATUTORY, OR OTHER. THIS INCLUDES, WITHOUT LIMITATION, WARRANTIES OF TITLE, MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NON-INFRINGEMENT, ABSENCE OF LATENT OR OTHER DEFECTS, ACCURACY, OR THE PRESENCE OR ABSENCE OF ERRORS, WHETHER OR NOT KNOWN OR DISCOVERABLE. WHERE DISCLAIMERS OF WARRANTIES ARE NOT ALLOWED IN FULL OR IN PART, THIS DISCLAIMER MAY NOT APPLY TO YOU.
+
+TO THE EXTENT POSSIBLE, IN NO EVENT WILL THE LICENSOR BE LIABLE TO YOU ON ANY LEGAL THEORY (INCLUDING, WITHOUT LIMITATION, NEGLIGENCE) OR OTHERWISE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, CONSEQUENTIAL, PUNITIVE, EXEMPLARY, OR OTHER LOSSES, COSTS, EXPENSES, OR DAMAGES ARISING OUT OF THIS PUBLIC LICENSE OR USE OF THE LICENSED MATERIAL, EVEN IF THE LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH LOSSES, COSTS, EXPENSES, OR DAMAGES. WHERE A LIMITATION OF LIABILITY IS NOT ALLOWED IN FULL OR IN PART, THIS LIMITATION MAY NOT APPLY TO YOU.
+
+The disclaimer of warranties and limitation of liability provided above shall be interpreted in a manner that, to the extent possible, most closely approximates an absolute disclaimer and waiver of all liability.
+
+@bye
diff --git a/docs/src/hcl/r500.texi b/docs/src/hcl/r500.texi
new file mode 100644
index 0000000..f8bd10a
--- /dev/null
+++ b/docs/src/hcl/r500.texi
@@ -0,0 +1,190 @@
+\input texinfo
+@documentencoding UTF-8
+
+@ifnottex
+@paragraphindent 0
+@end ifnottex
+@titlepage
+@title ThinkPad R500
+@end titlepage
+
+@node Top
+@top ThinkPad R500
+
+@menu
+* ThinkPad R500::
+* LCD compatibly::
+* Issues::
+* Descriptor differences::
+* No Gbe region!::
+@end menu
+
+@node ThinkPad R500
+@chapter ThinkPad R500
+@anchor{#thinkpad-r500}
+It is believed that all or most R500 laptops are compatible. See notes about @uref{../install/r500_external.html#cpu_compatibility,CPU compatibility} for potential incompatibilities.
+
+There are two possible flash chip sizes for the R500: 4MiB (32Mbit) or 8MiB (64Mbit). This can be identified by the type of flash chip below the palmrest: 4MiB is SOIC-8, 8MiB is SOIC-16. @strong{NOTE: this paragraph is being treated with contempt. When an R500 was disassembled, it didn't look like there was an extra place for SOIC-16. It's highly likely that these laptops only have SOIC-8 (4MiB) flash chips. For now, libreboot will distribute 8MiB images just in case. If it is found later on that no 8MiB (SOIC-16) chips exist on the R500, then libreboot will cease to distribute 8MiB ROM images for this laptop. It is only said that the R500 has 4MiB or 8MiB, for now, since this is the case on other GM45 thinkpads that are supported in libreboot.}
+
+@strong{The R400 laptops come with the ME (and sometimes AMT in addition) before flashing libreboot. Libreboot disables and removes it by using a modified descriptor: see @uref{gm45_remove_me.html,gm45_remove_me.html}} (contains notes, plus instructions)
+
+Flashing instructions can be found at @uref{../install/index.html#flashrom,../install/index.html#flashrom}
+
+@strong{NOTE: This board is unsupported in libreboot 20150518. To use it in libreboot, for now, you must build for it from source using the libreboot git repository.}
+
+@uref{index.html,Back to previous index}.
+@menu
+* Compatibility without blobs::
+@end menu
+
+@node Compatibility without blobs
+@section Compatibility (without blobs)
+@anchor{#compatibility-without-blobs}
+@menu
+* Hardware virtualization vt-x::
+@end menu
+
+@node Hardware virtualization vt-x
+@subsection Hardware virtualization (vt-x)
+@anchor{#hardware-virtualization-vt-x}
+The R400, when run without CPU microcode updates in coreboot, currently kernel panics if running QEMU with vt-x enabled on 2 cores for the guest. With a single core enabled for the guest, the guest panics (but the host is fine). Working around this in QEMU might be possible; if not, software virtualization should work fine (it's just slower).
+
+On GM45 hardware (with libreboot), make sure that the @emph{kvm} and @emph{kvm_intel} kernel modules are not loaded, when using QEMU.
+
+The following errata datasheet from Intel might help with investigation: @uref{http://download.intel.com/design/mobile/specupdt/320121.pdf,http://download.intel.com/design/mobile/specupdt/320121.pdf}
+
+@node LCD compatibly
+@chapter LCD compatibly
+@anchor{#lcd-compatibly}
+Not all LCD panels are known to be compatible yet. See @uref{gm45_lcd.html,gm45_lcd.html}.
+
+The R500 is almost identical to the X200, code-wise, but there are some hardware differences. See @uref{x200.html,x200.html}.
+@menu
+* Hardware register dumps::
+@end menu
+
+@node Hardware register dumps
+@section Hardware register dumps
+@anchor{#hardware-register-dumps}
+The coreboot wiki @uref{http://www.coreboot.org/Motherboard_Porting_Guide,shows} how to collect various logs useful in porting to new boards. Following are outputs from the R500:
+
+@itemize
+@item
+Lenovo BIOS 3.13 (EC firmware 1.06):
+@itemize
+@item
+@url{../resources/misc/dumps/r500/}
+@end itemize
+
+@end itemize
+
+@node Issues
+@chapter Issues
+@anchor{#issues}
+@menu
+* False report of overheating automatic shut down::
+* Cardbus slot didn't work when tested::
+@end menu
+
+@node False report of overheating automatic shut down
+@section False report of overheating, automatic shut down
+@anchor{#false-report-of-overheating-automatic-shut-down}
+When attempting to boot Trisquel 7 live USB (GNOME), the following error appears and then the system abruptly shuts down: @strong{thermal thermal_zone1: critical temperature reached(120 C),shutting down}.
+
+This is false. When booting with @strong{acpi=off}, xsensors shows no overheating during a stress test. The system does not feel hot, nor does anything smell like it's burning.
+
+This is most likely caused by an ACPI bug in coreboot, which will have to be investigated. Grep for those things, comparing factory/libreboot (iasl -d or acpidump):
+
+@verbatim
+ Return (C2K(\_SB.PCI0.LPCB.EC.TMP0))
+TMP0, 8, /* Thermal Zone 0 temperature */
+@end verbatim
+
+@node Cardbus slot didn't work when tested
+@section Cardbus slot didn't work when tested
+@anchor{#cardbus-slot-didnt-work-when-tested}
+Investigate.
+
+@node Descriptor differences
+@chapter Descriptor differences
+@anchor{#descriptor-differences}
+The @emph{ich9gen} and @emph{ich9deblob} utilities were modified, to reflect these differences.
+@menu
+* Component 1 Density::
+* flReg1LIMIT::
+* Onboard gigabit ethernet NIC is disabled::
+@end menu
+
+@node Component 1 Density
+@section Component 1 Density
+@anchor{#component-1-density}
+
+@verbatim
+- descriptorStruct.componentSection.flcomp.component1Density = 0x4;
++ descriptorStruct.componentSection.flcomp.component1Density = 0x3;
+@end verbatim
+
+Read page 848 in the ICH9 datasheet, linked to from @uref{gm45_remove_me.html#flash_descriptor_region,gm45_remove_me.html#flash_descriptor_region}. This doesn't break anything, but in the process of debugging descriptor differences on the R500, it was found that this config option isn't being modified in libreboot, for different size ROM images. 4MiB ROM images still contain 0x4 for component1Density. Per datasheets, 0x4 (100) is 8MiB, and 0x3 (011) is 4MiB. @strong{This should be fixed!}
+
+It was 0x3 for this test, because the R500 that was used to create this report had a 4MiB SOIC-8 flash chip.
+
+@node flReg1LIMIT
+@section flReg1.LIMIT
+@anchor{#flreg1.limit}
+
+@verbatim
+- /* descriptorStruct.regionSection.flReg1.LIMIT = 0x07ff; */
++ /* descriptorStruct.regionSection.flReg1.LIMIT = 0x03ff; */
+@end verbatim
+
+Ignore this. This is not used at all, and is instead automatically set, depending on the targetted ROM image size, both in ich9gen and ich9deblob. 0x7ff means 8MiB, and 0x3ff means 4MiB. flReg1 is for the BIOS region. Simply speaking, this is defining the final 4KiB section of the ROM image, where the BIOS region ends.
+
+It was 0x3ff for this test, because the R500 that was used to create this report had a 4MiB SOIC-8 flash chip.
+
+@node Onboard gigabit ethernet NIC is disabled
+@section Onboard gigabit ethernet NIC is disabled
+@anchor{#onboard-gigabit-ethernet-nic-is-disabled}
+
+@verbatim
+- descriptorStruct.ichStraps.ichStrap0.integratedGbe = 0x1;
+- descriptorStruct.ichStraps.ichStrap0.lanPhy = 0x1;
++ descriptorStruct.ichStraps.ichStrap0.integratedGbe = 0x0;
++ descriptorStruct.ichStraps.ichStrap0.lanPhy = 0x0;
+@end verbatim
+
+Most GM45 laptops (e.g. X200, T400, T500, R400) have the @strong{Intel 82567LM} integrated gigabit NIC.
+
+On the R500, a @strong{Broadcom BCM5787M} NIC is present. To make this work, the change above must be made for the R500 descriptor.
+
+@node No Gbe region!
+@chapter No Gbe region!
+@anchor{#no-gbe-region}
+Not shown in the diffs above:
+
+@verbatim
+Original: Descriptor start block: 00000000 ; Descriptor end block: 00000000
+Original: BIOS start block: 00200000 ; BIOS end block: 003ff000
+Original: ME start block: 00001000 ; ME end block: 001f7000
+Original: GBe start block: 00fff000 ; GBe end block: 00000000
+Original: Platform start block: 001f8000 ; Platform end block: 001ff000
+@end verbatim
+
+As explained above, this laptop uses a Broadcom NIC, which means that the Gbe region does not and @emph{should not} exist, since this is for the Intel NIC only.
+
+In the output above, Gbe starts at fff and ends at 000. Base 1FFF or FFF, and limit 0, means that the region is disabled.
+
+In the output above, the ME region is 4KiB larger than on other GM45 systems that have a Gbe region. This accounts for the lack of a Gbe region.
+
+As part of this effort, ich9gen/ich9deblob/demefactory will all be modified to account for the differences above.
+
+Copyright © 2015 Francis Rowe <info@@gluglug.org.uk>@* Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license can be found at @uref{../resources/licenses/gfdl-1.3.txt,gfdl-1.3.txt}
+
+Updated versions of the license (when available) can be found at @uref{https://www.gnu.org/licenses/licenses.html,https://www.gnu.org/licenses/licenses.html}
+
+UNLESS OTHERWISE SEPARATELY UNDERTAKEN BY THE LICENSOR, TO THE EXTENT POSSIBLE, THE LICENSOR OFFERS THE LICENSED MATERIAL AS-IS AND AS-AVAILABLE, AND MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND CONCERNING THE LICENSED MATERIAL, WHETHER EXPRESS, IMPLIED, STATUTORY, OR OTHER. THIS INCLUDES, WITHOUT LIMITATION, WARRANTIES OF TITLE, MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NON-INFRINGEMENT, ABSENCE OF LATENT OR OTHER DEFECTS, ACCURACY, OR THE PRESENCE OR ABSENCE OF ERRORS, WHETHER OR NOT KNOWN OR DISCOVERABLE. WHERE DISCLAIMERS OF WARRANTIES ARE NOT ALLOWED IN FULL OR IN PART, THIS DISCLAIMER MAY NOT APPLY TO YOU.
+
+TO THE EXTENT POSSIBLE, IN NO EVENT WILL THE LICENSOR BE LIABLE TO YOU ON ANY LEGAL THEORY (INCLUDING, WITHOUT LIMITATION, NEGLIGENCE) OR OTHERWISE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, CONSEQUENTIAL, PUNITIVE, EXEMPLARY, OR OTHER LOSSES, COSTS, EXPENSES, OR DAMAGES ARISING OUT OF THIS PUBLIC LICENSE OR USE OF THE LICENSED MATERIAL, EVEN IF THE LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH LOSSES, COSTS, EXPENSES, OR DAMAGES. WHERE A LIMITATION OF LIABILITY IS NOT ALLOWED IN FULL OR IN PART, THIS LIMITATION MAY NOT APPLY TO YOU.
+
+The disclaimer of warranties and limitation of liability provided above shall be interpreted in a manner that, to the extent possible, most closely approximates an absolute disclaimer and waiver of all liability.
+
+@bye
diff --git a/docs/src/hcl/t400.texi b/docs/src/hcl/t400.texi
new file mode 100644
index 0000000..2c2b303
--- /dev/null
+++ b/docs/src/hcl/t400.texi
@@ -0,0 +1,88 @@
+\input texinfo
+@documentencoding UTF-8
+
+@ifnottex
+@paragraphindent 0
+@end ifnottex
+@titlepage
+@title ThinkPad T400
+@end titlepage
+
+@node Top
+@top ThinkPad T400
+
+@menu
+* ThinkPad T400::
+* LCD compatibly::
+@end menu
+
+@node ThinkPad T400
+@chapter ThinkPad T400
+@anchor{#thinkpad-t400}
+It is believed that all or most T400 laptops are compatible. See notes about @uref{../install/t400_external.html#cpu_compatibility,CPU compatibility} for potential incompatibilities.
+
+There are two possible flash chip sizes for the T400: 4MiB (32Mbit) or 8MiB (64Mbit). This can be identified by the type of flash chip below the palmrest: 4MiB is SOIC-8, 8MiB is SOIC-16.
+
+@strong{The T400 laptops come with the ME (and sometimes AMT in addition) before flashing libreboot. Libreboot disables and removes it by using a modified descriptor: see @uref{gm45_remove_me.html,gm45_remove_me.html}} (contains notes, plus instructions)
+
+Flashing instructions can be found at @uref{../install/index.html#flashrom,../install/index.html#flashrom}
+
+@uref{index.html,Back to previous index}.
+@menu
+* Compatibility without blobs::
+@end menu
+
+@node Compatibility without blobs
+@section Compatibility (without blobs)
+@anchor{#compatibility-without-blobs}
+@menu
+* Hardware virtualization vt-x::
+@end menu
+
+@node Hardware virtualization vt-x
+@subsection Hardware virtualization (vt-x)
+@anchor{#hardware-virtualization-vt-x}
+The T400, when run without CPU microcode updates in coreboot, currently kernel panics if running QEMU with vt-x enabled on 2 cores for the guest. With a single core enabled for the guest, the guest panics (but the host is fine). Working around this in QEMU might be possible; if not, software virtualization should work fine (it's just slower).
+
+On GM45 hardware (with libreboot), make sure that the @emph{kvm} and @emph{kvm_intel} kernel modules are not loaded, when using QEMU.
+
+The following errata datasheet from Intel might help with investigation: @uref{http://download.intel.com/design/mobile/specupdt/320121.pdf,http://download.intel.com/design/mobile/specupdt/320121.pdf}
+
+The T400 is almost identical to the X200, code-wise. See @uref{x200.html,x200.html}.
+
+@node LCD compatibly
+@chapter LCD compatibly
+@anchor{#lcd-compatibly}
+Not all LCD panels are compatible yet. See @uref{gm45_lcd.html,gm45_lcd.html}.
+@menu
+* Hardware register dumps::
+@end menu
+
+@node Hardware register dumps
+@section Hardware register dumps
+@anchor{#hardware-register-dumps}
+The coreboot wiki @uref{http://www.coreboot.org/Motherboard_Porting_Guide,shows} how to collect various logs useful in porting to new boards. Following are outputs from the T400:
+
+@itemize
+@item
+T400 with @strong{Winbond W25X64} flash chip (8MiB, SOIC-16) and Lenovo BIOS 2.02 (EC firmware 1.01):
+@itemize
+@item
+@uref{../resources/misc/dumps/logs-t400-bios2.02-ec1.01/,../resources/misc/dumps/logs-t400-bios2.02-ec1.01/}
+@end itemize
+
+@item
+Version of flashrom used for the external flashing/reading logs is the one that libreboot git revision c164960 uses.
+@end itemize
+
+Copyright © 2015 Francis Rowe <info@@gluglug.org.uk>@* Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license can be found at @uref{../resources/licenses/gfdl-1.3.txt,gfdl-1.3.txt}
+
+Updated versions of the license (when available) can be found at @uref{https://www.gnu.org/licenses/licenses.html,https://www.gnu.org/licenses/licenses.html}
+
+UNLESS OTHERWISE SEPARATELY UNDERTAKEN BY THE LICENSOR, TO THE EXTENT POSSIBLE, THE LICENSOR OFFERS THE LICENSED MATERIAL AS-IS AND AS-AVAILABLE, AND MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND CONCERNING THE LICENSED MATERIAL, WHETHER EXPRESS, IMPLIED, STATUTORY, OR OTHER. THIS INCLUDES, WITHOUT LIMITATION, WARRANTIES OF TITLE, MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NON-INFRINGEMENT, ABSENCE OF LATENT OR OTHER DEFECTS, ACCURACY, OR THE PRESENCE OR ABSENCE OF ERRORS, WHETHER OR NOT KNOWN OR DISCOVERABLE. WHERE DISCLAIMERS OF WARRANTIES ARE NOT ALLOWED IN FULL OR IN PART, THIS DISCLAIMER MAY NOT APPLY TO YOU.
+
+TO THE EXTENT POSSIBLE, IN NO EVENT WILL THE LICENSOR BE LIABLE TO YOU ON ANY LEGAL THEORY (INCLUDING, WITHOUT LIMITATION, NEGLIGENCE) OR OTHERWISE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, CONSEQUENTIAL, PUNITIVE, EXEMPLARY, OR OTHER LOSSES, COSTS, EXPENSES, OR DAMAGES ARISING OUT OF THIS PUBLIC LICENSE OR USE OF THE LICENSED MATERIAL, EVEN IF THE LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH LOSSES, COSTS, EXPENSES, OR DAMAGES. WHERE A LIMITATION OF LIABILITY IS NOT ALLOWED IN FULL OR IN PART, THIS LIMITATION MAY NOT APPLY TO YOU.
+
+The disclaimer of warranties and limitation of liability provided above shall be interpreted in a manner that, to the extent possible, most closely approximates an absolute disclaimer and waiver of all liability.
+
+@bye
diff --git a/docs/src/hcl/t500.texi b/docs/src/hcl/t500.texi
new file mode 100644
index 0000000..42dcad1
--- /dev/null
+++ b/docs/src/hcl/t500.texi
@@ -0,0 +1,98 @@
+\input texinfo
+@documentencoding UTF-8
+
+@ifnottex
+@paragraphindent 0
+@end ifnottex
+@titlepage
+@title ThinkPad T500
+@end titlepage
+
+@node Top
+@top ThinkPad T500
+
+@menu
+* ThinkPad T500::
+* LCD compatibly::
+@end menu
+
+@node ThinkPad T500
+@chapter ThinkPad T500
+@anchor{#thinkpad-t500}
+It is believed that all or most T500 laptops are compatible. See notes about @uref{../install/t500_external.html#cpu_compatibility,CPU compatibility} for potential incompatibilities.
+
+There are two possible flash chip sizes for the T500: 4MiB (32Mbit) or 8MiB (64Mbit). This can be identified by the type of flash chip below the palmrest: 4MiB is SOIC-8, 8MiB is SOIC-16.
+
+@strong{The T500 laptops come with the ME (and sometimes AMT in addition) before flashing libreboot. Libreboot disables and removes it by using a modified descriptor: see @uref{gm45_remove_me.html,gm45_remove_me.html}} (contains notes, plus instructions)
+
+Flashing instructions can be found at @uref{../install/index.html#flashrom,../install/index.html#flashrom}
+
+@uref{index.html,Back to previous index}.
+@menu
+* Compatibility without blobs::
+@end menu
+
+@node Compatibility without blobs
+@section Compatibility (without blobs)
+@anchor{#compatibility-without-blobs}
+@menu
+* Hardware virtualization vt-x::
+@end menu
+
+@node Hardware virtualization vt-x
+@subsection Hardware virtualization (vt-x)
+@anchor{#hardware-virtualization-vt-x}
+The T500, when run without CPU microcode updates in coreboot, currently kernel panics if running QEMU with vt-x enabled on 2 cores for the guest. With a single core enabled for the guest, the guest panics (but the host is fine). Working around this in QEMU might be possible; if not, software virtualization should work fine (it's just slower).
+
+On GM45 hardware (with libreboot), make sure that the @emph{kvm} and @emph{kvm_intel} kernel modules are not loaded, when using QEMU.
+
+The following errata datasheet from Intel might help with investigation: @uref{http://download.intel.com/design/mobile/specupdt/320121.pdf,http://download.intel.com/design/mobile/specupdt/320121.pdf}
+
+The T500 is almost identical to the X200, code-wise. See @uref{x200.html,x200.html}.
+
+@node LCD compatibly
+@chapter LCD compatibly
+@anchor{#lcd-compatibly}
+Not all LCD panels are compatible yet. See @uref{gm45_lcd.html,gm45_lcd.html}.
+@menu
+* Descriptor and Gbe differences::
+* Hardware register dumps::
+@end menu
+
+@node Descriptor and Gbe differences
+@section Descriptor and Gbe differences
+@anchor{#descriptor-and-gbe-differences}
+See @uref{../resources/misc/dumps/t500_x200_descriptor/descriptor_diff_t500_x200.txt,../resources/misc/dumps/t500_x200_descriptor/descriptor_diff_t500_x200.txt} and @uref{../resources/misc/dumps/t500_x200_descriptor/gbe_diff_t500_x200.txt,../resources/misc/dumps/t500_x200_descriptor/gbe_diff_t500_x200.txt}
+
+The patches above are based on the output from ich9deblob on a factory.rom image dumped from the T500 with a SOIC-8 4MiB flash chip. The patch re-creates the X200 descriptor/gbe source, so the commands were something like:@* $ @strong{diff -u t500gbe x200gbe}@* $ @strong{diff -u t500descriptor x200descriptor}
+
+ME VSCC table is in a different place and a different size on the T500. Libreboot disables and removes the ME anyway, so it doesn't matter.
+
+The very same descriptor/gbe used on the X200 (generated by @uref{gm45_remove_me.html#ich9gen,ich9gen}) was re-used on the T500, and it still worked.
+
+@node Hardware register dumps
+@section Hardware register dumps
+@anchor{#hardware-register-dumps}
+The coreboot wiki @uref{http://www.coreboot.org/Motherboard_Porting_Guide,shows} how to collect various logs useful in porting to new boards. Following are outputs from the T500:
+
+@itemize
+@item
+T500 with @strong{Macronix MX25L3205D} flash chip (4MiB, SOIC-8) and Lenovo BIOS 3.13 7VET83WW (EC firmware 1.06):
+@itemize
+@item
+@uref{../resources/misc/dumps/t500log/,../resources/misc/dumps/t500log/}
+@end itemize
+
+@end itemize
+
+Copyright © 2015 Francis Rowe <info@@gluglug.org.uk>@* Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license can be found at @uref{../resources/licenses/gfdl-1.3.txt,gfdl-1.3.txt}
+
+Updated versions of the license (when available) can be found at @uref{https://www.gnu.org/licenses/licenses.html,https://www.gnu.org/licenses/licenses.html}
+
+UNLESS OTHERWISE SEPARATELY UNDERTAKEN BY THE LICENSOR, TO THE EXTENT POSSIBLE, THE LICENSOR OFFERS THE LICENSED MATERIAL AS-IS AND AS-AVAILABLE, AND MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND CONCERNING THE LICENSED MATERIAL, WHETHER EXPRESS, IMPLIED, STATUTORY, OR OTHER. THIS INCLUDES, WITHOUT LIMITATION, WARRANTIES OF TITLE, MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NON-INFRINGEMENT, ABSENCE OF LATENT OR OTHER DEFECTS, ACCURACY, OR THE PRESENCE OR ABSENCE OF ERRORS, WHETHER OR NOT KNOWN OR DISCOVERABLE. WHERE DISCLAIMERS OF WARRANTIES ARE NOT ALLOWED IN FULL OR IN PART, THIS DISCLAIMER MAY NOT APPLY TO YOU.
+
+TO THE EXTENT POSSIBLE, IN NO EVENT WILL THE LICENSOR BE LIABLE TO YOU ON ANY LEGAL THEORY (INCLUDING, WITHOUT LIMITATION, NEGLIGENCE) OR OTHERWISE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, CONSEQUENTIAL, PUNITIVE, EXEMPLARY, OR OTHER LOSSES, COSTS, EXPENSES, OR DAMAGES ARISING OUT OF THIS PUBLIC LICENSE OR USE OF THE LICENSED MATERIAL, EVEN IF THE LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH LOSSES, COSTS, EXPENSES, OR DAMAGES. WHERE A LIMITATION OF LIABILITY IS NOT ALLOWED IN FULL OR IN PART, THIS LIMITATION MAY NOT APPLY TO YOU.
+
+The disclaimer of warranties and limitation of liability provided above shall be interpreted in a manner that, to the extent possible, most closely approximates an absolute disclaimer and waiver of all liability.
+
+@bye
diff --git a/docs/src/hcl/x200.texi b/docs/src/hcl/x200.texi
new file mode 100644
index 0000000..76d5bad
--- /dev/null
+++ b/docs/src/hcl/x200.texi
@@ -0,0 +1,220 @@
+\input texinfo
+@documentencoding UTF-8
+
+@macro textstrikeout{text}
+~~\text\~~
+@end macro
+
+@ifnottex
+@paragraphindent 0
+@end ifnottex
+@titlepage
+@title ThinkPad X200
+@end titlepage
+
+@node Top
+@top ThinkPad X200
+
+@menu
+* ThinkPad X200::
+* RAM S3 and microcode updates::
+@end menu
+
+@node ThinkPad X200
+@chapter ThinkPad X200
+@anchor{#thinkpad-x200}
+It is believed that all X200 laptops are compatible. X200S and X200 Tablet will also work, @ref{#x200s,depending on the configuration}.
+
+It *might* be possible to put an X200 motherboard in an X201 chassis, though this is currently untested by the libreboot project. The same may also apply between X200S and X201S; again, this is untested. @strong{It's most likely true.}
+
+There are two possible flash chip sizes for the X200: 4MiB (32Mbit) or 8MiB (64Mbit). This can be identified by the type of flash chip below the palmrest: 4MiB is SOIC-8, 8MiB is SOIC-16.
+
+@strong{The X200 laptops come with the ME (and sometimes AMT in addition) before flashing libreboot. Libreboot disables and removes it by using a modified descriptor: see @uref{gm45_remove_me.html,gm45_remove_me.html}} (contains notes, plus instructions)
+
+Flashing instructions can be found at @uref{../install/index.html#flashrom,../install/index.html#flashrom}
+
+@uref{index.html,Back to previous index}.
+@menu
+* Compatibility without blobs::
+* X200S and X200 Tablet::
+* Trouble undocking button doesn't work::
+* LCD compatibility list::
+* How to tell if it has an LED or CCFL?::
+* Hardware register dumps::
+@end menu
+
+@node Compatibility without blobs
+@section Compatibility (without blobs)
+@anchor{#compatibility-without-blobs}
+@menu
+* Hardware virtualization vt-x::
+@end menu
+
+@node Hardware virtualization vt-x
+@subsection Hardware virtualization (vt-x)
+@anchor{#hardware-virtualization-vt-x}
+The X200, when run without CPU microcode updates in coreboot, currently kernel panics if running QEMU with vt-x enabled on 2 cores for the guest. With a single core enabled for the guest, the guest panics (but the host is fine). Working around this in QEMU might be possible; if not, software virtualization should work fine (it's just slower).
+
+On GM45 hardware (with libreboot), make sure that the @emph{kvm} and @emph{kvm_intel} kernel modules are not loaded, when using QEMU.
+
+The following errata datasheet from Intel might help with investigation: @uref{http://download.intel.com/design/mobile/specupdt/320121.pdf,http://download.intel.com/design/mobile/specupdt/320121.pdf}
+
+@node X200S and X200 Tablet
+@section X200S and X200 Tablet.
+@anchor{#x200s-and-x200-tablet.}
+X200S and X200 Tablet have raminit issues at the time of writing (GS45 chipset. X200 uses GM45).
+
+X200S and X200 Tablet are known to work, but only with certain CPU+RAM configurations. The current stumbling block is RCOMP and SFF, mentioned in @uref{https://www.cs.cmu.edu/~410/doc/minimal_boot.pdf,https://www.cs.cmu.edu/~410/doc/minimal_boot.pdf}.
+
+The issues mostly relate to raminit (memory initialization). With an unpatched coreboot, you get the following: @uref{../resources/text/x200s/cblog00.txt,x200s/cblog00.txt}. No SODIMM combination that was tested would work. At first glance, it looks like GS45 (chipset that X200S uses. X200 uses GM45) is unsupported, but there is a workaround that can be used to make certain models of the X200S work, depending on the RAM.
+
+The datasheet for GS45 describes two modes: low-performance and high-performance. Low performance uses the SU range of ultra-low voltage procesors (SU9400, for example), and high-performance uses the SL range of processors (SL9400, for example). According to datasheets, GS45 behaves very similarly to GM45 when operating in high-performance mode.
+
+The theory then was that you could simply remove the checks in coreboot and make it pass GS45 off as GM45; the idea is that, with a high-performance mode CPU (SL9400, for example) it would just boot up and work.
+
+This suspicion was confirmed with the following log: @uref{../resources/text/x200s/cblog01.txt,x200s/cblog01.txt}. The memory modules in this case are 2x4GB. @textstrikeout{@strong{However, not all configurations work: @uref{../resources/text/x200s/cblog02.txt,x200s/cblog02.txt} (2x2GB) and @uref{../resources/text/x200s/cblog03.txt,x200s/cblog03.txt} (1x2GB) show a failed bootup.}} @emph{False alarm. The modules were mixed (non-matching). X200S with high-performance mode CPU will work so long as you use matching memory modules (doesn't matter what size).}
+
+This was then pushed as a patch for coreboot, which can be found at @uref{http://review.coreboot.org/#/c/7786/,http://review.coreboot.org/#/c/7786/} (libreboot merges this patch in coreboot-libre now. Check the 'getcb' script in src or git).
+@menu
+* Proper GS45 raminit::
+@end menu
+
+@node Proper GS45 raminit
+@subsection Proper GS45 raminit
+@anchor{#proper-gs45-raminit}
+A new northbridge gs45 should be added to coreboot, based on gm45, and a new port x200st (X200S and X200T) should be added based on the x200 port.
+
+This port would have proper raminit. Alternatively, gs45 (if raminit is taken to be the only issue with it) can be part of gm45 northbridge support (and X200S/Tablet being part of the X200 port) with conditional checks in the raminit that make raminit work differently (as required) for GS45. nico_h and pgeorgi/patrickg in the coreboot IRC channel should know more about raminit on gm45 and likely gs45.
+
+pgeorgi recommends to run SerialICE on the factory BIOS (for X200S), comparing it with X200 (factory BIOS) and X200 (gm45 raminit code in coreboot), to see what the differences are. Then tweak raminit code based on that.
+
+@node Trouble undocking button doesn't work
+@section Trouble undocking (button doesn't work)
+@anchor{#trouble-undocking-button-doesnt-work}
+This person seems to have a workaround: @uref{https://github.com/the-unconventional/libreboot-undock,https://github.com/the-unconventional/libreboot-undock}
+
+@node LCD compatibility list
+@section LCD compatibility list
+@anchor{#lcd-compatibility-list}
+LCD panel list (X200 panels listed there): @uref{http://www.thinkwiki.org/wiki/TFT_display,http://www.thinkwiki.org/wiki/TFT_display}
+
+All LCD panels for the X200, X200S and X200 Tablet are known to work.
+
+@ref{#pagetop,Back to top of page.}
+@menu
+* AFFS/IPS panels::
+* X200S::
+@end menu
+
+@node AFFS/IPS panels
+@subsection AFFS/IPS panels
+@anchor{#affsips-panels}
+@menu
+* X200::
+@end menu
+
+@node X200
+@subsubsection X200
+@anchor{#x200}
+Adapted from @uref{https://github.com/bibanon/Coreboot-ThinkPads/wiki/ThinkPad-X200,https://github.com/bibanon/Coreboot-ThinkPads/wiki/ThinkPad-X200}
+
+Look at wikipedia for difference between TN and IPS panels. IPS have much better colour/contrast than a regular TN, and will typically have good viewing angles.
+
+These seem to be from the X200 tablet. You need to find one without the glass touchscreen protection on it (might be able to remove it, though). It also must not have a digitizer on it (again, might be possible to just simply remove the digitizer).
+
+@itemize
+@item
+BOE-Hydis HV121WX4-120, HV121WX4-110 or HV121WX4-100 - cheap-ish, might be hard to find
+@item
+Samsung LTN121AP02-001 - common to find, cheap
+@end itemize
+
+@strong{If your X200 has an LED backlit panel in it, then you also need to get an inverter and harness cable that is compatible with the CCFL panels. To see which panel type you have, see @ref{#led_howtotell,#led_howtotell}. If you need the inverter/cable, here are part numbers: 44C9909 for CCFL LVDS cable with bluetooth and camera connections, and 42W8009 or 42W8010 for the inverter.}
+
+There are glossy and matte versions of these. Matte means anti-glare, which is what you want (in this authors opinion).
+
+Refer to the HMM (hardware maintenance manual) for how to replace the screen.
+
+Sources:
+
+@itemize
+@item
+@uref{http://forum.thinkpads.com/viewtopic.php?f=2&t=84941,ThinkPad Forums - Matte AFFS Panel on X200}
+@item
+@uref{http://forum.thinkpads.com/viewtopic.php?p=660662#p660662,ThinkPad Forums - Parts for X200 AFFS Mod}
+@item
+@uref{http://thinkwiki.de/X200_Displayumbau,ThinkWiki.de - X200 Displayumbau} (achtung: du musst lesen und/oder spreche deutsch; oder ein freund fur hilfe)
+@end itemize
+
+@node X200S
+@subsection X200S
+@anchor{#x200s}
+@uref{http://forum.thinkpads.com/viewtopic.php?p=618928#p618928,http://forum.thinkpads.com/viewtopic.php?p=618928#p618928} explains that the X200S screens/assemblies are thinner. You need to replace the whole lid with one from a normal X200/X201.
+
+@ref{#pagetop,Back to top of page.}
+
+@node How to tell if it has an LED or CCFL?
+@section How to tell if it has an LED or CCFL?
+@anchor{#how-to-tell-if-it-has-an-led-or-ccfl}
+Some X200s have a CCFL backlight and some have an LED backlight, in their LCD panel. This also means that the inverters will vary, so you must be careful if ever replacing either the panel and/or inverter. (a CCFL inverter is high-voltage and will destroy an LED backlit panel).
+
+CCFLs contain mercury. An X200 with a CCFL backlight will (@strong{}unless it has been changed to an LED, with the correct inverter. Check with your supplier!) the following: @emph{"This product contains Lithium Ion Battery, Lithium Battery and a lamp which contains mercury; dispose according to local, state or federal laws"} (one with an LED backlit panel will say something different).
+
+@ref{#pagetop,Back to top of page.}
+
+@node Hardware register dumps
+@section Hardware register dumps
+@anchor{#hardware-register-dumps}
+The coreboot wiki @uref{http://www.coreboot.org/Motherboard_Porting_Guide,shows} how to collect various logs useful in porting to new boards. Following are outputs from the X200:
+
+@itemize
+@item
+BIOS 3.15, EC 1.06
+@itemize
+@item
+@url{../resources/misc/dumps/x200/}
+@end itemize
+
+@end itemize
+
+@node RAM S3 and microcode updates
+@chapter RAM, S3 and microcode updates
+@anchor{#ram-s3-and-microcode-updates}
+Not all memory modules work. Most of the default ones do, but you have to be careful when upgrading to 8GiB; some modules work, some don't.
+
+pehjota started collecting some steppings for different CPUs on several X200 laptops. You can get the CPUID by running: @* $ @strong{dmesg | sed -n 's/^.* microcode: CPU0 sig=0x\([^,]*\),.*$/\1/p'}
+
+What pehjota wrote: The laptops that have issues resuming from suspend, as well as a laptop that (as I mentioned earlier in #libreboot) won't boot with any Samsung DIMMs, all have CPUID 0x10676 (stepping M0).
+
+What pehjota wrote: Laptops with CPUID 0x167A (stepping R0) resume properly every time and work with Samsung DIMMs. I'll need to do more testing on more units to better confirm these trends, but it looks like the M0 microcode is very buggy. That would also explain why I didn't have issues with Samsung DIMMs with the Lenovo BIOS (which would have microcode updates). I wonder if VT-x works on R0.
+
+What pehjota wrote: As I said, 10676 is M0 and 1067A is R0; those are the two CPUIDs and steppings for Intel Core 2 Duo P8xxx CPUs with factory microcode. (1067 is the family and model, and 6 or A is the stepping ID.)
+
+@strong{TODO: check the CPUIDs and test S3 resume and/or KVM on any C2D systems (including non-P8xxx ones, which I don't have here) you have available. I'd be curious if you could confirm these results.} It might not be coreboot that's buggy with raminit/S3; it might just be down to the microcode updates.
+@menu
+* Unsorted notes::
+@end menu
+
+@node Unsorted notes
+@section Unsorted notes
+@anchor{#unsorted-notes}
+
+@verbatim
+<sgsit> do you know if it's possible to flash thinkpads over the LPC debug connector at the front edge?
+<sgsit> that would make life much easier for systems like this
+<sgsit> all the Wistron manufactured systems have this thing called a "golden finger", normally at the front edge of the board
+<sgsit> you can plug a board in which gives diagnostic codes but i'm wondering whether it is capable of more
+<sgsit> http://www.endeer.cz/bios.tools/bios.html
+@end verbatim
+
+Copyright © 2014, 2015 Francis Rowe <info@@gluglug.org.uk>@* Copyright © 2015 Patrick "P. J." McDermott <pj@@pehjota.net>@* Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license can be found at @uref{../resources/licenses/gfdl-1.3.txt,gfdl-1.3.txt}
+
+Updated versions of the license (when available) can be found at @uref{https://www.gnu.org/licenses/licenses.html,https://www.gnu.org/licenses/licenses.html}
+
+UNLESS OTHERWISE SEPARATELY UNDERTAKEN BY THE LICENSOR, TO THE EXTENT POSSIBLE, THE LICENSOR OFFERS THE LICENSED MATERIAL AS-IS AND AS-AVAILABLE, AND MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND CONCERNING THE LICENSED MATERIAL, WHETHER EXPRESS, IMPLIED, STATUTORY, OR OTHER. THIS INCLUDES, WITHOUT LIMITATION, WARRANTIES OF TITLE, MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NON-INFRINGEMENT, ABSENCE OF LATENT OR OTHER DEFECTS, ACCURACY, OR THE PRESENCE OR ABSENCE OF ERRORS, WHETHER OR NOT KNOWN OR DISCOVERABLE. WHERE DISCLAIMERS OF WARRANTIES ARE NOT ALLOWED IN FULL OR IN PART, THIS DISCLAIMER MAY NOT APPLY TO YOU.
+
+TO THE EXTENT POSSIBLE, IN NO EVENT WILL THE LICENSOR BE LIABLE TO YOU ON ANY LEGAL THEORY (INCLUDING, WITHOUT LIMITATION, NEGLIGENCE) OR OTHERWISE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, CONSEQUENTIAL, PUNITIVE, EXEMPLARY, OR OTHER LOSSES, COSTS, EXPENSES, OR DAMAGES ARISING OUT OF THIS PUBLIC LICENSE OR USE OF THE LICENSED MATERIAL, EVEN IF THE LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH LOSSES, COSTS, EXPENSES, OR DAMAGES. WHERE A LIMITATION OF LIABILITY IS NOT ALLOWED IN FULL OR IN PART, THIS LIMITATION MAY NOT APPLY TO YOU.
+
+The disclaimer of warranties and limitation of liability provided above shall be interpreted in a manner that, to the extent possible, most closely approximates an absolute disclaimer and waiver of all liability.
+
+@bye
generated by cgit v0.9.1 at 2024-11-09 10:32:58 (EST)