Update coreboot-libre

Rebase all patches. Remove the ones that are no longer needed.

More CPU microcode updates were moved to coreboot's 3rdparty
repository, so there are less blobs for libreboot to delete
now (because the 3rdparty repository is not checked out in
libreboot).

Correct HDA verbs used for T400 (also R400, T500) (patch is in
coreboot, merged).

25 files changed, 245 insertions, 2779 deletions

diff --git a/resources/libreboot/patch/0004-southbridge-intel-common-spi-Add-Flash-lockdown-opti.patch b/resources/libreboot/patch/0001-southbridge-intel-common-spi-Add-Flash-lockdown-opti.patch
index f1f7e42..fd0b8eb 100644
--- a/resources/libreboot/patch/0004-southbridge-intel-common-spi-Add-Flash-lockdown-opti.patch
+++ b/resources/libreboot/patch/0001-southbridge-intel-common-spi-Add-Flash-lockdown-opti.patch
@@ -1,7 +1,7 @@
-From 8c85c6ce851927a6ee781f2ddc970584376e6710 Mon Sep 17 00:00:00 2001
+From 29a398fd71efa8ca63a98125ec4e5c1de96bcb85 Mon Sep 17 00:00:00 2001
 From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Tue, 7 Apr 2015 13:45:06 -0500
-Subject: [PATCH 04/22] southbridge/intel/common/spi: Add Flash lockdown option
+Subject: [PATCH 01/17] southbridge/intel/common/spi: Add Flash lockdown option
 
 Under certain circumstances it is desirable to prevent
 software from altering the contents of the Flash device.
@@ -34,7 +34,7 @@ index 949310b..52ada30 100644
 +	  a hardware programmer AND physical access to the Flash device!
 \ No newline at end of file
 diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
-index 416a30f..6c8e2eb 100644
+index 1d3ebf6..04f05ed 100644
 --- a/src/southbridge/intel/common/spi.c
 +++ b/src/southbridge/intel/common/spi.c
 @@ -2,6 +2,7 @@
@@ -45,7 +45,7 @@ index 416a30f..6c8e2eb 100644
   *
   * See file CREDITS for list of people who contributed to this
   * project.
-@@ -354,11 +355,19 @@ void spi_init(void)
+@@ -353,11 +354,19 @@ void spi_init(void)
  
  	ich_set_bbar(0);
  
@@ -70,7 +70,7 @@ index 416a30f..6c8e2eb 100644
  }
  #ifndef __SMM__
  static void spi_init_cb(void *unused)
-@@ -928,7 +937,6 @@ static int ich_hwseq_write(struct spi_flash *flash,
+@@ -927,7 +936,6 @@ static int ich_hwseq_write(struct spi_flash *flash,
  	return 0;
  }
  
diff --git a/resources/libreboot/patch/0001-src-southbridge-intel-i82801ix-Add-GPIO-register-loc.patch b/resources/libreboot/patch/0001-src-southbridge-intel-i82801ix-Add-GPIO-register-loc.patch
deleted file mode 100644
index 469bd37..0000000
--- a/resources/libreboot/patch/0001-src-southbridge-intel-i82801ix-Add-GPIO-register-loc.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From a0aa2b0da29244b7ca657b45f5d4e959cebea8ad Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <tpearson@raptorengineeringinc.com>
-Date: Sun, 5 Apr 2015 18:03:15 -0500
-Subject: [PATCH 01/22] src/southbridge/intel/i82801ix: Add GPIO register
- locations
-
-Change-Id: I226a1a6bc6b1f921c03f8ec57875a88314928aeb
-Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
----
- src/southbridge/intel/i82801ix/i82801ix.h | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
-diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h
-index 10b2717..afc644b 100644
---- a/src/southbridge/intel/i82801ix/i82801ix.h
-+++ b/src/southbridge/intel/i82801ix/i82801ix.h
-@@ -1,6 +1,7 @@
- /*
-  * This file is part of the coreboot project.
-  *
-+ * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
-  * Copyright (C) 2008-2009 coresystems GmbH
-  *               2012 secunet Security Networks AG
-  *
-@@ -76,6 +77,15 @@
- #define ALT_GP_SMI_STS	0x3a
- 
- 
-+#define GP_IO_USE_SEL	0x00
-+#define GP_IO_SEL	0x04
-+#define GP_LVL		0x0c
-+#define GPO_BLINK	0x18
-+#define GPI_INV		0x2c
-+#define GP_IO_USE_SEL2	0x30
-+#define GP_IO_SEL2	0x34
-+#define GP_LVL2		0x38
-+
- #define DEBUG_PERIODIC_SMIS	0
- 
- #define MAINBOARD_POWER_OFF	0
--- 
-1.9.1
-
diff --git a/resources/libreboot/patch/0008-mainboards-lenovo-t400-Enable-serial-debug-option-fo.patch b/resources/libreboot/patch/0002-mainboards-lenovo-t400-Enable-serial-debug-option-fo.patch
index aeda457..d0030a9 100644
--- a/resources/libreboot/patch/0008-mainboards-lenovo-t400-Enable-serial-debug-option-fo.patch
+++ b/resources/libreboot/patch/0002-mainboards-lenovo-t400-Enable-serial-debug-option-fo.patch
@@ -1,7 +1,7 @@
-From fa064bbdca26d7fb9241f9414200fe39e65c2f58 Mon Sep 17 00:00:00 2001
+From afd81dfadb70b6b4357fab2842b0ac62e48623a1 Mon Sep 17 00:00:00 2001
 From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Sun, 5 Apr 2015 17:58:01 -0500
-Subject: [PATCH 08/22] mainboards/lenovo/t400: Enable serial debug option for
+Subject: [PATCH 02/17] mainboards/lenovo/t400: Enable serial debug option for
  use with dock
 
 Change-Id: I93fcc8147586c7ca32d4805579f4185cad3d61db
@@ -11,7 +11,7 @@ Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
  1 file changed, 1 deletion(-)
 
 diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig
-index 392ce692..a38af5e 100644
+index e410f20..a1d0652 100644
 --- a/src/mainboard/lenovo/t400/Kconfig
 +++ b/src/mainboard/lenovo/t400/Kconfig
 @@ -8,7 +8,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
diff --git a/resources/libreboot/patch/0002-northbridge-intel-gm45-gma-Add-backlight-control-reg.patch b/resources/libreboot/patch/0002-northbridge-intel-gm45-gma-Add-backlight-control-reg.patch
deleted file mode 100644
index 6be1246..0000000
--- a/resources/libreboot/patch/0002-northbridge-intel-gm45-gma-Add-backlight-control-reg.patch
+++ /dev/null
@@ -1,61 +0,0 @@
-From 9f3557bfdc06fc87e50f39336fe24a4c599a5c5d Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <tpearson@raptorengineeringinc.com>
-Date: Mon, 6 Apr 2015 22:01:23 -0500
-Subject: [PATCH 02/22] northbridge/intel/gm45/gma: Add backlight control
- register field
-
-This allows the backlight control register to be set via devicetree.cb
-
-Change-Id: I32b42dfc1cc609fb6f8995c6158c85be67633770
-Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
----
- src/drivers/intel/gma/i915.h     | 1 +
- src/northbridge/intel/gm45/gma.c | 8 ++++++--
- 2 files changed, 7 insertions(+), 2 deletions(-)
-
-diff --git a/src/drivers/intel/gma/i915.h b/src/drivers/intel/gma/i915.h
-index 0d5b8af..36ac5fc 100644
---- a/src/drivers/intel/gma/i915.h
-+++ b/src/drivers/intel/gma/i915.h
-@@ -291,6 +291,7 @@ struct i915_gpu_controller_info
- 	int lvds_dual_channel;
- 	int link_frequency_270_mhz;
- 	int lvds_num_lanes;
-+	u32 backlight;
- };
- 
- int i915lightup(unsigned int physbase, unsigned int mmio,
-diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c
-index 4cf2776..b08422a 100644
---- a/src/northbridge/intel/gm45/gma.c
-+++ b/src/northbridge/intel/gm45/gma.c
-@@ -446,12 +446,13 @@ static void gma_func0_init(struct device *dev)
- 	/* Init graphics power management */
- 	gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);
- 
-+	struct northbridge_intel_gm45_config *conf = dev->chip_info;
-+
- #if !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
- 	/* PCI Init, will run VBIOS */
- 	pci_dev_init(dev);
- #else
- 	u32 physbase;
--	struct northbridge_intel_gm45_config *conf = dev->chip_info;
- 	struct resource *lfb_res;
- 	struct resource *pio_res;
- 
-@@ -475,7 +476,10 @@ static void gma_func0_init(struct device *dev)
- 	/* Post VBIOS init */
- 	/* Enable Backlight  */
- 	gtt_write(BLC_PWM_CTL2, (1 << 31));
--	gtt_write(BLC_PWM_CTL, 0x06100610);
-+	if (conf->gfx.backlight == 0)
-+		gtt_write(BLC_PWM_CTL, 0x06100610);
-+	else
-+		gtt_write(BLC_PWM_CTL, conf->gfx.backlight);
- }
- 
- static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)
--- 
-1.9.1
-
diff --git a/resources/libreboot/patch/0009-mainboard-lenovo-t400-Add-initial-hybrid-graphics-su.patch b/resources/libreboot/patch/0003-mainboard-lenovo-t400-Add-initial-hybrid-graphics-su.patch
index f76926b..ad75319 100644
--- a/resources/libreboot/patch/0009-mainboard-lenovo-t400-Add-initial-hybrid-graphics-su.patch
+++ b/resources/libreboot/patch/0003-mainboard-lenovo-t400-Add-initial-hybrid-graphics-su.patch
@@ -1,7 +1,7 @@
-From 76a977c5fb717315154317ea4ccb0d46b329731a Mon Sep 17 00:00:00 2001
+From bbf3462e7442c2cae568e147d3f0eb1195f86991 Mon Sep 17 00:00:00 2001
 From: Timothy Pearson <tpearson@raptorengineeringinc.com>
 Date: Sun, 5 Apr 2015 18:10:09 -0500
-Subject: [PATCH 09/22] mainboard/lenovo/t400: Add initial hybrid graphics
+Subject: [PATCH 03/17] mainboard/lenovo/t400: Add initial hybrid graphics
  support
 
 TEST: Booted T400 with Intel/ATI hybrid graphics in integrated
@@ -27,10 +27,10 @@ index 67b8920..06eec57 100644
 +hybrid_graphics_mode=Integrated Only
 \ No newline at end of file
 diff --git a/src/mainboard/lenovo/t400/cmos.layout b/src/mainboard/lenovo/t400/cmos.layout
-index fbb2293..687b284 100644
+index 2dc91bf..44f5d04 100644
 --- a/src/mainboard/lenovo/t400/cmos.layout
 +++ b/src/mainboard/lenovo/t400/cmos.layout
-@@ -86,7 +86,10 @@ entries
+@@ -85,7 +85,10 @@ entries
  # coreboot config options: northbridge
  941         3       e       11       gfx_uma_size
  
@@ -42,7 +42,7 @@ index fbb2293..687b284 100644
  
  # coreboot config options: check sums
  984          16       h       0        check_sum
-@@ -138,6 +141,9 @@ enumerations
+@@ -137,6 +140,9 @@ enumerations
  11    3     128M
  11    5     96M
  11    6     160M
@@ -53,7 +53,7 @@ index fbb2293..687b284 100644
  # -----------------------------------------------------------------
  checksums
 diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c
-index 5f50f32..20071c0 100644
+index a739d18..c62df60 100644
 --- a/src/mainboard/lenovo/t400/romstage.c
 +++ b/src/mainboard/lenovo/t400/romstage.c
 @@ -1,6 +1,7 @@
@@ -64,7 +64,7 @@ index 5f50f32..20071c0 100644
   * Copyright (C) 2012 secunet Security Networks AG
   *
   * This program is free software; you can redistribute it and/or
-@@ -38,6 +39,118 @@
+@@ -37,6 +38,118 @@
  #define LPC_DEV PCI_DEV(0, 0x1f, 0)
  #define MCH_DEV PCI_DEV(0, 0, 0)
  
@@ -183,7 +183,7 @@ index 5f50f32..20071c0 100644
  static void default_southbridge_gpio_setup(void)
  {
  	outl(0x197e23fe, DEFAULT_GPIOBASE + GP_IO_USE_SEL);
-@@ -99,6 +212,31 @@ void main(unsigned long bist)
+@@ -98,6 +211,31 @@ void main(unsigned long bist)
  
  	default_southbridge_gpio_setup();
  
@@ -215,7 +215,7 @@ index 5f50f32..20071c0 100644
  	/* ASPM related setting, set early by original BIOS. */
  	DMIBAR16(0x204) &= ~(3 << 10);
  
-@@ -178,6 +316,11 @@ void main(unsigned long bist)
+@@ -177,6 +315,11 @@ void main(unsigned long bist)
  	outl(inl(DEFAULT_GPIOBASE + 0x38) & ~0x400, DEFAULT_GPIOBASE + 0x38);
  
  	cbmem_initted = !cbmem_recovery(s3resume);
diff --git a/resources/libreboot/patch/0003-northbridge-intel-gm45-gma-Minor-cleanup.patch b/resources/libreboot/patch/0003-northbridge-intel-gm45-gma-Minor-cleanup.patch
deleted file mode 100644
index f98f09e..0000000
--- a/resources/libreboot/patch/0003-northbridge-intel-gm45-gma-Minor-cleanup.patch
+++ /dev/null
@@ -1,63 +0,0 @@
-From 9b8322db70364aae21f05755b62a58695ade0a82 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <tpearson@raptorengineeringinc.com>
-Date: Mon, 6 Apr 2015 21:54:56 -0500
-Subject: [PATCH 03/22] northbridge/intel/gm45/gma: Minor cleanup
-
-1.) Removed invalid set of TRANS_STATE_MASK bit
-2.) Used i915 register defines to clarify code
-
-Change-Id: I08d016e9d66b5eeea8f2174abaa35a98e2b4eca3
-Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
----
- src/northbridge/intel/gm45/gma.c | 13 +++++--------
- 1 file changed, 5 insertions(+), 8 deletions(-)
-
-diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c
-index b08422a..c71b8b2 100644
---- a/src/northbridge/intel/gm45/gma.c
-+++ b/src/northbridge/intel/gm45/gma.c
-@@ -134,9 +134,9 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
- 		outl(physbase + (i << 12) + 1, piobase + 4);
- 	}
- 
--	write32(mmio + 0x61100, 0x40008c18);
-+	write32(mmio + ADPA, 0x40008c18);
- 	write32(mmio + 0x7041c, 0x0);
--	write32(mmio + 0x6020, 0x3);
-+	write32(mmio + _DPLL_B_MD, 0x3);
- 
- 	vga_misc_write(0x67);
- 
-@@ -174,9 +174,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
- 
- 	target_frequency = info->gfx.lvds_dual_channel ? edid.pixel_clock
- 		: (2 * edid.pixel_clock);
--#if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
--	vga_textmode_init();
--#else
-+#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
- 	vga_sr_write(1, 1);
- 	vga_sr_write(0x2, 0xf);
- 	vga_sr_write(0x3, 0x0);
-@@ -200,6 +198,8 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
- 	write32(mmio + DSPSURF(0), 0);
- 	for (i = 0; i < 0x100; i++)
- 		write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101);
-+#else
-+	vga_textmode_init();
- #endif
- 
- 	/* Find suitable divisors.  */
-@@ -391,9 +391,6 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
- 	write32(mmio + 0x000f000c, 0xb01a2050);
- 	mdelay(1);
- 	write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC
--#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
--		| TRANS_STATE_MASK
--#endif
- 		);
- 	write32(mmio + LVDS,
- 		LVDS_PORT_ENABLE
--- 
-1.9.1
-
diff --git a/resources/libreboot/patch/0012-NOTFORMERGE-lenovo-t400-hard-code-enable-integrated-.patch b/resources/libreboot/patch/0004-NOTFORMERGE-lenovo-t400-hard-code-enable-integrated-.patch
index 7b73027..bd5cf69 100644
--- a/resources/libreboot/patch/0012-NOTFORMERGE-lenovo-t400-hard-code-enable-integrated-.patch
+++ b/resources/libreboot/patch/0004-NOTFORMERGE-lenovo-t400-hard-code-enable-integrated-.patch
@@ -1,7 +1,7 @@
-From bdcc0135ef189c778161607be157aded94f9e1b4 Mon Sep 17 00:00:00 2001
+From 959c74de0ecd066c9d241b784aa280dadc43bb1e Mon Sep 17 00:00:00 2001
 From: Francis Rowe <info@gluglug.org.uk>
-Date: Mon, 4 May 2015 14:40:18 +0100
-Subject: [PATCH 12/22] NOTFORMERGE: lenovo/t400: hard-code enable
+Date: Mon, 15 Jun 2015 03:44:15 +0100
+Subject: [PATCH 04/17] NOTFORMERGE: lenovo/t400: hard-code enable
  integrated-only video
 
 Written with libreboot in mind. Libreboot uses native graphics
@@ -11,23 +11,23 @@ only use the integrated (Intel) GPU for which native init exists.
 Native graphics initialization does not yet exist for the ATI GPUs
 on these laptops...
 
-Change-Id: I2eae4b6eb05a6d9e188cfca84692f6a8b5d67090
+Change-Id: I2c056a8fb498972f87c4ec1122b239fdc9a4c666
 Signed-off-by: Francis Rowe <info@gluglug.org.uk>
 ---
  src/mainboard/lenovo/t400/romstage.c | 3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)
 
 diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c
-index 20071c0..ad9e749 100644
+index c62df60..daf6fa8 100644
 --- a/src/mainboard/lenovo/t400/romstage.c
 +++ b/src/mainboard/lenovo/t400/romstage.c
-@@ -213,7 +213,8 @@ void main(unsigned long bist)
+@@ -212,7 +212,8 @@ void main(unsigned long bist)
  	default_southbridge_gpio_setup();
  
  	uint8_t hybrid_graphics_mode = HYBRID_GRAPHICS_INTEGRATED_ONLY;
 -	get_option(&hybrid_graphics_mode, "hybrid_graphics_mode");
 +	/* Not for merge! Hard-code enable integrated-only by commenting this line: */
-+	/* get_option(&hybrid_graphics_mode, "hybrid_graphics_mode"); */
++	/* get_option(&hybrid_graphics_mode, "hybrid_graphics_mode");  */
  
  	/* Set up hybrid graphics */
  	hybrid_graphics_set_up_gpio();
diff --git a/resources/libreboot/patch/0013-lenovo-x60-Enable-text-mode-native-gfx-init.patch b/resources/libreboot/patch/0005-lenovo-x60-Enable-VESA-framebuffer-mode-native-graph.patch
index 691c30d..046a775 100644
--- a/resources/libreboot/patch/0013-lenovo-x60-Enable-text-mode-native-gfx-init.patch
+++ b/resources/libreboot/patch/0005-lenovo-x60-Enable-VESA-framebuffer-mode-native-graph.patch
@@ -1,10 +1,15 @@
-From e1a421df8add1b976ee9bd001c88fbc95900e1f3 Mon Sep 17 00:00:00 2001
-From: Vladimir Serbinenko <phcoder@gmail.com>
-Date: Thu, 21 Aug 2014 02:25:59 +0200
-Subject: [PATCH 13/22] lenovo/x60: Enable text mode native gfx init
+From 35dbc64845f9624f6629f400dbd4b6d502baf398 Mon Sep 17 00:00:00 2001
+From: Francis Rowe <info@gluglug.org.uk>
+Date: Mon, 15 Jun 2015 20:08:06 +0100
+Subject: [PATCH 05/17] lenovo/x60: Enable VESA framebuffer mode (native
+ graphics)
 
-Change-Id: I3aad96a7034c73e447cf8995473a45ffd3893f3f
-Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
+At present, no option exists for "Keep VESA framebuffer", which
+means that text-mode will be used. Add the appropriate Kconfig
+option.
+
+Change-Id: Iaed07eba6d9288c857f7e7a0b0be1107071e49e5
+Signed-off-by: Francis Rowe <info@gluglug.org.uk>
 ---
  src/mainboard/lenovo/x60/Kconfig | 1 +
  1 file changed, 1 insertion(+)
diff --git a/resources/libreboot/patch/0005-mainboard-lenovo-x200-Use-defines-from-southbridge-f.patch b/resources/libreboot/patch/0005-mainboard-lenovo-x200-Use-defines-from-southbridge-f.patch
deleted file mode 100644
index 1c659e8..0000000
--- a/resources/libreboot/patch/0005-mainboard-lenovo-x200-Use-defines-from-southbridge-f.patch
+++ /dev/null
@@ -1,49 +0,0 @@
-From 654222e8ccc7bf3e7d222a16aaeb3d5e2846b0d9 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <tpearson@raptorengineeringinc.com>
-Date: Mon, 6 Apr 2015 03:41:28 -0500
-Subject: [PATCH 05/22] mainboard/lenovo/x200: Use defines from southbridge for
- GPIO config
-
-Change-Id: I9f65922d0785e06a173221b3262e73b575087dfd
-Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
----
- src/mainboard/lenovo/x200/romstage.c | 16 ++++++++--------
- 1 file changed, 8 insertions(+), 8 deletions(-)
-
-diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c
-index f232642..5f50f32 100644
---- a/src/mainboard/lenovo/x200/romstage.c
-+++ b/src/mainboard/lenovo/x200/romstage.c
-@@ -40,21 +40,21 @@
- 
- static void default_southbridge_gpio_setup(void)
- {
--	outl(0x197e23fe, DEFAULT_GPIOBASE + 0x00);
--	outl(0xe1a66dfe, DEFAULT_GPIOBASE + 0x04);
--	outl(0xe3faef3f, DEFAULT_GPIOBASE + 0x0c);
-+	outl(0x197e23fe, DEFAULT_GPIOBASE + GP_IO_USE_SEL);
-+	outl(0xe1a66dfe, DEFAULT_GPIOBASE + GP_IO_SEL);
-+	outl(0xe3faef3f, DEFAULT_GPIOBASE + GP_LVL);
- 
- 	/* Disable blink [31:0]. */
--	outl(0x00000000, DEFAULT_GPIOBASE + 0x18);
-+	outl(0x00000000, DEFAULT_GPIOBASE + GPO_BLINK);
- 	/* Set input inversion [31:0]. */
--	outl(0x00000102, DEFAULT_GPIOBASE + 0x2c);
-+	outl(0x00000102, DEFAULT_GPIOBASE + GPI_INV);
- 
- 	/* Enable GPIOs [60:32]. */
--	outl(0x030306f6, DEFAULT_GPIOBASE + 0x30);
-+	outl(0x030306f6, DEFAULT_GPIOBASE + GP_IO_USE_SEL2);
- 	/* Set input/output mode [60:32] (0 == out, 1 == in). */
--	outl(0x1f55f9f1, DEFAULT_GPIOBASE + 0x34);
-+	outl(0x1f55f9f1, DEFAULT_GPIOBASE + GP_IO_SEL2);
- 	/* Set gpio levels [60:32].  */
--	outl(0x1dffff53, DEFAULT_GPIOBASE + 0x38);
-+	outl(0x1dffff53, DEFAULT_GPIOBASE + GP_LVL2);
- }
- 
- static void early_lpc_setup(void)
--- 
-1.9.1
-
diff --git a/resources/libreboot/patch/0014-lenovo-x60-Enable-legacy-brightness-controls-native-.patch b/resources/libreboot/patch/0006-lenovo-x60-Enable-brightness-controls-native-graphic.patch
index 1c5b4b3..8e03471 100644
--- a/resources/libreboot/patch/0014-lenovo-x60-Enable-legacy-brightness-controls-native-.patch
+++ b/resources/libreboot/patch/0006-lenovo-x60-Enable-brightness-controls-native-graphic.patch
@@ -1,10 +1,17 @@
-From 89f4c7561e486030d867674e4df2978a7260c4a7 Mon Sep 17 00:00:00 2001
+From 30b0666a7d2b0d8265433cb308ed1bbbabd10674 Mon Sep 17 00:00:00 2001
 From: Francis Rowe <info@gluglug.org.uk>
 Date: Sat, 11 Oct 2014 16:43:28 +0100
-Subject: [PATCH 14/22] lenovo/x60: Enable legacy brightness controls (native
+Subject: [PATCH 06/17] lenovo/x60: Enable brightness controls (native
  graphics)
 
-Value obtained by reading BLC_PWM_CTL when running the VBIOS (option ROM).
+This makes the Fn Home/End keys work for controlling the
+brightness of the display. Value obtained by reading
+BLC_PWM_CTL when running the VBIOS (option ROM).
+
+On i945 legacy brightness control is enabled by a single
+bit in BLC_PWM_CTL. It's bit 16 or bit 0 (the other one
+reverses polarity). Set the bit to enable brightness
+controls.
 
 Change-Id: Id855c4e91fe71fb489739e62fbe99ca22841acd2
 Signed-off-by: Francis Rowe <info@gluglug.org.uk>
@@ -13,10 +20,10 @@ Signed-off-by: Francis Rowe <info@gluglug.org.uk>
  1 file changed, 1 insertion(+), 1 deletion(-)
 
 diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb
-index 382ebaf..4e02d3c 100644
+index a3d31a6..9c3c524 100644
 --- a/src/mainboard/lenovo/x60/devicetree.cb
 +++ b/src/mainboard/lenovo/x60/devicetree.cb
-@@ -25,7 +25,7 @@ chip northbridge/intel/i945
+@@ -27,7 +27,7 @@ chip northbridge/intel/i945
  	register "gpu_hotplug" = "0x00000220"
  	register "gpu_lvds_use_spread_spectrum_clock" = "1"
  	register "gpu_lvds_is_dual_channel" = "0"
diff --git a/resources/libreboot/patch/0006-mainboard-lenovo-x200-Add-power_on_after_fail-NVRAM-.patch b/resources/libreboot/patch/0006-mainboard-lenovo-x200-Add-power_on_after_fail-NVRAM-.patch
deleted file mode 100644
index 6636eb3..0000000
--- a/resources/libreboot/patch/0006-mainboard-lenovo-x200-Add-power_on_after_fail-NVRAM-.patch
+++ /dev/null
@@ -1,76 +0,0 @@
-From 7f23259568c9afb01e22e24ae7ae8e201cb89445 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <tpearson@raptorengineeringinc.com>
-Date: Mon, 6 Apr 2015 22:12:47 -0500
-Subject: [PATCH 06/22] mainboard/lenovo/x200: Add power_on_after_fail NVRAM
- option
-
-Change-Id: I8e78cbae132566b6ca27e0a68af2656364c82b8f
-Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
----
- src/mainboard/lenovo/x200/cmos.default |  1 +
- src/mainboard/lenovo/x200/cmos.layout  | 29 +++++++++++++++--------------
- 2 files changed, 16 insertions(+), 14 deletions(-)
-
-diff --git a/src/mainboard/lenovo/x200/cmos.default b/src/mainboard/lenovo/x200/cmos.default
-index 1da4c7c..67b8920 100644
---- a/src/mainboard/lenovo/x200/cmos.default
-+++ b/src/mainboard/lenovo/x200/cmos.default
-@@ -2,6 +2,7 @@ boot_option=Fallback
- last_boot=Fallback
- baud_rate=115200
- debug_level=Spew
-+power_on_after_fail=Disable
- volume=0x3
- first_battery=Primary
- bluetooth=Enable
-diff --git a/src/mainboard/lenovo/x200/cmos.layout b/src/mainboard/lenovo/x200/cmos.layout
-index 57dd4d1..fbb2293 100644
---- a/src/mainboard/lenovo/x200/cmos.layout
-+++ b/src/mainboard/lenovo/x200/cmos.layout
-@@ -64,28 +64,29 @@ entries
- 
- # coreboot config options: southbridge
- 408         1       e       10        sata_mode
-+409         2       e       7         power_on_after_fail
- 
- # coreboot config options: EC
--409         1       e       9        first_battery
--410         1       e       1        bluetooth
--411         1       e       1        wwan
--412         1       e       1        wlan
--413         1       e       1        trackpoint
--414         1       e       1        fn_ctrl_swap
--415         1       e       1        sticky_fn
-+411         1       e       9        first_battery
-+412         1       e       1        bluetooth
-+413         1       e       1        wwan
-+414         1       e       1        wlan
-+415         1       e       1        trackpoint
-+416         1       e       1        fn_ctrl_swap
-+417         1       e       1        sticky_fn
- 
- # coreboot config options: bootloader
--416         512       s       0        boot_devices
--928           8       h       0        boot_default
-+418         512       s       0        boot_devices
-+930           8       h       0        boot_default
- 
--936         1       e       1        power_management_beeps
--937         1       e       1        low_battery_beep
--938         1       e       1        uwb
-+938         1       e       1        power_management_beeps
-+939         1       e       1        low_battery_beep
-+940         1       e       1        uwb
- 
- # coreboot config options: northbridge
--939         3       e       11       gfx_uma_size
-+941         3       e       11       gfx_uma_size
- 
--#942          2       r       0        unused
-+#944          2       r       0        unused
- 
- # coreboot config options: check sums
- 984          16       h       0        check_sum
--- 
-1.9.1
-
diff --git a/resources/libreboot/patch/0015-lenovo-t60-Enable-native-intel-gfx-init.patch b/resources/libreboot/patch/0007-lenovo-t60-Enable-native-intel-gfx-init.patch
index f54094a..0c209e0 100644
--- a/resources/libreboot/patch/0015-lenovo-t60-Enable-native-intel-gfx-init.patch
+++ b/resources/libreboot/patch/0007-lenovo-t60-Enable-native-intel-gfx-init.patch
@@ -1,7 +1,7 @@
-From 5a762600dd0d41c1f1f24dfccea62d9cefb5b3d6 Mon Sep 17 00:00:00 2001
+From 64106428f6739ed87392f59993f3e0f1a3f045c8 Mon Sep 17 00:00:00 2001
 From: Vladimir Serbinenko <phcoder@gmail.com>
 Date: Tue, 4 Mar 2014 18:08:26 +0100
-Subject: [PATCH 15/22] lenovo/t60: Enable native intel gfx init.
+Subject: [PATCH 07/17] lenovo/t60: Enable native intel gfx init.
 
 Tested on T60 with intel graphics.
 
@@ -29,12 +29,12 @@ index 0cf19a1..2254185 100644
  	string
  	default lenovo/t60
 diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb
-index bca0787..a0ee7f9 100644
+index 719fa9a..fdced26 100644
 --- a/src/mainboard/lenovo/t60/devicetree.cb
 +++ b/src/mainboard/lenovo/t60/devicetree.cb
-@@ -22,6 +22,11 @@
- 
- chip northbridge/intel/i945
+@@ -24,6 +24,11 @@ chip northbridge/intel/i945
+ 	register "gfx.ndid" = "3"
+ 	register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
  
 +	register "gpu_hotplug" = "0x00000220"
 +	register "gpu_lvds_use_spread_spectrum_clock" = "1"
diff --git a/resources/libreboot/patch/0007-mainboards-lenovo-Copy-X200-board-to-T400-for-future.patch b/resources/libreboot/patch/0007-mainboards-lenovo-Copy-X200-board-to-T400-for-future.patch
deleted file mode 100644
index 3567945..0000000
--- a/resources/libreboot/patch/0007-mainboards-lenovo-Copy-X200-board-to-T400-for-future.patch
+++ /dev/null
@@ -1,2014 +0,0 @@
-From ad570a63a5bcf9d461158edac71603e2f1eee830 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <tpearson@raptorengineeringinc.com>
-Date: Sun, 5 Apr 2015 17:54:08 -0500
-Subject: [PATCH 07/22] mainboards/lenovo: Copy X200 board to T400 for future
- expansion
-
-Change-Id: If2d48b84fe7bd7b144e96171e54067891e3c4e2e
-Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
----
- src/mainboard/lenovo/Kconfig                     |   6 +
- src/mainboard/lenovo/t400/Kconfig                |  49 ++++++
- src/mainboard/lenovo/t400/Makefile.inc           |  20 +++
- src/mainboard/lenovo/t400/acpi/dock.asl          |  73 ++++++++
- src/mainboard/lenovo/t400/acpi/ec.asl            |   1 +
- src/mainboard/lenovo/t400/acpi/gm45_pci_irqs.asl |  86 ++++++++++
- src/mainboard/lenovo/t400/acpi/gpe.asl           |  29 ++++
- src/mainboard/lenovo/t400/acpi/ich9_pci_irqs.asl | 110 ++++++++++++
- src/mainboard/lenovo/t400/acpi/platform.asl      | 206 +++++++++++++++++++++++
- src/mainboard/lenovo/t400/acpi/superio.asl       |   0
- src/mainboard/lenovo/t400/acpi_tables.c          |  91 ++++++++++
- src/mainboard/lenovo/t400/board_info.txt         |   5 +
- src/mainboard/lenovo/t400/cmos.default           |  16 ++
- src/mainboard/lenovo/t400/cmos.layout            | 146 ++++++++++++++++
- src/mainboard/lenovo/t400/cstates.c              |  41 +++++
- src/mainboard/lenovo/t400/devicetree.cb          | 203 ++++++++++++++++++++++
- src/mainboard/lenovo/t400/dock.c                 |  65 +++++++
- src/mainboard/lenovo/t400/dock.h                 |  26 +++
- src/mainboard/lenovo/t400/dsdt.asl               |  59 +++++++
- src/mainboard/lenovo/t400/fadt.c                 | 158 +++++++++++++++++
- src/mainboard/lenovo/t400/hda_verb.c             |  51 ++++++
- src/mainboard/lenovo/t400/mainboard.c            |  70 ++++++++
- src/mainboard/lenovo/t400/mptable.c              |   1 +
- src/mainboard/lenovo/t400/romstage.c             | 205 ++++++++++++++++++++++
- src/mainboard/lenovo/t400/smihandler.c           |  75 +++++++++
- 25 files changed, 1792 insertions(+)
- create mode 100644 src/mainboard/lenovo/t400/Kconfig
- create mode 100644 src/mainboard/lenovo/t400/Makefile.inc
- create mode 100644 src/mainboard/lenovo/t400/acpi/dock.asl
- create mode 100644 src/mainboard/lenovo/t400/acpi/ec.asl
- create mode 100644 src/mainboard/lenovo/t400/acpi/gm45_pci_irqs.asl
- create mode 100644 src/mainboard/lenovo/t400/acpi/gpe.asl
- create mode 100644 src/mainboard/lenovo/t400/acpi/ich9_pci_irqs.asl
- create mode 100644 src/mainboard/lenovo/t400/acpi/platform.asl
- create mode 100644 src/mainboard/lenovo/t400/acpi/superio.asl
- create mode 100644 src/mainboard/lenovo/t400/acpi_tables.c
- create mode 100644 src/mainboard/lenovo/t400/board_info.txt
- create mode 100644 src/mainboard/lenovo/t400/cmos.default
- create mode 100644 src/mainboard/lenovo/t400/cmos.layout
- create mode 100644 src/mainboard/lenovo/t400/cstates.c
- create mode 100644 src/mainboard/lenovo/t400/devicetree.cb
- create mode 100644 src/mainboard/lenovo/t400/dock.c
- create mode 100644 src/mainboard/lenovo/t400/dock.h
- create mode 100644 src/mainboard/lenovo/t400/dsdt.asl
- create mode 100644 src/mainboard/lenovo/t400/fadt.c
- create mode 100644 src/mainboard/lenovo/t400/hda_verb.c
- create mode 100644 src/mainboard/lenovo/t400/mainboard.c
- create mode 100644 src/mainboard/lenovo/t400/mptable.c
- create mode 100644 src/mainboard/lenovo/t400/romstage.c
- create mode 100644 src/mainboard/lenovo/t400/smihandler.c
-
-diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig
-index 95f7cfd..b6da044 100644
---- a/src/mainboard/lenovo/Kconfig
-+++ b/src/mainboard/lenovo/Kconfig
-@@ -32,6 +32,11 @@ config BOARD_LENOVO_X230
- 	help
- 	  Lenovo X230 laptop. Consult wiki for details.
- 
-+config BOARD_LENOVO_T400
-+	bool "ThinkPad T400"
-+	help
-+	  Lenovo T400 laptop. Consult wiki for details.
-+
- config BOARD_LENOVO_T420S
- 	bool "ThinkPad T420s"
- 	help
-@@ -72,6 +77,7 @@ source "src/mainboard/lenovo/x200/Kconfig"
- source "src/mainboard/lenovo/x201/Kconfig"
- source "src/mainboard/lenovo/x220/Kconfig"
- source "src/mainboard/lenovo/x230/Kconfig"
-+source "src/mainboard/lenovo/t400/Kconfig"
- source "src/mainboard/lenovo/t420s/Kconfig"
- source "src/mainboard/lenovo/t430s/Kconfig"
- source "src/mainboard/lenovo/t520/Kconfig"
-diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig
-new file mode 100644
-index 0000000..392ce692
---- /dev/null
-+++ b/src/mainboard/lenovo/t400/Kconfig
-@@ -0,0 +1,49 @@
-+if BOARD_LENOVO_T400
-+
-+config BOARD_SPECIFIC_OPTIONS # dummy
-+	def_bool y
-+	select SYSTEM_TYPE_LAPTOP
-+	select CPU_INTEL_SOCKET_BGA956
-+	select NORTHBRIDGE_INTEL_GM45
-+	select SOUTHBRIDGE_INTEL_I82801IX
-+	select EC_LENOVO_PMH7
-+	select EC_LENOVO_H8
-+	select NO_UART_ON_SUPERIO
-+	select DRIVERS_ICS_954309
-+	select BOARD_ROMSIZE_KB_8192
-+	select DRIVERS_GENERIC_IOAPIC
-+	select HAVE_MP_TABLE
-+	select HAVE_ACPI_TABLES
-+	select EC_ACPI
-+	select HAVE_OPTION_TABLE
-+	select HAVE_CMOS_DEFAULT
-+	select HAVE_ACPI_RESUME
-+	select MAINBOARD_HAS_NATIVE_VGA_INIT
-+	select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG
-+	select INTEL_INT15
-+
-+config MAINBOARD_DIR
-+	string
-+	default lenovo/t400
-+
-+config MAINBOARD_PART_NUMBER
-+	string
-+	default "ThinkPad T400"
-+
-+config MMCONF_BASE_ADDRESS
-+	hex
-+	default 0xf0000000
-+
-+config USBDEBUG_HCD_INDEX
-+	int
-+	default 2
-+
-+config MAX_CPUS
-+	int
-+	default 2
-+
-+config CBFS_SIZE
-+	hex
-+	default 0x200000
-+
-+endif # BOARD_LENOVO_T400
-diff --git a/src/mainboard/lenovo/t400/Makefile.inc b/src/mainboard/lenovo/t400/Makefile.inc
-new file mode 100644
-index 0000000..4eb1216
---- /dev/null
-+++ b/src/mainboard/lenovo/t400/Makefile.inc
-@@ -0,0 +1,20 @@
-+##
-+## This file is part of the coreboot project.
-+##
-+## Copyright (C) 2012 secunet Security Networks AG
-+##
-+## This program is free software; you can redistribute it and/or modify
-+## it under the terms of the GNU General Public License as published by
-+## the Free Software Foundation; version 2 of the License.
-+##
-+## This program is distributed in the hope that it will be useful,
-+## but WITHOUT ANY WARRANTY; without even the implied warranty of
-+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+## GNU General Public License for more details.
-+##
-+## You should have received a copy of the GNU General Public License
-+## along with this program; if not, write to the Free Software
-+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-+##
-+
-+ramstage-y += dock.c
-diff --git a/src/mainboard/lenovo/t400/acpi/dock.asl b/src/mainboard/lenovo/t400/acpi/dock.asl
-new file mode 100644
-index 0000000..605836b
---- /dev/null
-+++ b/src/mainboard/lenovo/t400/acpi/dock.asl
-@@ -0,0 +1,73 @@
-+/*
-+ * This file is part of the coreboot project.
-+ *
-+ * Copyright (c) 2011 Sven Schnelle <svens@stackframe.org>
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; version 2 of
-+ * the License.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
-+ * MA 02110-1301 USA
-+ */
-+
-+Scope (\_SB)
-+{
-+	Device(DOCK)
-+	{
-+		Name(_HID, "ACPI0003")
-+		Name(_UID, 0x00)
-+		Name(_PCL, Package() { \_SB } )
-+
-+		Method(_DCK, 1, NotSerialized)
-+		{
-+			if (Arg0) {
-+			   /* connect dock */
-+			   Store (1, \GP28)
-+			   Store (1, \_SB.PCI0.LPCB.EC.DKR1)
-+			} else {
-+			   /* disconnect dock */
-+			   Store (0, \GP28)
-+			   Store (0, \_SB.PCI0.LPCB.EC.DKR1)
-+			}
-+			Xor(Arg0, \_SB.PCI0.LPCB.EC.DKR1, Local0)
-+			Return (Local0)
-+		}
-+
-+		Method(_STA, 0, NotSerialized)
-+		{
-+			Return (\_SB.PCI0.LPCB.EC.DKR1)
-+		}
-+	}
-+}
-+
-+Scope(\_SB.PCI0.LPCB.EC)
-+{
-+	Method(_Q18, 0, NotSerialized)
-+	{
-+		Notify(\_SB.DOCK, 3)
-+	}
-+
-+	Method(_Q45, 0, NotSerialized)
-+	{
-+		Notify(\_SB.DOCK, 3)
-+	}
-+
-+	Method(_Q58, 0, NotSerialized)
-+	{
-+		Notify(\_SB.DOCK, 0)
-+	}
-+
-+	Method(_Q37, 0, NotSerialized)
-+	{
-+		Notify(\_SB.DOCK, 0)
-+	}
-+}
-diff --git a/src/mainboard/lenovo/t400/acpi/ec.asl b/src/mainboard/lenovo/t400/acpi/ec.asl
-new file mode 100644
-index 0000000..c3569e8
---- /dev/null
-+++ b/src/mainboard/lenovo/t400/acpi/ec.asl
-@@ -0,0 +1 @@
-+#include <ec/lenovo/h8/acpi/ec.asl>
-diff --git a/src/mainboard/lenovo/t400/acpi/gm45_pci_irqs.asl b/src/mainboard/lenovo/t400/acpi/gm45_pci_irqs.asl
-new file mode 100644
-index 0000000..83c7762
---- /dev/null
-+++ b/src/mainboard/lenovo/t400/acpi/gm45_pci_irqs.asl
-@@ -0,0 +1,86 @@
-+/*
-+ * This file is part of the coreboot project.
-+ *
-+ * Copyright (C) 2007-2009 coresystems GmbH
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; version 2 of
-+ * the License.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
-+ * MA 02110-1301 USA
-+ */
-+
-+/* This is board specific information: IRQ routing for the
-+ * gm45
-+ */
-+
-+
-+// PCI Interrupt Routing
-+Method(_PRT)
-+{
-+	If (PICM) {
-+		Return (Package() {
-+			// PCIe Graphics		0:1.0
-+			Package() { 0x0001ffff, 0, 0, 16 },
-+			// Onboard graphics (IGD)	0:2.0
-+			Package() { 0x0002ffff, 0, 0, 16 },
-+			// USB and EHCI			0:1a.x
-+			Package() { 0x001affff, 0, 0, 16 },
-+			Package() { 0x001affff, 1, 0, 17 },
-+			Package() { 0x001affff, 2, 0, 18 },
-+			// High Definition Audio	0:1b.0
-+			Package() { 0x001bffff, 0, 0, 16 },
-+			// PCIe Root Ports		0:1c.x
-+			Package() { 0x001cffff, 0, 0, 16 },
-+			// USB and EHCI			0:1d.x
-+			Package() { 0x001dffff, 0, 0, 16 },
-+			Package() { 0x001dffff, 1, 0, 17 },
-+			Package() { 0x001dffff, 2, 0, 18 },
-+			// FIXME
-+			// CardBus/IEEE1394		0:1e.2, 0:1e.3
-+			// Package() { 0x001effff, 0, 0, 22 },
-+			// Package() { 0x001effff, 1, 0, 20 },
-+			// LPC device			0:1f.0
-+			Package() { 0x001fffff, 0, 0, 16 },
-+			Package() { 0x001fffff, 1, 0, 17 },
-+			Package() { 0x001fffff, 2, 0, 18 }
-+		})
-+	} Else {
-+		Return (Package() {
-+			// PCIe Graphics		0:1.0
-+			Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
-+			// Onboard graphics (IGD)	0:2.0
-+			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
-+			// USB and EHCI			0:1a.x
-+			Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
-+			Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
-+			Package() { 0x001affff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
-+			// High Definition Audio	0:1b.0
-+			Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
-+			// PCIe Root Ports		0:1c.x
-+			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
-+			// USB and EHCI			0:1d.x
-+			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
-+			Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
-+			Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
-+			// FIXME
-+			// CardBus/IEEE1394		0:1e.2, 0:1e.3
-+			// Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
-+			// Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
-+			// LPC device			0:1f.0
-+			Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
-+			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
-+			Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }
-+		})
-+	}
-+}
-+
-diff --git a/src/mainboard/lenovo/t400/acpi/gpe.asl b/src/mainboard/lenovo/t400/acpi/gpe.asl
-new file mode 100644
-index 0000000..3120caf
---- /dev/null
-+++ b/src/mainboard/lenovo/t400/acpi/gpe.asl
-@@ -0,0 +1,29 @@
-+/*
-+ * This file is part of the coreboot project.
-+ *
-+ * Copyright (c) 2011 Sven Schnelle <svens@stackframe.org>
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; version 2 of
-+ * the License.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
-+ * MA 02110-1301 USA
-+ */
-+
-+Scope (\_GPE)
-+{
-+	Method(_L18, 0, NotSerialized)
-+	{
-+		/* Read EC register to clear wake status */
-+		Store(\_SB.PCI0.LPCB.EC.WAKE, Local0)
-+	}
-+}
-diff --git a/src/mainboard/lenovo/t400/acpi/ich9_pci_irqs.asl b/src/mainboard/lenovo/t400/acpi/ich9_pci_irqs.asl
-new file mode 100644
-index 0000000..325f13c
---- /dev/null
-+++ b/src/mainboard/lenovo/t400/acpi/ich9_pci_irqs.asl
-@@ -0,0 +1,110 @@
-+/*
-+ * This file is part of the coreboot project.
-+ *
-+ * Copyright (C) 2007-2009 coresystems GmbH
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; version 2 of
-+ * the License.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
-+ * MA 02110-1301 USA
-+ */
-+
-+/* This is board specific information: IRQ routing for the
-+ * 0:1e.0 PCI bridge of the ICH9
-+ */
-+
-+/* TODO: which slots are actually relevant? */
-+If (PICM) {
-+	Return (Package() {
-+		// PCI Slot 1 routes ABCD
-+		Package() { 0x0000ffff, 0, 0, 16},
-+		Package() { 0x0000ffff, 1, 0, 17},
-+		Package() { 0x0000ffff, 2, 0, 18},
-+		Package() { 0x0000ffff, 3, 0, 19},
-+
-+		// PCI Slot 2 routes BCDA
-+		Package() { 0x0001ffff, 0, 0, 17},
-+		Package() { 0x0001ffff, 1, 0, 18},
-+		Package() { 0x0001ffff, 2, 0, 19},
-+		Package() { 0x0001ffff, 3, 0, 16},
-+
-+		// PCI Slot 3 routes CDAB
-+		Package() { 0x0002ffff, 0, 0, 18},
-+		Package() { 0x0002ffff, 1, 0, 19},
-+		Package() { 0x0002ffff, 2, 0, 16},
-+		Package() { 0x0002ffff, 3, 0, 17},
-+
-+		// PCI Slot 4 routes ABCD
-+		Package() { 0x0003ffff, 0, 0, 16},
-+		Package() { 0x0003ffff, 1, 0, 17},
-+		Package() { 0x0003ffff, 2, 0, 18},
-+		Package() { 0x0003ffff, 3, 0, 19},
-+
-+		// PCI Slot 5 routes ABCD
-+		Package() { 0x0004ffff, 0, 0, 16},
-+		Package() { 0x0004ffff, 1, 0, 17},
-+		Package() { 0x0004ffff, 2, 0, 18},
-+		Package() { 0x0004ffff, 3, 0, 19},
-+
-+		// PCI Slot 6 routes BCDA
-+		Package() { 0x0005ffff, 0, 0, 17},
-+		Package() { 0x0005ffff, 1, 0, 18},
-+		Package() { 0x0005ffff, 2, 0, 19},
-+		Package() { 0x0005ffff, 3, 0, 16},
-+
-+		// FIXME: what's this supposed to mean? (adopted from ich7)
-+		//Package() { 0x0008ffff, 0, 0, 20},
-+	})
-+} Else {
-+	Return (Package() {
-+		// PCI Slot 1 routes ABCD
-+		Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0},
-+		Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0},
-+		Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0},
-+		Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0},
-+
-+		// PCI Slot 2 routes BCDA
-+		Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKB, 0},
-+		Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKC, 0},
-+		Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKD, 0},
-+		Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKA, 0},
-+
-+		// PCI Slot 3 routes CDAB
-+		Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKC, 0},
-+		Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKD, 0},
-+		Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKA, 0},
-+		Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKB, 0},
-+
-+		// PCI Slot 4 routes ABCD
-+		Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0},
-+		Package() { 0x0003ffff, 1, \_SB.PCI0.LPCB.LNKB, 0},
-+		Package() { 0x0003ffff, 2, \_SB.PCI0.LPCB.LNKC, 0},
-+		Package() { 0x0003ffff, 3, \_SB.PCI0.LPCB.LNKD, 0},
-+
-+		// PCI Slot 5 routes ABCD
-+		Package() { 0x0004ffff, 0, \_SB.PCI0.LPCB.LNKA, 0},
-+		Package() { 0x0004ffff, 1, \_SB.PCI0.LPCB.LNKB, 0},
-+		Package() { 0x0004ffff, 2, \_SB.PCI0.LPCB.LNKC, 0},
-+		Package() { 0x0004ffff, 3, \_SB.PCI0.LPCB.LNKD, 0},
-+
-+		// PCI Slot 6 routes BCDA
-+		Package() { 0x0005ffff, 0, \_SB.PCI0.LPCB.LNKB, 0},
-+		Package() { 0x0005ffff, 1, \_SB.PCI0.LPCB.LNKC, 0},
-+		Package() { 0x0005ffff, 2, \_SB.PCI0.LPCB.LNKD, 0},
-+		Package() { 0x0005ffff, 3, \_SB.PCI0.LPCB.LNKA, 0},
-+
-+		// FIXME
-+		// Package() { 0x0008ffff, 0, \_SB.PCI0.LPCB.LNKE, 0},
-+	})
-+}
-+
-diff --git a/src/mainboard/lenovo/t400/acpi/platform.asl b/src/mainboard/lenovo/t400/acpi/platform.asl
-new file mode 100644
-index 0000000..2aa556f
---- /dev/null
-+++ b/src/mainboard/lenovo/t400/acpi/platform.asl
-@@ -0,0 +1,206 @@
-+/*
-+ * This file is part of the coreboot project.
-+ *
-+ * Copyright (C) 2007-2009 coresystems GmbH
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; version 2 of
-+ * the License.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
-+ * MA 02110-1301 USA
-+ */
-+
-+/* These come from the dynamically created CPU SSDT */
-+External(PDC0)
-+External(PDC1)
-+
-+/* The APM port can be used for generating software SMIs */
-+
-+OperationRegion (APMP, SystemIO, 0xb2, 2)
-+Field (APMP, ByteAcc, NoLock, Preserve)
-+{
-+	APMC, 8,	// APM command
-+	APMS, 8		// APM status
-+}
-+
-+/* Port 80 POST */
-+
-+OperationRegion (POST, SystemIO, 0x80, 1)
-+Field (POST, ByteAcc, Lock, Preserve)
-+{
-+	DBG0, 8
-+}
-+
-+/* SMI I/O Trap */
-+Method(TRAP, 1, Serialized)
-+{
-+	Store (Arg0, SMIF)	// SMI Function
-+	Store (0, TRP0)		// Generate trap
-+	Return (SMIF)		// Return value of SMI handler
-+}
-+
-+/* The _PIC method is called by the OS to choose between interrupt
-+ * routing via the i8259 interrupt controller or the APIC.
-+ *
-+ * _PIC is called with a parameter of 0 for i8259 configuration and
-+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
-+ */
-+
-+Method(_PIC, 1)
-+{
-+	// Remember the OS' IRQ routing choice.
-+	Store(Arg0, PICM)
-+}
-+
-+/* The _PTS method (Prepare To Sleep) is called before the OS is
-+ * entering a sleep state. The sleep state number is passed in Arg0
-+ */
-+
-+Method(_PTS,1)
-+{
-+	// Call a trap so SMI can prepare for Sleep as well.
-+	// TRAP(0x55)
-+}
-+
-+/* The _WAK method is called on system wakeup */
-+
-+Method(_WAK,1)
-+{
-+	// CPU specific part
-+
-+	// Notify PCI Express slots in case a card
-+	// was inserted while a sleep state was active.
-+
-+	// Are we going to S3?
-+	If (LEqual(Arg0, 3)) {
-+		// ..
-+	}
-+
-+	// Are we going to S4?
-+	If (LEqual(Arg0, 4)) {
-+		// ..
-+	}
-+
-+	// TODO: Windows XP SP2 P-State restore
-+
-+	// TODO: Return Arg0 as second value if S-Arg0 was entered
-+	// before.
-+
-+	Return(Package(){0,0})
-+}
-+
-+// Power notification
-+
-+External (\_PR_.CP00, DeviceObj)
-+External (\_PR_.CP01, DeviceObj)
-+
-+Method (PNOT)
-+{
-+	If (MPEN) {
-+		If(And(PDC0, 0x08)) {
-+			Notify (\_PR_.CP00, 0x80)	 // _PPC
-+
-+			If (And(PDC0, 0x10)) {
-+				Sleep(100)
-+				Notify(\_PR_.CP00, 0x81) // _CST
-+			}
-+		}
-+
-+		If(And(PDC1, 0x08)) {
-+			Notify (\_PR_.CP01, 0x80)	 // _PPC
-+			If (And(PDC1, 0x10)) {
-+				Sleep(100)
-+				Notify(\_PR_.CP01, 0x81) // _CST
-+			}
-+		}
-+
-+	} Else { // UP
-+		Notify (\_PR_.CP00, 0x80)
-+		Sleep(0x64)
-+		Notify(\_PR_.CP00, 0x81)
-+	}
-+
-+}
-+
-+/* System Bus */
-+
-+Scope(\_SB)
-+{
-+	/* This method is placed on the top level, so we can make sure it's the
-+	 * first executed _INI method.
-+	 */
-+	Method(_INI, 0)
-+	{
-+		/* The DTS data in NVS is probably not up to date.
-+		 * Update temperature values and make sure AP thermal
-+		 * interrupts can happen
-+		 */
-+
-+		// TRAP(71) // TODO
-+
-+		/* Determine the Operating System and save the value in OSYS.
-+		 * We have to do this in order to be able to work around
-+		 * certain windows bugs.
-+		 *
-+		 *    OSYS value | Operating System
-+		 *    -----------+------------------
-+		 *       2000    | Windows 2000
-+		 *       2001    | Windows XP(+SP1)
-+		 *       2002    | Windows XP SP2
-+		 *       2006    | Windows Vista
-+		 *       ????    | Windows 7
-+		 */
-+
-+		/* Let's assume we're running at least Windows 2000 */
-+		Store (2000, OSYS)
-+
-+		If (CondRefOf(_OSI, Local0)) {
-+			/* Linux answers _OSI with "True" for a couple of
-+			 * Windows version queries. But unlike Windows it
-+			 * needs a Video repost, so let's determine whether
-+			 * we're running Linux.
-+			 */
-+
-+			If (_OSI("Linux")) {
-+				Store (1, LINX)
-+			}
-+
-+			If (_OSI("Windows 2001")) {
-+				Store (2001, OSYS)
-+			}
-+
-+			If (_OSI("Windows 2001 SP1")) {
-+				Store (2001, OSYS)
-+			}
-+
-+			If (_OSI("Windows 2001 SP2")) {
-+				Store (2002, OSYS)
-+			}
-+
-+			If (_OSI("Windows 2006")) {
-+				Store (2006, OSYS)
-+			}
-+		}
-+
-+		/* And the OS workarounds start right after we know what we're
-+		 * running: Windows XP SP1 needs to have C-State coordination
-+		 * enabled in SMM.
-+		 */
-+		If (LAnd(LEqual(OSYS, 2001), MPEN)) {
-+			// TRAP(61) // TODO
-+		}
-+
-+		/* SMM power state and C4-on-C3 settings need to be updated */
-+		// TRAP(43) // TODO
-+	}
-+}
-+
-diff --git a/src/mainboard/lenovo/t400/acpi/superio.asl b/src/mainboard/lenovo/t400/acpi/superio.asl
-new file mode 100644
-index 0000000..e69de29
-diff --git a/src/mainboard/lenovo/t400/acpi_tables.c b/src/mainboard/lenovo/t400/acpi_tables.c
-new file mode 100644
-index 0000000..77491dc
---- /dev/null
-+++ b/src/mainboard/lenovo/t400/acpi_tables.c
-@@ -0,0 +1,91 @@
-+/*
-+ * This file is part of the coreboot project.
-+ *
-+ * Copyright (C) 2007-2009 coresystems GmbH
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; version 2 of
-+ * the License.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
-+ * MA 02110-1301 USA
-+ */
-+
-+#include <string.h>
-+#include <console/console.h>
-+#include <arch/io.h>
-+#include <arch/ioapic.h>
-+#include <arch/acpi.h>
-+#include <arch/acpigen.h>
-+#include <arch/smp/mpspec.h>
-+#include <device/device.h>
-+#include <device/pci.h>
-+#include <device/pci_ids.h>
-+
-+#include "southbridge/intel/i82801ix/nvs.h"
-+void acpi_create_gnvs(global_nvs_t *gnvs)
-+{
-+	memset((void *)gnvs, 0, sizeof(*gnvs));
-+	gnvs->apic = 1;
-+	gnvs->mpen = 1; /* Enable Multi Processing */
-+
-+	/* Enable both COM ports */
-+	gnvs->cmap = 0x01;
-+	gnvs->cmbp = 0x01;
-+
-+	/* IGD Displays */
-+	gnvs->ndid = 0; /* Will use default of 0x00000400. */
-+	gnvs->did[0] = 0x80000100;
-+	gnvs->did[1] = 0x80000240;
-+	gnvs->did[2] = 0x80000410;
-+	gnvs->did[3] = 0x80000410;
-+	gnvs->did[4] = 0x00000005;
-+}
-+
-+unsigned long acpi_fill_madt(unsigned long current)
-+{
-+	/* Local APICs */
-+	current = acpi_create_madt_lapics(current);
-+
-+	/* IOAPIC */
-+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
-+				2, IO_APIC_ADDR, 0);
-+
-+	/* LAPIC_NMI */
-+	current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
-+				current, 0,
-+				MP_IRQ_POLARITY_HIGH |
-+				MP_IRQ_TRIGGER_EDGE, 0x01);
-+	current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
-+				current, 1, MP_IRQ_POLARITY_HIGH |
-+				MP_IRQ_TRIGGER_EDGE, 0x01);
-+
-+	/* INT_SRC_OVR */
-+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-+		 current, 0, 0, 2, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_EDGE);
-+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-+		 current, 0, 9, 9, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_LEVEL);
-+
-+
-+	return current;
-+}
-+
-+unsigned long acpi_fill_slit(unsigned long current)
-+{
-+	// Not implemented
-+	return current;
-+}
-+
-+unsigned long acpi_fill_srat(unsigned long current)
-+{
-+	/* No NUMA, no SRAT */
-+	return current;
-+}
-diff --git a/src/mainboard/lenovo/t400/board_info.txt b/src/mainboard/lenovo/t400/board_info.txt
-new file mode 100644
-index 0000000..60496f5
---- /dev/null
-+++ b/src/mainboard/lenovo/t400/board_info.txt
-@@ -0,0 +1,5 @@
-+Category: laptop
-+ROM package: SOIC-16
-+ROM protocol: SPI
-+ROM socketed: n
-+Flashrom support: n
-diff --git a/src/mainboard/lenovo/t400/cmos.default b/src/mainboard/lenovo/t400/cmos.default
-new file mode 100644
-index 0000000..67b8920
---- /dev/null
-+++ b/src/mainboard/lenovo/t400/cmos.default
-@@ -0,0 +1,16 @@
-+boot_option=Fallback
-+last_boot=Fallback
-+baud_rate=115200
-+debug_level=Spew
-+power_on_after_fail=Disable
-+volume=0x3
-+first_battery=Primary
-+bluetooth=Enable
-+wwan=Enable
-+wlan=Enable
-+trackpoint=Enable
-+fn_ctrl_swap=Disable
-+sticky_fn=Disable
-+power_management_beeps=Enable
-+low_battery_beep=Enable
-+sata_mode=AHCI
-diff --git a/src/mainboard/lenovo/t400/cmos.layout b/src/mainboard/lenovo/t400/cmos.layout
-new file mode 100644
-index 0000000..fbb2293
---- /dev/null
-+++ b/src/mainboard/lenovo/t400/cmos.layout
-@@ -0,0 +1,146 @@
-+#
-+# This file is part of the coreboot project.
-+#
-+# Copyright (C) 2007-2008 coresystems GmbH
-+#               2012 secunet Security Networks AG
-+#
-+# This program is free software; you can redistribute it and/or
-+# modify it under the terms of the GNU General Public License as
-+# published by the Free Software Foundation; version 2 of
-+# the License.
-+#
-+# This program is distributed in the hope that it will be useful,
-+# but WITHOUT ANY WARRANTY; without even the implied warranty of
-+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+# GNU General Public License for more details.
-+#
-+# You should have received a copy of the GNU General Public License
-+# along with this program; if not, write to the Free Software
-+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
-+# MA 02110-1301 USA
-+#
-+
-+# -----------------------------------------------------------------
-+entries
-+
-+# -----------------------------------------------------------------
-+# Status Register A
-+# -----------------------------------------------------------------
-+# Status Register B
-+# -----------------------------------------------------------------
-+# Status Register C
-+#96           4       r       0        status_c_rsvd
-+#100          1       r       0        uf_flag
-+#101          1       r       0        af_flag
-+#102          1       r       0        pf_flag
-+#103          1       r       0        irqf_flag
-+# -----------------------------------------------------------------
-+# Status Register D
-+#104          7       r       0        status_d_rsvd
-+#111          1       r       0        valid_cmos_ram
-+# -----------------------------------------------------------------
-+# Diagnostic Status Register
-+#112          8       r       0        diag_rsvd1
-+
-+# -----------------------------------------------------------------
-+0           120       r       0        reserved_memory
-+#120        240       r       0        unused
-+
-+# -----------------------------------------------------------------
-+# RTC_BOOT_BYTE (coreboot hardcoded)
-+384           1       e       4        boot_option
-+385           1       e       4        last_boot
-+388           4       r       0        reboot_bits
-+#390          2       r       0        unused?
-+
-+# -----------------------------------------------------------------
-+# coreboot config options: console
-+392           3       e       5        baud_rate
-+395           4       e       6        debug_level
-+#399          1       r       0        unused
-+
-+# coreboot config options: EC
-+400         8       h       0        volume
-+
-+# coreboot config options: southbridge
-+408         1       e       10        sata_mode
-+409         2       e       7         power_on_after_fail
-+
-+# coreboot config options: EC
-+411         1       e       9        first_battery
-+412         1       e       1        bluetooth
-+413         1       e       1        wwan
-+414         1       e       1        wlan
-+415         1       e       1        trackpoint
-+416         1       e       1        fn_ctrl_swap
-+417         1       e       1        sticky_fn
-+
-+# coreboot config options: bootloader
-+418         512       s       0        boot_devices
-+930           8       h       0        boot_default
-+
-+938         1       e       1        power_management_beeps
-+939         1       e       1        low_battery_beep
-+940         1       e       1        uwb
-+
-+# coreboot config options: northbridge
-+941         3       e       11       gfx_uma_size
-+
-+#944          2       r       0        unused
-+
-+# coreboot config options: check sums
-+984          16       h       0        check_sum
-+#1000        24       r       0        unused
-+
-+# ram initialization internal data
-+1024        128       r       0        read_training_results
-+
-+# -----------------------------------------------------------------
-+
-+enumerations
-+
-+#ID value   text
-+1     0     Disable
-+1     1     Enable
-+2     0     Enable
-+2     1     Disable
-+4     0     Fallback
-+4     1     Normal
-+5     0     115200
-+5     1     57600
-+5     2     38400
-+5     3     19200
-+5     4     9600
-+5     5     4800
-+5     6     2400
-+5     7     1200
-+6     1     Emergency
-+6     2     Alert
-+6     3     Critical
-+6     4     Error
-+6     5     Warning
-+6     6     Notice
-+6     7     Info
-+6     8     Debug
-+6     9     Spew
-+7     0     Disable
-+7     1     Enable
-+7     2     Keep
-+8     0     No
-+8     1     Yes
-+9     0     Secondary
-+9     1     Primary
-+10    0     AHCI
-+10    1     Compatible
-+11    0     32M
-+11    1     48M
-+11    2     64M
-+11    3     128M
-+11    5     96M
-+11    6     160M
-+
-+# -----------------------------------------------------------------
-+checksums
-+
-+checksum 392 983 984
-+
-diff --git a/src/mainboard/lenovo/t400/cstates.c b/src/mainboard/lenovo/t400/cstates.c
-new file mode 100644
-index 0000000..aacfc31
---- /dev/null
-+++ b/src/mainboard/lenovo/t400/cstates.c
-@@ -0,0 +1,41 @@
-+/*
-+ * This file is part of the coreboot project.
-+ *
-+ * Copyright (C) 2012 secunet Security Networks AG
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; version 2 of the License.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-+ */
-+
-+#include <arch/acpigen.h>
-+#include <device/device.h> /* fix for i82801ix.h */
-+#include <southbridge/intel/i82801ix/i82801ix.h>
-+
-+static acpi_cstate_t cst_entries[] = {
-+	{
-+		/* acpi C1 / cpu C1 */
-+		1, 0x01, 1000,
-+		{ ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0, 0 }
-+	},
-+	{
-+		/* acpi C2 / cpu C2 */
-+		2, 0x01,  500,
-+		{ ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0x10, 0 }
-+	},
-+};
-+
-+int get_cst_entries(acpi_cstate_t **entries)
-+{
-+	*entries = cst_entries;
-+	return ARRAY_SIZE(cst_entries);
-+}
-diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb
-new file mode 100644
-index 0000000..cc27d25
---- /dev/null
-+++ b/src/mainboard/lenovo/t400/devicetree.cb
-@@ -0,0 +1,203 @@
-+chip northbridge/intel/gm45
-+
-+	register "gfx.use_spread_spectrum_clock" = "1"
-+	register "gfx.lvds_dual_channel" = "0"
-+	register "gfx.link_frequency_270_mhz" = "1"
-+	register "gfx.lvds_num_lanes" = "4"
-+
-+	device cpu_cluster 0 on
-+		chip cpu/intel/socket_BGA956
-+			device lapic 0 on end
-+		end
-+		chip cpu/intel/model_1067x
-+			# Magic APIC ID to locate this chip
-+			device lapic 0xACAC off end
-+
-+			# Enable Super LFM
-+			register "slfm" = "1"
-+
-+			# Enable C5, C6
-+			register "c5" = "1"
-+			register "c6" = "1"
-+		end
-+	end
-+
-+	device domain 0 on
-+		device pci 00.0 on
-+			subsystemid 0x17aa 0x20e0
-+		end # host bridge
-+		device pci 02.0 on # VGA
-+			subsystemid 0x17aa 0x20e4
-+			ioapic_irq 2 INTA 0x10
-+		end
-+		device pci 02.1 on
-+			subsystemid 0x17aa 0x20e4
-+		end # Display
-+		device pci 03.0 on
-+			subsystemid 0x17aa 0x20e6
-+		end # ME
-+		device pci 03.1 off end # ME
-+		device pci 03.2 off end # ME
-+		device pci 03.3 off end # ME
-+		chip southbridge/intel/i82801ix
-+			register "pirqa_routing" = "0x0b"
-+			register "pirqb_routing" = "0x0b"
-+			register "pirqc_routing" = "0x0b"
-+			register "pirqd_routing" = "0x0b"
-+			register "pirqe_routing" = "0x80"
-+			register "pirqf_routing" = "0x80"
-+			register "pirqg_routing" = "0x80"
-+			register "pirqh_routing" = "0x80"
-+
-+			register "gpi8_routing"  = "2"
-+			register "gpe0_en" = "0x01000000"
-+			register "gpi1_routing"  = "2"
-+
-+			# Set AHCI mode, enable ports 1 and 2.
-+			register "sata_port_map"		= "0x03"
-+			register "sata_clock_request"		= "0"
-+			register "sata_traffic_monitor"		= "0"
-+
-+			# Set c-state support
-+			register "c4onc3_enable"		= "0"
-+			register "c5_enable"			= "1"
-+			register "c6_enable"			= "1"
-+
-+			# Set thermal throttling to 75%.
-+			register "throttle_duty"		= "THTL_75_0"
-+
-+			# Enable PCIe ports 1,2,4 as slots (Mini * PCIe).
-+			register "pcie_slot_implemented"	= "0xb"
-+			# Set power limits to 10 * 10^0 watts.
-+			# Maybe we should set less for Mini PCIe.
-+			register "pcie_power_limits" = "{ { 10, 0 }, { 10, 0 }, { 0, 0 }, { 10, 0 }, { 0, 0 }, { 0, 0 } }"
-+			register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
-+
-+			chip drivers/generic/ioapic
-+				register "have_isa_interrupts" = "1"
-+				register "irq_on_fsb" = "1"
-+				register "enable_virtual_wire" = "1"
-+				register "base" = "(void *)0xfec00000"
-+				device ioapic 2 on end
-+			end
-+
-+			device pci 19.0 on end # LAN
-+			device pci 1a.0 on # UHCI
-+				subsystemid 0x17aa 0x20f0
-+				ioapic_irq 2 INTA 0x10
-+			end
-+			device pci 1a.1 on # UHCI
-+				subsystemid 0x17aa 0x20f0
-+				ioapic_irq 2 INTB 0x11
-+			end
-+			device pci 1a.2 on # UHCI
-+				subsystemid 0x17aa 0x20f0
-+				ioapic_irq 2 INTC 0x12
-+			end
-+			device pci 1a.7 on # EHCI
-+				subsystemid 0x17aa 0x20f1
-+				ioapic_irq 2 INTC 0x12
-+			end
-+			device pci 1b.0 on # HD Audio
-+				subsystemid 0x17aa 0x20f2
-+				ioapic_irq 2 INTA 0x10
-+			end
-+			device pci 1c.0 on # PCIe Port #1
-+				subsystemid 0x17aa 0x20f3 # WWAN
-+				ioapic_irq 2 INTA 0x10
-+			end
-+			device pci 1c.1 on
-+				subsystemid 0x17aa 0x20f3 # WLAN
-+			end # PCIe Port #2
-+			device pci 1c.2 on
-+				subsystemid 0x17aa 0x20f3 # UWB
-+			end # PCIe Port #3
-+			device pci 1c.3 on
-+				subsystemid 0x17aa 0x20f3 # Expresscard
-+			end # PCIe Port #4
-+			device pci 1c.4 off end # PCIe Port #5
-+			device pci 1c.5 off end # PCIe Port #6
-+			device pci 1d.0 on # UHCI
-+				subsystemid 0x17aa 0x20f0
-+				ioapic_irq 2 INTA 0x10
-+			end
-+			device pci 1d.1 on # UHCI
-+				subsystemid 0x17aa 0x20f0
-+				ioapic_irq 2 INTB 0x11
-+			end
-+			device pci 1d.2 on # UHCI
-+				subsystemid 0x17aa 0x20f0
-+				ioapic_irq 2 INTC 0x12
-+			end
-+			device pci 1d.7 on # EHCI
-+				subsystemid 0x17aa 0x20f1
-+				ioapic_irq 2 INTA 0x10
-+			end
-+			device pci 1e.0 on # PCI
-+				subsystemid 0x17aa 0x20f4
-+			end
-+			device pci 1f.0 on # LPC bridge
-+				subsystemid 0x17aa 0x20f5
-+				chip ec/lenovo/pmh7
-+					device pnp ff.1 on # dummy
-+					end
-+					register "backlight_enable" = "0x01"
-+					register "dock_event_enable" = "0x01"
-+				end
-+
-+				chip ec/lenovo/h8
-+					device pnp ff.2 on # dummy
-+						io 0x60 = 0x62
-+						io 0x62 = 0x66
-+						io 0x64 = 0x1600
-+						io 0x66 = 0x1604
-+					end
-+
-+					register "config0" = "0xa6"
-+					register "config1" = "0x04"
-+					register "config2" = "0xa0"
-+					register "config3" = "0x01"
-+
-+					register "beepmask0" = "0xfe"
-+					register "beepmask1" = "0x96"
-+					register "has_power_management_beeps" = "1"
-+					register "has_uwb" = "1"
-+
-+					register "event2_enable" = "0xff"
-+					register "event3_enable" = "0xff"
-+					register "event4_enable" = "0xf4"
-+					register "event5_enable" = "0x3c"
-+					register "event6_enable" = "0x80"
-+					register "event7_enable" = "0x01"
-+					register "event8_enable" = "0x01"
-+					register "event9_enable" = "0xff"
-+					register "eventa_enable" = "0xff"
-+					register "eventb_enable" = "0xff"
-+					register "eventc_enable" = "0xff"
-+					register "eventd_enable" = "0xff"
-+				end
-+			end
-+			device pci 1f.2 on # SATA/IDE 1
-+				subsystemid 0x17aa 0x20f8
-+				ioapic_irq 2 INTB 0x11
-+			end
-+			device pci 1f.3 on # SMBus
-+				subsystemid 0x17aa 0x20f9
-+				ioapic_irq 2 INTC 0x12
-+			        # eeprom, 8 virtual devices, same chip
-+				chip drivers/i2c/at24rf08c
-+					device i2c 54 on end
-+					device i2c 55 on end
-+					device i2c 56 on end
-+					device i2c 57 on end
-+					device i2c 5c on end
-+					device i2c 5d on end
-+					device i2c 5e on end
-+					device i2c 5f on end
-+				end
-+			end
-+			device pci 1f.5 off end # SATA/IDE 2
-+			device pci 1f.6 off end # Thermal
-+		end
-+	end
-+end
-diff --git a/src/mainboard/lenovo/t400/dock.c b/src/mainboard/lenovo/t400/dock.c
-new file mode 100644
-index 0000000..6f9e953
---- /dev/null
-+++ b/src/mainboard/lenovo/t400/dock.c
-@@ -0,0 +1,65 @@
-+/*
-+ * This file is part of the coreboot project.
-+ *
-+ * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
-+ * Copyright (C) 2013 Vladimir Serbinenko <phcoder@gmail.com>
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; version 2 of
-+ * the License.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
-+ * MA 02110-1301 USA
-+ */
-+
-+#define __SIMPLE_DEVICE__
-+#include <console/console.h>
-+#include <arch/io.h>
-+#include <device/device.h>
-+#include <device/pci.h>
-+#include <delay.h>
-+#include "dock.h"
-+#include "southbridge/intel/i82801ix/i82801ix.h"
-+#include "ec/lenovo/h8/h8.h"
-+#include <ec/acpi/ec.h>
-+
-+#define LPC_DEV PCI_DEV(0, 0x1f, 0)
-+
-+void h8_mainboard_init_dock (void)
-+{
-+	if (dock_present()) {
-+		printk(BIOS_DEBUG, "dock is connected\n");
-+		dock_connect();
-+	} else
-+		printk(BIOS_DEBUG, "dock is not connected\n");
-+}
-+
-+void dock_connect(void)
-+{
-+	u16 gpiobase = pci_read_config16(LPC_DEV, D31F0_GPIO_BASE) & 0xfffc;
-+	ec_set_bit(0x02, 0);
-+	outl(inl(gpiobase + 0x0c) | (1 << 28), gpiobase + 0x0c);
-+}
-+
-+void dock_disconnect(void)
-+{
-+	u16 gpiobase = pci_read_config16(LPC_DEV, D31F0_GPIO_BASE) & 0xfffc;
-+	ec_clr_bit(0x02, 0);
-+	outl(inl(gpiobase + 0x0c) & ~(1 << 28), gpiobase + 0x0c);
-+}
-+
-+int dock_present(void)
-+{
-+	u16 gpiobase = pci_read_config16(LPC_DEV, D31F0_GPIO_BASE) & 0xfffc;
-+	u8 st = inb(gpiobase + 0x0c);
-+
-+	return ((st >> 2) & 7) != 7;
-+}
-diff --git a/src/mainboard/lenovo/t400/dock.h b/src/mainboard/lenovo/t400/dock.h
-new file mode 100644
-index 0000000..e888583
---- /dev/null
-+++ b/src/mainboard/lenovo/t400/dock.h
-@@ -0,0 +1,26 @@
-+/*
-+ * This file is part of the coreboot project.
-+ *
-+ * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; version 2 of the License.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-+ */
-+
-+#ifndef THINKPAD_X200_DOCK_H
-+#define THINKPAD_X200_DOCK_H
-+
-+extern void dock_connect(void);
-+extern void dock_disconnect(void);
-+extern int dock_present(void);
-+#endif
-diff --git a/src/mainboard/lenovo/t400/dsdt.asl b/src/mainboard/lenovo/t400/dsdt.asl
-new file mode 100644
-index 0000000..0409e66
---- /dev/null
-+++ b/src/mainboard/lenovo/t400/dsdt.asl
-@@ -0,0 +1,59 @@
-+/*
-+ * This file is part of the coreboot project.
-+ *
-+ * Copyright (C) 2007-2009 coresystems GmbH
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; version 2 of
-+ * the License.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
-+ * MA 02110-1301 USA
-+ */
-+
-+#define THINKPAD_EC_GPE 17
-+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.LCD0.INCB
-+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.LCD0.DECB
-+#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
-+#define DISPLAY_DEVICE_2_IS_LCD_SCREEN 1
-+
-+DefinitionBlock(
-+	"dsdt.aml",
-+	"DSDT",
-+	0x03,		// DSDT revision: ACPI v3.0
-+	"COREv4",	// OEM id
-+	"COREBOOT",	// OEM table id
-+	0x20090419	// OEM revision
-+)
-+{
-+	// Some generic macros
-+	#include "acpi/platform.asl"
-+
-+	// global NVS and variables
-+	#include <southbridge/intel/i82801ix/acpi/globalnvs.asl>
-+
-+	// General Purpose Events
-+	#include "acpi/gpe.asl"
-+
-+	Scope (\_SB) {
-+		Device (PCI0)
-+		{
-+			#include <northbridge/intel/gm45/acpi/gm45.asl>
-+			#include <southbridge/intel/i82801ix/acpi/ich9.asl>
-+		}
-+	}
-+
-+	/* Chipset specific sleep states */
-+	#include <southbridge/intel/i82801ix/acpi/sleepstates.asl>
-+
-+	/* Dock support code */
-+	#include "acpi/dock.asl"
-+}
-diff --git a/src/mainboard/lenovo/t400/fadt.c b/src/mainboard/lenovo/t400/fadt.c
-new file mode 100644
-index 0000000..fef9721
---- /dev/null
-+++ b/src/mainboard/lenovo/t400/fadt.c
-@@ -0,0 +1,158 @@
-+/*
-+ * This file is part of the coreboot project.
-+ *
-+ * Copyright (C) 2007-2008 coresystems GmbH
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; version 2 of
-+ * the License.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
-+ * MA 02110-1301 USA
-+ */
-+
-+#include <string.h>
-+#include <device/pci.h>
-+#include <arch/acpi.h>
-+#include <cpu/x86/smm.h>
-+
-+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
-+{
-+	acpi_header_t *header = &(fadt->header);
-+	u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe;
-+
-+	memset((void *) fadt, 0, sizeof(acpi_fadt_t));
-+	memcpy(header->signature, "FACP", 4);
-+	header->length = sizeof(acpi_fadt_t);
-+	header->revision = 3;
-+	memcpy(header->oem_id, OEM_ID, 6);
-+	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
-+	memcpy(header->asl_compiler_id, ASLC, 4);
-+	header->asl_compiler_revision = 0;
-+
-+	fadt->firmware_ctrl = (unsigned long) facs;
-+	fadt->dsdt = (unsigned long) dsdt;
-+	fadt->model = 0x00;
-+	fadt->preferred_pm_profile = PM_MOBILE;
-+	fadt->sci_int = 0x9;
-+	fadt->smi_cmd = APM_CNT;
-+	fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
-+	fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
-+	fadt->s4bios_req = 0x0;
-+	fadt->pstate_cnt = APM_CNT_PST_CONTROL;
-+
-+	fadt->pm1a_evt_blk = pmbase;
-+	fadt->pm1b_evt_blk = 0x0;
-+	fadt->pm1a_cnt_blk = pmbase + 0x4;
-+	fadt->pm1b_cnt_blk = 0x0;
-+	fadt->pm2_cnt_blk = pmbase + 0x50;
-+	fadt->pm_tmr_blk = pmbase + 0x8;
-+	fadt->gpe0_blk = pmbase + 0x20;
-+	fadt->gpe1_blk = 0;
-+
-+	fadt->pm1_evt_len = 4;
-+	fadt->pm1_cnt_len = 2; /* Upper word is reserved and
-+				  Linux complains about 32 bit. */
-+	fadt->pm2_cnt_len = 1;
-+	fadt->pm_tmr_len = 4;
-+	fadt->gpe0_blk_len = 16;
-+	fadt->gpe1_blk_len = 0;
-+	fadt->gpe1_base = 0;
-+	fadt->cst_cnt = APM_CNT_CST_CONTROL;
-+	fadt->p_lvl2_lat = 1;
-+	fadt->p_lvl3_lat = 0x39;
-+	fadt->flush_size = 0;
-+	fadt->flush_stride = 0;
-+	fadt->duty_offset = 1;
-+	fadt->duty_width = 3;
-+	fadt->day_alrm = 0xd;
-+	fadt->mon_alrm = 0x00;
-+	fadt->century = 0x32;
-+	fadt->iapc_boot_arch = 0x00;
-+	fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
-+			ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE |
-+			ACPI_FADT_DOCKING_SUPPORTED | ACPI_FADT_RESET_REGISTER |
-+			ACPI_FADT_PLATFORM_CLOCK;
-+
-+	fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO;
-+	fadt->reset_reg.bit_width = 8;
-+	fadt->reset_reg.bit_offset = 0;
-+	fadt->reset_reg.resv = 0;
-+	fadt->reset_reg.addrl = 0xcf9;
-+	fadt->reset_reg.addrh = 0;
-+	fadt->reset_value = 0x06;
-+
-+	fadt->x_firmware_ctl_l = 0; /* Set X_FIRMWARE_CTRL only if FACS is */
-+	fadt->x_firmware_ctl_h = 0; /* above 4GB. If X_FIRMWARE_CTRL is set, */
-+				    /* then FIRMWARE_CTRL must be zero. */
-+	fadt->x_dsdt_l = (unsigned long)dsdt;
-+	fadt->x_dsdt_h = 0;
-+
-+	fadt->x_pm1a_evt_blk.space_id = 1;
-+	fadt->x_pm1a_evt_blk.bit_width = 32;
-+	fadt->x_pm1a_evt_blk.bit_offset = 0;
-+	fadt->x_pm1a_evt_blk.resv = 0;
-+	fadt->x_pm1a_evt_blk.addrl = pmbase;
-+	fadt->x_pm1a_evt_blk.addrh = 0x0;
-+
-+	fadt->x_pm1b_evt_blk.space_id = 0;
-+	fadt->x_pm1b_evt_blk.bit_width = 0;
-+	fadt->x_pm1b_evt_blk.bit_offset = 0;
-+	fadt->x_pm1b_evt_blk.resv = 0;
-+	fadt->x_pm1b_evt_blk.addrl = 0x0;
-+	fadt->x_pm1b_evt_blk.addrh = 0x0;
-+
-+	fadt->x_pm1a_cnt_blk.space_id = 1;
-+	fadt->x_pm1a_cnt_blk.bit_width = 16; /* Upper word is reserved and
-+						Linux complains about 32 bit. */
-+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
-+	fadt->x_pm1a_cnt_blk.resv = 0;
-+	fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
-+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
-+
-+	fadt->x_pm1b_cnt_blk.space_id = 0;
-+	fadt->x_pm1b_cnt_blk.bit_width = 0;
-+	fadt->x_pm1b_cnt_blk.bit_offset = 0;
-+	fadt->x_pm1b_cnt_blk.resv = 0;
-+	fadt->x_pm1b_cnt_blk.addrl = 0x0;
-+	fadt->x_pm1b_cnt_blk.addrh = 0x0;
-+
-+	fadt->x_pm2_cnt_blk.space_id = 1;
-+	fadt->x_pm2_cnt_blk.bit_width = 8;
-+	fadt->x_pm2_cnt_blk.bit_offset = 0;
-+	fadt->x_pm2_cnt_blk.resv = 0;
-+	fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
-+	fadt->x_pm2_cnt_blk.addrh = 0x0;
-+
-+	fadt->x_pm_tmr_blk.space_id = 1;
-+	fadt->x_pm_tmr_blk.bit_width = 32;
-+	fadt->x_pm_tmr_blk.bit_offset = 0;
-+	fadt->x_pm_tmr_blk.resv = 0;
-+	fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
-+	fadt->x_pm_tmr_blk.addrh = 0x0;
-+
-+	fadt->x_gpe0_blk.space_id = 1;
-+	fadt->x_gpe0_blk.bit_width = 128;
-+	fadt->x_gpe0_blk.bit_offset = 0;
-+	fadt->x_gpe0_blk.resv = 0;
-+	fadt->x_gpe0_blk.addrl = pmbase + 0x20;
-+	fadt->x_gpe0_blk.addrh = 0x0;
-+
-+	fadt->x_gpe1_blk.space_id = 0;
-+	fadt->x_gpe1_blk.bit_width = 0;
-+	fadt->x_gpe1_blk.bit_offset = 0;
-+	fadt->x_gpe1_blk.resv = 0;
-+	fadt->x_gpe1_blk.addrl = 0x0;
-+	fadt->x_gpe1_blk.addrh = 0x0;
-+
-+	header->checksum =
-+	    acpi_checksum((void *) fadt, header->length);
-+}
-diff --git a/src/mainboard/lenovo/t400/hda_verb.c b/src/mainboard/lenovo/t400/hda_verb.c
-new file mode 100644
-index 0000000..c1cd542
---- /dev/null
-+++ b/src/mainboard/lenovo/t400/hda_verb.c
-@@ -0,0 +1,51 @@
-+/*
-+ * This file is part of the coreboot project.
-+ *
-+ * Copyright (C) 2007-2009 coresystems GmbH
-+ *               2012 secunet Security Networks AG
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; version 2 of the License.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-+ */
-+
-+#include <device/azalia_device.h>
-+
-+const u32 cim_verb_data[] = {
-+	/* coreboot specific header */
-+	0x14f15051,	// Conexant CX20561 (Hermosa)
-+	0x17aa20ff,	// Subsystem ID
-+	0x00000008,	// Number of entries
-+
-+	/* Pin Widget Verb Table */
-+
-+	AZALIA_PIN_CFG(0, 0x16, 0x042140f0),
-+	AZALIA_PIN_CFG(0, 0x17, 0x61a190f0),
-+	AZALIA_PIN_CFG(0, 0x18, 0x04a190f0),
-+	AZALIA_PIN_CFG(0, 0x19, 0x612140f0),
-+	AZALIA_PIN_CFG(0, 0x1a, 0x901701f0),
-+	AZALIA_PIN_CFG(0, 0x1b, 0x40f001f0),
-+	AZALIA_PIN_CFG(0, 0x1c, 0x40f001f0),
-+	AZALIA_PIN_CFG(0, 0x1d, 0x90a601f0)
-+};
-+
-+const u32 pc_beep_verbs[] = {
-+	0x00170500,	/* power up codec */
-+	0x01470500,	/* power up speakers */
-+	0x01470100,	/* select lout1 (input 0x0) for speakers */
-+	0x01470740,	/* enable speakers output */
-+	0x00b37517,	/* unmute beep (mixer's input 0x5), set amp 0dB */
-+	0x00c37100,	/* unmute mixer in lout1 (lout1 input 0x1) */
-+	0x00c3b015,	/* set lout1 output volume -15dB */
-+	0x0143b000,	/* unmute speakers */
-+};
-+AZALIA_ARRAY_SIZES;
-diff --git a/src/mainboard/lenovo/t400/mainboard.c b/src/mainboard/lenovo/t400/mainboard.c
-new file mode 100644
-index 0000000..5354834
---- /dev/null
-+++ b/src/mainboard/lenovo/t400/mainboard.c
-@@ -0,0 +1,70 @@
-+/*
-+ * This file is part of the coreboot project.
-+ *
-+ * Copyright (C) 2012 secunet Security Networks AG
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; version 2 of the License.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-+ */
-+
-+#include <stdint.h>
-+#include <stdlib.h>
-+#include <arch/io.h>
-+#include <device/device.h>
-+#include <console/console.h>
-+#include <drivers/intel/gma/int15.h>
-+#include <pc80/keyboard.h>
-+#include <ec/acpi/ec.h>
-+#include <smbios.h>
-+#include <string.h>
-+#include <version.h>
-+#include <ec/lenovo/pmh7/pmh7.h>
-+#include <ec/acpi/ec.h>
-+#include <ec/lenovo/h8/h8.h>
-+
-+#include "cstates.c" /* Include it, as the linker won't find
-+			the overloaded weak function in there. */
-+
-+const char *smbios_mainboard_bios_version(void)
-+{
-+	static char *s = NULL;
-+
-+	/* Satisfy thinkpad_acpi.  */
-+	if (strlen(CONFIG_LOCALVERSION))
-+		return "CBET4000 " CONFIG_LOCALVERSION;
-+
-+	if (s != NULL)
-+		return s;
-+	s = strconcat("CBET4000 ", coreboot_version);
-+	return s;
-+}
-+
-+static void mainboard_init(device_t dev)
-+{
-+	/* This sneaked in here, because X200 SuperIO chip isn't really
-+	   connected to anything and hence we don't init it.
-+	 */
-+	pc_keyboard_init();
-+}
-+
-+static void mainboard_enable(device_t dev)
-+{
-+	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 2);
-+
-+	dev->ops->init = mainboard_init;
-+}
-+
-+struct chip_operations mainboard_ops = {
-+	.enable_dev = mainboard_enable,
-+};
-+
-diff --git a/src/mainboard/lenovo/t400/mptable.c b/src/mainboard/lenovo/t400/mptable.c
-new file mode 100644
-index 0000000..f1839f0
---- /dev/null
-+++ b/src/mainboard/lenovo/t400/mptable.c
-@@ -0,0 +1 @@
-+/* dummy file */
-diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c
-new file mode 100644
-index 0000000..5f50f32
---- /dev/null
-+++ b/src/mainboard/lenovo/t400/romstage.c
-@@ -0,0 +1,205 @@
-+/*
-+ * This file is part of the coreboot project.
-+ *
-+ * Copyright (C) 2012 secunet Security Networks AG
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; version 2 of
-+ * the License.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
-+ * MA 02110-1301 USA
-+ */
-+
-+// __PRE_RAM__ means: use "unsigned" for device, not a struct.
-+
-+#include <stdint.h>
-+#include <string.h>
-+#include <arch/io.h>
-+#include <cpu/x86/lapic.h>
-+#include <cpu/x86/msr.h>
-+#include <cpu/x86/tsc.h>
-+#include <cbmem.h>
-+#include <lib.h>
-+#include <pc80/mc146818rtc.h>
-+#include <console/console.h>
-+#include <southbridge/intel/i82801ix/i82801ix.h>
-+#include <northbridge/intel/gm45/gm45.h>
-+#include <cpu/intel/romstage.h>
-+
-+#define LPC_DEV PCI_DEV(0, 0x1f, 0)
-+#define MCH_DEV PCI_DEV(0, 0, 0)
-+
-+static void default_southbridge_gpio_setup(void)
-+{
-+	outl(0x197e23fe, DEFAULT_GPIOBASE + GP_IO_USE_SEL);
-+	outl(0xe1a66dfe, DEFAULT_GPIOBASE + GP_IO_SEL);
-+	outl(0xe3faef3f, DEFAULT_GPIOBASE + GP_LVL);
-+
-+	/* Disable blink [31:0]. */
-+	outl(0x00000000, DEFAULT_GPIOBASE + GPO_BLINK);
-+	/* Set input inversion [31:0]. */
-+	outl(0x00000102, DEFAULT_GPIOBASE + GPI_INV);
-+
-+	/* Enable GPIOs [60:32]. */
-+	outl(0x030306f6, DEFAULT_GPIOBASE + GP_IO_USE_SEL2);
-+	/* Set input/output mode [60:32] (0 == out, 1 == in). */
-+	outl(0x1f55f9f1, DEFAULT_GPIOBASE + GP_IO_SEL2);
-+	/* Set gpio levels [60:32].  */
-+	outl(0x1dffff53, DEFAULT_GPIOBASE + GP_LVL2);
-+}
-+
-+static void early_lpc_setup(void)
-+{
-+	/* Set up SuperIO LPC forwards */
-+
-+	/* Configure serial IRQs.*/
-+	pci_write_config8(LPC_DEV, D31F0_SERIRQ_CNTL, 0xd0);
-+	/* Map COMa on 0x3f8, COMb on 0x2f8. */
-+	pci_write_config16(LPC_DEV, D31F0_LPC_IODEC, 0x0010);
-+	pci_write_config16(LPC_DEV, D31F0_LPC_EN, 0x3f0f);
-+	pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0x7c1601);
-+	pci_write_config32(LPC_DEV, D31F0_GEN2_DEC, 0xc15e1);
-+	pci_write_config32(LPC_DEV, D31F0_GEN3_DEC, 0x1c1681);
-+}
-+
-+void main(unsigned long bist)
-+{
-+	sysinfo_t sysinfo;
-+	int s3resume = 0;
-+	int cbmem_initted;
-+	u16 reg16;
-+
-+	/* basic northbridge setup, including MMCONF BAR */
-+	gm45_early_init();
-+
-+	if (bist == 0)
-+		enable_lapic();
-+
-+	/* First, run everything needed for console output. */
-+	i82801ix_early_init();
-+	early_lpc_setup();
-+	console_init();
-+	printk(BIOS_DEBUG, "running main(bist = %lu)\n", bist);
-+
-+	reg16 = pci_read_config16(LPC_DEV, D31F0_GEN_PMCON_3);
-+	pci_write_config16(LPC_DEV, D31F0_GEN_PMCON_3, reg16);
-+	if ((MCHBAR16(SSKPD_MCHBAR) == 0xCAFE) && !(reg16 & (1 << 9))) {
-+		printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
-+		gm45_early_reset();
-+	}
-+
-+	default_southbridge_gpio_setup();
-+
-+	/* ASPM related setting, set early by original BIOS. */
-+	DMIBAR16(0x204) &= ~(3 << 10);
-+
-+	/* Check for S3 resume. */
-+	const u32 pm1_cnt = inl(DEFAULT_PMBASE + 0x04);
-+	if (((pm1_cnt >> 10) & 7) == 5) {
-+#if CONFIG_HAVE_ACPI_RESUME
-+		printk(BIOS_DEBUG, "Resume from S3 detected.\n");
-+		s3resume = 1;
-+		/* Clear SLP_TYPE. This will break stage2 but
-+		 * we care for that when we get there.
-+		 */
-+		outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + 0x04);
-+#else
-+		printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
-+#endif
-+	}
-+
-+	/* RAM initialization */
-+	enter_raminit_or_reset();
-+	memset(&sysinfo, 0, sizeof(sysinfo));
-+	sysinfo.spd_map[0] = 0x50;
-+	sysinfo.spd_map[2] = 0x51;
-+	sysinfo.enable_igd = 1;
-+	sysinfo.enable_peg = 0;
-+	get_gmch_info(&sysinfo);
-+	raminit(&sysinfo, s3resume);
-+
-+	const u32 deven = pci_read_config32(MCH_DEV, D0F0_DEVEN);
-+	/* Disable D4F0 (unknown signal controller). */
-+	pci_write_config32(MCH_DEV, D0F0_DEVEN, deven & ~0x4000);
-+
-+	init_pm(&sysinfo, 0);
-+
-+	i82801ix_dmi_setup();
-+	gm45_late_init(sysinfo.stepping);
-+	i82801ix_dmi_poll_vc1();
-+
-+	MCHBAR16(SSKPD_MCHBAR) = 0xCAFE;
-+	/* Enable ethernet.  */
-+	RCBA32(0x3414) &= ~0x20;
-+
-+	RCBA32(0x0238) = 0x00543210;
-+	RCBA32(0x0240) = 0x009c0b02;
-+	RCBA32(0x0244) = 0x00a20b1a;
-+	RCBA32(0x0248) = 0x005402cb;
-+	RCBA32(0x0254) = 0x00470966;
-+	RCBA32(0x0258) = 0x00470473;
-+	RCBA32(0x0260) = 0x00e90825;
-+	RCBA32(0x0278) = 0x00bc0efb;
-+	RCBA32(0x027c) = 0x00c00f0b;
-+	RCBA32(0x0280) = 0x00670000;
-+	RCBA32(0x0284) = 0x006d0000;
-+	RCBA32(0x0288) = 0x00600b4e;
-+	RCBA32(0x1e10) = 0x00020800;
-+	RCBA32(0x1e18) = 0x36ea00a0;
-+	RCBA32(0x1e80) = 0x000c0801;
-+	RCBA32(0x1e84) = 0x000200f0;
-+	RCBA32(0x2028) = 0x04c8f95e;
-+	RCBA32(0x202c) = 0x055c095e;
-+	RCBA32(0x204c) = 0x001ffc00;
-+	RCBA32(0x2050) = 0x00100fff;
-+	RCBA32(0x2090) = 0x37000000;
-+	RCBA32(0x20b0) = 0x0c000000;
-+	RCBA32(0x20d0) = 0x09000000;
-+	RCBA32(0x20f0) = 0x05000000;
-+	RCBA32(0x3400) = 0x0000001c;
-+	RCBA32(0x3410) = 0x00100461;
-+	RCBA32(0x3414) = 0x00000000;
-+	RCBA32(0x341c) = 0xbf4f001f;
-+	RCBA32(0x3420) = 0x00000000;
-+	RCBA32(0x3430) = 0x00000001;
-+
-+	init_iommu();
-+
-+	/* FIXME: make a proper SMBUS mux support.  */
-+	outl(inl(DEFAULT_GPIOBASE + 0x38) & ~0x400, DEFAULT_GPIOBASE + 0x38);
-+
-+	cbmem_initted = !cbmem_recovery(s3resume);
-+#if CONFIG_HAVE_ACPI_RESUME
-+	/* If there is no high memory area, we didn't boot before, so
-+	 * this is not a resume. In that case we just create the cbmem toc.
-+	 */
-+	if (s3resume && cbmem_initted) {
-+		void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
-+
-+		/* copy 1MB - 64K to high tables ram_base to prevent memory corruption
-+		 * through stage 2. We could keep stuff like stack and heap in high tables
-+		 * memory completely, but that's a wonderful clean up task for another
-+		 * day.
-+		 */
-+		if (resume_backup_memory)
-+			memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
-+
-+		/* Magic for S3 resume */
-+		pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_ACPI_S3_MAGIC);
-+	} else {
-+		/* Magic for S3 resume */
-+		pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_NORMAL_BOOT_MAGIC);
-+	}
-+#endif
-+	printk(BIOS_SPEW, "exit main()\n");
-+}
-+
-diff --git a/src/mainboard/lenovo/t400/smihandler.c b/src/mainboard/lenovo/t400/smihandler.c
-new file mode 100644
-index 0000000..baa038e
---- /dev/null
-+++ b/src/mainboard/lenovo/t400/smihandler.c
-@@ -0,0 +1,75 @@
-+/*
-+ * This file is part of the coreboot project.
-+ *
-+ * Copyright (C) 2008-2009 coresystems GmbH
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; version 2 of the License.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-+ */
-+
-+#include <arch/io.h>
-+#include <console/console.h>
-+#include <cpu/x86/smm.h>
-+#include <southbridge/intel/i82801ix/nvs.h>
-+#include <southbridge/intel/i82801ix/i82801ix.h>
-+#include <ec/acpi/ec.h>
-+
-+/* The southbridge SMI handler checks whether gnvs has a
-+ * valid pointer before calling the trap handler
-+ */
-+extern global_nvs_t *gnvs;
-+
-+int mainboard_io_trap_handler(int smif)
-+{
-+	switch (smif) {
-+	case 0x99:
-+		printk(BIOS_DEBUG, "Sample\n");
-+		gnvs->smif = 0;
-+		break;
-+	default:
-+		return 0;
-+	}
-+
-+	/* On success, the IO Trap Handler returns 0
-+	 * On failure, the IO Trap Handler returns a value != 0
-+	 *
-+	 * For now, we force the return value to 0 and log all traps to
-+	 * see what's going on.
-+	 */
-+	//gnvs->smif = 0;
-+	return 1;
-+}
-+
-+void mainboard_smi_gpi(u32 gpi_sts)
-+{
-+	if (gpi_sts & (1 << 1)) {
-+		printk(BIOS_DEBUG, "EC/SMI\n");
-+		/* TODO */
-+	}
-+}
-+
-+int mainboard_smi_apmc(u8 apmc)
-+{
-+	switch (apmc) {
-+	case APM_CNT_ACPI_ENABLE:
-+		send_ec_command(0x05); /* Set_SMI_Disable */
-+		send_ec_command(0xaa); /* Set_ACPI_Enable */
-+		break;
-+
-+	case APM_CNT_ACPI_DISABLE:
-+		send_ec_command(0x04); /* Set_SMI_Enable */
-+		send_ec_command(0xab); /* Set_ACPI_Disable */
-+		break;
-+	}
-+	return 0;
-+}
--- 
-1.9.1
-
diff --git a/resources/libreboot/patch/0016-lenovo-t60-Enable-text-mode-native-gfx-init.patch b/resources/libreboot/patch/0008-lenovo-t60-Enable-VESA-framebuffer-mode-native-graph.patch
index 6aee3ad..729b09d 100644
--- a/resources/libreboot/patch/0016-lenovo-t60-Enable-text-mode-native-gfx-init.patch
+++ b/resources/libreboot/patch/0008-lenovo-t60-Enable-VESA-framebuffer-mode-native-graph.patch
@@ -1,9 +1,14 @@
-From 875078b081cfe58eaf755bfdd10c743b7207be0f Mon Sep 17 00:00:00 2001
+From c37e4a312e8c18b3b1e2fb11bb1cf8bb5b4aa9d2 Mon Sep 17 00:00:00 2001
 From: Francis Rowe <info@gluglug.org.uk>
-Date: Sat, 11 Oct 2014 18:41:35 +0100
-Subject: [PATCH 16/22] lenovo/t60: Enable text mode native gfx init
+Date: Mon, 15 Jun 2015 19:56:29 +0100
+Subject: [PATCH 08/17] lenovo/t60: Enable VESA framebuffer mode (native
+ graphics)
 
-Change-Id: Iffd2b1d5f86d4b872f8d39466cbbccd088ef7784
+At present, no option exists for "Keep VESA framebuffer", which
+means that text-mode will be used. Add the appropriate Kconfig
+option.
+
+Change-Id: Ie8c91fc04c8d6a8ff41977be0b730e86e34546af
 Signed-off-by: Francis Rowe <info@gluglug.org.uk>
 ---
  src/mainboard/lenovo/t60/Kconfig | 1 +
diff --git a/resources/libreboot/patch/0017-lenovo-t60-Enable-legacy-brightness-controls-native-.patch b/resources/libreboot/patch/0009-lenovo-t60-Enable-brightness-controls-native-graphic.patch
index 7757620..7e381e2 100644
--- a/resources/libreboot/patch/0017-lenovo-t60-Enable-legacy-brightness-controls-native-.patch
+++ b/resources/libreboot/patch/0009-lenovo-t60-Enable-brightness-controls-native-graphic.patch
@@ -1,22 +1,29 @@
-From 519a5be5914a2949f93f4c2f76b22cf4e6102879 Mon Sep 17 00:00:00 2001
+From e226918085e01a51916357b4c8d667e31e040fe4 Mon Sep 17 00:00:00 2001
 From: Francis Rowe <info@gluglug.org.uk>
-Date: Sat, 11 Oct 2014 20:36:10 +0100
-Subject: [PATCH 17/22] lenovo/t60: Enable legacy brightness controls (native
+Date: Mon, 15 Jun 2015 19:59:46 +0100
+Subject: [PATCH 09/17] lenovo/t60: Enable brightness controls (native
  graphics)
 
-Value obtained by reading BLC_PWM_CTL when running the VBIOS (option ROM).
+This makes the Fn Home/End keys work for controlling the
+brightness of the display. Value obtained by reading
+BLC_PWM_CTL when running the VBIOS (option ROM).
 
-Change-Id: I95f634c5071f6d4bdd423819ce4e40985732761c
+On i945 legacy brightness control is enabled by a single
+bit in BLC_PWM_CTL. It's bit 16 or bit 0 (the other one
+reverses polarity). Set the bit to enable brightness
+controls.
+
+Change-Id: I22e261f2ce28ec81cd208a73e6311ec67146eb72
 Signed-off-by: Francis Rowe <info@gluglug.org.uk>
 ---
  src/mainboard/lenovo/t60/devicetree.cb | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)
 
 diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb
-index a0ee7f9..43f570e 100644
+index fdced26..5f90a73 100644
 --- a/src/mainboard/lenovo/t60/devicetree.cb
 +++ b/src/mainboard/lenovo/t60/devicetree.cb
-@@ -25,7 +25,7 @@ chip northbridge/intel/i945
+@@ -27,7 +27,7 @@ chip northbridge/intel/i945
  	register "gpu_hotplug" = "0x00000220"
  	register "gpu_lvds_use_spread_spectrum_clock" = "1"
  	register "gpu_lvds_is_dual_channel" = "1"
diff --git a/resources/libreboot/patch/0018-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch b/resources/libreboot/patch/0010-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch
index 70bf654..f84d048 100644
--- a/resources/libreboot/patch/0018-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch
+++ b/resources/libreboot/patch/0010-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch
@@ -1,17 +1,10 @@
-From a36e204862fc556c7d06cbc9c29f6b0a4df21287 Mon Sep 17 00:00:00 2001
+From 7786aea5d38e6e132a259c2a00cf75f493fc12fd Mon Sep 17 00:00:00 2001
 From: Francis Rowe <info@gluglug.org.uk>
 Date: Mon, 13 Oct 2014 00:14:53 +0100
-Subject: [PATCH 18/22] NOTFORMERGE: ec/lenovo/h8:
+Subject: [PATCH 10/17] NOTFORMERGE: ec/lenovo/h8:
  wlan/trackpoint/touchpad/bluetooth/wwan
 
-Permanently enable them. Ignore configuration made by nvramtool.
-Almost every user will want all of these to be enabled, and those
-who would like them to be disabled would physically remove the
-relevant components from their machine anyway, or just not use
-them (in the case of the touchpad or trackpoint). So, why make it
-configurable in the first place? All it does is add confusion.
-
-The mind boggles.
+Permanently enable them.
 
 Change-Id: Ic76ab9ab9c865f30312378e18af58bece6c3260a
 Signed-off-by: Francis Rowe <info@gluglug.org.uk>
@@ -21,10 +14,10 @@ Signed-off-by: Francis Rowe <info@gluglug.org.uk>
  2 files changed, 15 insertions(+), 17 deletions(-)
 
 diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c
-index 13b0483..b688e64 100644
+index 46480f4..b6bc406 100644
 --- a/src/ec/lenovo/h8/h8.c
 +++ b/src/ec/lenovo/h8/h8.c
-@@ -245,9 +245,11 @@ static void h8_enable(struct device *dev)
+@@ -252,9 +252,11 @@ static void h8_enable(struct device *dev)
  
  	ec_write(H8_FAN_CONTROL, H8_FAN_CONTROL_AUTO);
  
@@ -39,7 +32,7 @@ index 13b0483..b688e64 100644
  
  	h8_trackpoint_enable(1);
  	h8_usb_power_enable(1);
-@@ -255,14 +257,13 @@ static void h8_enable(struct device *dev)
+@@ -262,14 +264,13 @@ static void h8_enable(struct device *dev)
  	if (get_option(&val, "volume") == CB_SUCCESS)
  		ec_write(H8_VOLUME_CONTROL, val);
  
@@ -61,7 +54,7 @@ index 13b0483..b688e64 100644
  	if (conf->has_uwb) {
  		if (get_option(&val, "uwb") != CB_SUCCESS)
 diff --git a/src/ec/lenovo/pmh7/pmh7.c b/src/ec/lenovo/pmh7/pmh7.c
-index f67fbda..9cb7149 100644
+index cc6e891..38aef16 100644
 --- a/src/ec/lenovo/pmh7/pmh7.c
 +++ b/src/ec/lenovo/pmh7/pmh7.c
 @@ -106,7 +106,6 @@ static void enable_dev(struct device *dev)
diff --git a/resources/libreboot/patch/0010-mainboard-lenovo-t400-Add-initial-ATPX-ACPI-implemen.patch b/resources/libreboot/patch/0010-mainboard-lenovo-t400-Add-initial-ATPX-ACPI-implemen.patch
deleted file mode 100644
index 2c0d10e..0000000
--- a/resources/libreboot/patch/0010-mainboard-lenovo-t400-Add-initial-ATPX-ACPI-implemen.patch
+++ /dev/null
@@ -1,138 +0,0 @@
-From 83483e772d5b19b52b82e2518805be2e305e6a27 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <tpearson@raptorengineeringinc.com>
-Date: Sun, 5 Apr 2015 23:22:18 -0500
-Subject: [PATCH 10/22] mainboard/lenovo/t400: Add initial ATPX ACPI
- implementation
-
-Change-Id: I9b86ebec59ccb63db0e1ba61533d162507a22379
-Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
----
- src/mainboard/lenovo/t400/acpi/graphics.asl | 101 ++++++++++++++++++++++++++++
- src/mainboard/lenovo/t400/dsdt.asl          |   3 +
- 2 files changed, 104 insertions(+)
- create mode 100644 src/mainboard/lenovo/t400/acpi/graphics.asl
-
-diff --git a/src/mainboard/lenovo/t400/acpi/graphics.asl b/src/mainboard/lenovo/t400/acpi/graphics.asl
-new file mode 100644
-index 0000000..e928d77
---- /dev/null
-+++ b/src/mainboard/lenovo/t400/acpi/graphics.asl
-@@ -0,0 +1,101 @@
-+/*
-+ * This file is part of the coreboot project.
-+ *
-+ * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; version 2 of the License.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-+ */
-+
-+/* WARNING
-+ * Switchable graphics not yet tested!
-+ */
-+
-+/* Hybrid graphics enable/disable GPIO bitfields */
-+Name (HYG1, 0x004A0000)
-+Name (HYG2, 0x00020000)
-+
-+/* GPIO control port */
-+Name (GPCP, DEFAULT_GPIOBASE)
-+
-+/* GPIO control map */
-+OperationRegion (GPCM, SystemIO, GPCP, 0x3F)
-+Field (GPCM, ByteAcc, NoLock, Preserve) {
-+	GPUS, 32,
-+	GPIS, 32,
-+	Offset (0x0C),
-+	GPLV, 32,
-+	Offset (0x30),
-+	GQUS, 32,
-+	GQIS, 32,
-+	GQLV, 32
-+}
-+
-+Method(SHYB, 1) {
-+	/* Switch hybrid graphics */
-+	if (LEqual(Arg0, One))
-+	{
-+		/* Discrete graphics requested */
-+		Or(GPLV, HYG1, GPLV)
-+		Or(GQLV, HYG2, GQLV)
-+	}
-+	else
-+	{
-+		/* Integrated graphics requested */
-+		Xor(HYG1, 0xFFFFFFFF, Local0)
-+		And(GPLV, Local0, GPLV)
-+		Xor(HYG2, 0xFFFFFFFF, Local0)
-+		And(GQLV, Local0, GQLV)
-+	}
-+}
-+
-+Method (ATPX, 2, NotSerialized) {
-+	/* Create local variables */
-+	Name (ATPR, Buffer (0x08) {
-+		0x0, 0x0, 0x0, 0x0,
-+		0x0, 0x0, 0x0, 0x0
-+	})
-+	CreateWordField (ATPR, 0x00, SIZE)
-+	CreateWordField (ATPR, 0x02, VERS)
-+	CreateDWordField (ATPR, 0x02, MASK)
-+	CreateDWordField (ATPR, 0x04, FUNC)
-+	CreateDWordField (ATPR, 0x06, FLAG)
-+
-+	/* Version request */
-+	if (LEqual(Arg0, 0x0))
-+	{
-+		/* Assemble and return version information */
-+		Store (0x08, SIZE)	/* Response length */
-+		Store (0x01, VERS)	/* Version number */
-+		Store (0x0F, FUNC)	/* Supported functions? */
-+		Return (ATPR)
-+	}
-+
-+	/* Mux select */
-+	if (LEqual(Arg0, 0x2))
-+	{
-+		CreateByteField (Arg1, 0x02, PWST)
-+		Store (PWST, Local0)
-+		And (Local0, 0x01, Local0)
-+		If (Local0)
-+		{
-+			/* Enable discrete graphics */
-+			SHYB(0x01)
-+		}
-+		else
-+		{
-+			/* Enable integrated graphics */
-+			SHYB(0x00)
-+		}
-+	}
-+}
-diff --git a/src/mainboard/lenovo/t400/dsdt.asl b/src/mainboard/lenovo/t400/dsdt.asl
-index 0409e66..d2582ce 100644
---- a/src/mainboard/lenovo/t400/dsdt.asl
-+++ b/src/mainboard/lenovo/t400/dsdt.asl
-@@ -54,6 +54,9 @@ DefinitionBlock(
- 	/* Chipset specific sleep states */
- 	#include <southbridge/intel/i82801ix/acpi/sleepstates.asl>
- 
-+	/* Hybrid graphics support code */
-+	#include "acpi/graphics.asl"
-+
- 	/* Dock support code */
- 	#include "acpi/dock.asl"
- }
--- 
-1.9.1
-
diff --git a/resources/libreboot/patch/0011-mainboard-lenovo-t400-Increase-backlight-frequency-t.patch b/resources/libreboot/patch/0011-mainboard-lenovo-t400-Increase-backlight-frequency-t.patch
deleted file mode 100644
index 28bdf45..0000000
--- a/resources/libreboot/patch/0011-mainboard-lenovo-t400-Increase-backlight-frequency-t.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From f50edfa55ae12a6575c502b00f9f42e283cc9c4b Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <tpearson@raptorengineeringinc.com>
-Date: Mon, 6 Apr 2015 22:02:18 -0500
-Subject: [PATCH 11/22] mainboard/lenovo/t400: Increase backlight frequency to
- reduce flicker
-
-TEST: Booted Lenovo T400 with LED backlight and verified the absence
-of any visible flicker along with proper operation of the brightness
-control.
-
-Change-Id: Ifb485f4aad385aac794978527fd7d246f444ea08
-Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
----
- src/mainboard/lenovo/t400/devicetree.cb | 2 ++
- 1 file changed, 2 insertions(+)
-
-diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb
-index cc27d25..6280b91 100644
---- a/src/mainboard/lenovo/t400/devicetree.cb
-+++ b/src/mainboard/lenovo/t400/devicetree.cb
-@@ -5,6 +5,8 @@ chip northbridge/intel/gm45
- 	register "gfx.link_frequency_270_mhz" = "1"
- 	register "gfx.lvds_num_lanes" = "4"
- 
-+	register "gfx.backlight" = "0x620062"
-+
- 	device cpu_cluster 0 on
- 		chip cpu/intel/socket_BGA956
- 			device lapic 0 on end
--- 
-1.9.1
-
diff --git a/resources/libreboot/patch/0019-NOTFORMERGE-northbridge-gm45-raminit.c-enable-GS45-h.patch b/resources/libreboot/patch/0011-northbridge-gm45-raminit.c-enable-GS45-high-performa.patch
index 8626071..d41363f 100644
--- a/resources/libreboot/patch/0019-NOTFORMERGE-northbridge-gm45-raminit.c-enable-GS45-h.patch
+++ b/resources/libreboot/patch/0011-northbridge-gm45-raminit.c-enable-GS45-high-performa.patch
@@ -1,39 +1,30 @@
-From 8747a02e76193b8764088ca25784a5e41969e357 Mon Sep 17 00:00:00 2001
-From: Francis Rowe <info@gluglug.org.uk>
+From 3b67763d6029ce954cea0dbc02ff6814b7c02478 Mon Sep 17 00:00:00 2001
+From: Steve Shenton <sgsit@libreboot.org>
 Date: Fri, 12 Dec 2014 12:42:01 +0000
-Subject: [PATCH 19/22] NOTFORMERGE: northbridge/gm45/raminit.c: enable GS45
- high-perf
-
-X200S uses GS45 chipset, unlike X200 which uses GM45. These two
-chipsets are mostly compatible except for raminit.
+Subject: [PATCH 11/17] northbridge/gm45/raminit.c: enable GS45
+ high-performance mode
 
 The datasheets for GS45 describe a high- and low-performance mode
-for different CPU's. Coreboot currently disables GS45 altogether,
+for different CPUs. Coreboot currently disables GS45 altogether,
 but forcing coreboot to treat high-performance GS45 as GM45 makes
-the X200S boot with certain RAM configurations.
-
-1x2GB fails: http://paste.debian.net/hidden/ae66cff7/
-2x2GB fails: http://paste.debian.net/hidden/8802e220/
-2x4GB boots: http://paste.debian.net/hidden/61114378/
+the X200S and X200 Tablet boot if it has the right CPU type.
 
 Hardcode-enable GS45 high-performance mode in coreboot, passing it
-off as GM45. This is known to work with all CPU's except the SU
+off as GM45. This is known to work with all CPUs except the SU
 (low performance) models.
 
-Patch courtesy of sgsit.
-
 Change-Id: I57032bb6e1ebdaf4e2aa09548e73d253afb9b078
-Signed-off-by: Francis Rowe <info@gluglug.org.uk>
 Signed-off-by: Steve Shenton <sgsit@libreboot.org>
+Signed-off-by: Francis Rowe <info@gluglug.org.uk>
 ---
  src/northbridge/intel/gm45/raminit.c | 6 +++---
  1 file changed, 3 insertions(+), 3 deletions(-)
 
 diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
-index 2c810de..a194c85 100644
+index 9c4fecd..9f5aa06 100644
 --- a/src/northbridge/intel/gm45/raminit.c
 +++ b/src/northbridge/intel/gm45/raminit.c
-@@ -109,8 +109,8 @@ void get_gmch_info(sysinfo_t *sysinfo)
+@@ -108,8 +108,8 @@ void get_gmch_info(sysinfo_t *sysinfo)
  			printk(BIOS_SPEW, "GMCH: GS40\n");
  			break;
  		case GMCH_GS45:
@@ -44,7 +35,7 @@ index 2c810de..a194c85 100644
  			break;
  		case GMCH_PM45:
  			printk(BIOS_SPEW, "GMCH: PM45\n");
-@@ -1693,7 +1693,7 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume)
+@@ -1692,7 +1692,7 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume)
  {
  	const dimminfo_t *const dimms = sysinfo->dimms;
  	const timings_t *const timings = &sysinfo->selected_timings;
diff --git a/resources/libreboot/patch/0020-gm45-fix-uneven-backlight-native-gfx-init.patch b/resources/libreboot/patch/0012-gm45-fix-uneven-backlight-native-gfx-init.patch
index a2afa53..1172d61 100644
--- a/resources/libreboot/patch/0020-gm45-fix-uneven-backlight-native-gfx-init.patch
+++ b/resources/libreboot/patch/0012-gm45-fix-uneven-backlight-native-gfx-init.patch
@@ -1,7 +1,7 @@
-From 512caf2594be34e07383b8a5d5e9e2013c6e2067 Mon Sep 17 00:00:00 2001
+From cb40445b1debc5900835f94d0aa3287cc213a0d5 Mon Sep 17 00:00:00 2001
 From: Francis Rowe <info@gluglug.org.uk>
 Date: Mon, 29 Dec 2014 21:02:48 +0000
-Subject: [PATCH 20/22] gm45: fix uneven backlight (native gfx init)
+Subject: [PATCH 12/17] gm45: fix uneven backlight (native gfx init)
 
 When setting brightness levels low, backlight becomes uneven.
 This patch fixes that.
@@ -15,27 +15,28 @@ Signed-off-by: Francis Rowe <info@gluglug.org.uk>
  1 file changed, 3 insertions(+), 3 deletions(-)
 
 diff --git a/src/northbridge/intel/gm45/acpi/igd.asl b/src/northbridge/intel/gm45/acpi/igd.asl
-index 199765b..6f0eb8c 100644
+index 696cc2b..39fefb2 100644
 --- a/src/northbridge/intel/gm45/acpi/igd.asl
 +++ b/src/northbridge/intel/gm45/acpi/igd.asl
-@@ -206,14 +206,14 @@ Device (GFX0)
+@@ -62,15 +62,15 @@ Device (GFX0)
  
- 		Method (_BCM, 1, NotSerialized)
- 		{
--			Store (ShiftLeft (Arg0, 4), ^^BCLV)
-+			Store (ShiftLeft (Arg0, 8), ^^BCLV)
- 			Store (0x80000000, ^^CR1)
--			Store (0x0610, ^^BCLM)
-+			Store (ShiftLeft (0x61, 8), ^^BCLM)
- 		}
- 		Method (_BQC, 0, NotSerialized)
- 		{
- 			Store (^^BCLV, Local0)
--			ShiftRight (Local0, 4, Local0)
-+			ShiftRight (Local0, 8, Local0)
- 			Return (Local0)
- 		}
+ 	Method (XBCM, 1, NotSerialized)
+ 	{
+-		Store (ShiftLeft (Arg0, 4), BCLV)
++		Store (ShiftLeft (Arg0, 8), BCLV)
+ 		Store (0x80000000, CR1)
+-		Store (0x0610, BCLM)
++		Store (ShiftLeft (0x61, 8), BCLM)
+ 	}
  
+ 	Method (XBQC, 0, NotSerialized)
+ 	{
+ 		Store (BCLV, Local0)
+-		ShiftRight (Local0, 4, Local0)
++		ShiftRight (Local0, 8, Local0)
+ 		Return (Local0)
+ 	}
+ #include <drivers/intel/gma/igd.asl>
 -- 
 1.9.1
 
diff --git a/resources/libreboot/patch/0021-lenovo-r400-Add-clone-of-Lenovo-T400.patch b/resources/libreboot/patch/0013-lenovo-r400-Add-clone-of-Lenovo-T400.patch
index ceebdac..04f7076 100644
--- a/resources/libreboot/patch/0021-lenovo-r400-Add-clone-of-Lenovo-T400.patch
+++ b/resources/libreboot/patch/0013-lenovo-r400-Add-clone-of-Lenovo-T400.patch
@@ -1,59 +1,28 @@
-From 264b65a2a8220c120297173fd9d6bab9880965f1 Mon Sep 17 00:00:00 2001
+From f5755e978b6a1b10adb0bfeb4c3fd790315c4848 Mon Sep 17 00:00:00 2001
 From: =?UTF-8?q?Micha=C5=82=20Mas=C5=82owski?= <mtjm@mtjm.eu>
 Date: Tue, 3 Feb 2015 23:26:05 +0100
-Subject: [PATCH 21/22] lenovo/r400: Add clone of Lenovo T400
+Subject: [PATCH 13/17] lenovo/r400: Add clone of Lenovo T400
 MIME-Version: 1.0
 Content-Type: text/plain; charset=UTF-8
 Content-Transfer-Encoding: 8bit
 
 The existing code for the Lenovo T400 works without changes on the
-Lenovo R400.
-
-The vendor BIOS provides different HDA verbs as the connectors are on
-the front and not the right, but this doesn't provide enough benefit
-to justify having different source files.
-
-This used to be based on the X200 code, now based on T400. This
-should still be replaced with a separate port, with the
-differences implemented, instead of being a clone.
+Lenovo R400.  Same HDA verbs are provided by Lenovo BIOS on both
+laptops.
 
 Change-Id: I1dadddd7250ab80a4c40c2435865d72e3e5d99c9
 Signed-off-by: Michał Masłowski <mtjm@mtjm.eu>
 Signed-off-by: Francis Rowe <info@gluglug.org.uk>
 ---
- src/mainboard/lenovo/Kconfig             | 6 ++++++
  src/mainboard/lenovo/r400/Kconfig        | 7 +++++++
+ src/mainboard/lenovo/r400/Kconfig.name   | 2 ++
  src/mainboard/lenovo/r400/board_info.txt | 6 ++++++
  src/mainboard/lenovo/t400/Kconfig        | 6 +++++-
- util/nvidia/cbootimage                   | 2 +-
- 5 files changed, 25 insertions(+), 2 deletions(-)
+ 4 files changed, 20 insertions(+), 1 deletion(-)
  create mode 100644 src/mainboard/lenovo/r400/Kconfig
+ create mode 100644 src/mainboard/lenovo/r400/Kconfig.name
  create mode 100644 src/mainboard/lenovo/r400/board_info.txt
 
-diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig
-index b6da044..4fc56cd 100644
---- a/src/mainboard/lenovo/Kconfig
-+++ b/src/mainboard/lenovo/Kconfig
-@@ -70,6 +70,11 @@ config BOARD_LENOVO_G505S
- 	help
- 	  Lenovo G505s
- 
-+config BOARD_LENOVO_R400
-+	bool "ThinkPad R400"
-+	help
-+	  Lenovo R400 laptop. Consult wiki for details.
-+
- endchoice
- 
- source "src/mainboard/lenovo/x60/Kconfig"
-@@ -84,6 +89,7 @@ source "src/mainboard/lenovo/t520/Kconfig"
- source "src/mainboard/lenovo/t530/Kconfig"
- source "src/mainboard/lenovo/t60/Kconfig"
- source "src/mainboard/lenovo/g505s/Kconfig"
-+source "src/mainboard/lenovo/r400/Kconfig"
- 
- config MAINBOARD_VENDOR
- 	string
 diff --git a/src/mainboard/lenovo/r400/Kconfig b/src/mainboard/lenovo/r400/Kconfig
 new file mode 100644
 index 0000000..0966bf1
@@ -67,6 +36,14 @@ index 0000000..0966bf1
 +	default "ThinkPad R400"
 +
 +endif
+diff --git a/src/mainboard/lenovo/r400/Kconfig.name b/src/mainboard/lenovo/r400/Kconfig.name
+new file mode 100644
+index 0000000..15a99b1
+--- /dev/null
++++ b/src/mainboard/lenovo/r400/Kconfig.name
+@@ -0,0 +1,2 @@
++config BOARD_LENOVO_R400
++	bool "ThinkPad R400"
 diff --git a/src/mainboard/lenovo/r400/board_info.txt b/src/mainboard/lenovo/r400/board_info.txt
 new file mode 100644
 index 0000000..007ec6c
@@ -80,7 +57,7 @@ index 0000000..007ec6c
 +Flashrom support: n
 +Clone of: lenovo/t400
 diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig
-index a38af5e..719f6e4 100644
+index a1d0652..2ea592f 100644
 --- a/src/mainboard/lenovo/t400/Kconfig
 +++ b/src/mainboard/lenovo/t400/Kconfig
 @@ -1,4 +1,4 @@
@@ -89,7 +66,7 @@ index a38af5e..719f6e4 100644
  
  config BOARD_SPECIFIC_OPTIONS # dummy
  	def_bool y
-@@ -25,10 +25,14 @@ config MAINBOARD_DIR
+@@ -26,10 +26,14 @@ config MAINBOARD_DIR
  	string
  	default lenovo/t400
  
@@ -104,13 +81,6 @@ index a38af5e..719f6e4 100644
  config MMCONF_BASE_ADDRESS
  	hex
  	default 0xf0000000
-diff --git a/util/nvidia/cbootimage b/util/nvidia/cbootimage
-index 2eb9a86..b7d5b2d 160000
---- a/util/nvidia/cbootimage
-+++ b/util/nvidia/cbootimage
-@@ -1 +1 @@
--Subproject commit 2eb9a86724db0d86c9ab9b6aeca21d1000d74e78
-+Subproject commit b7d5b2d6a6dd05874d86ee900ff441d261f9034c
 -- 
 1.9.1
 
diff --git a/resources/libreboot/patch/0022-New-mainboard-Lenovo-T500.patch b/resources/libreboot/patch/0014-lenovo-t500-Add-clone-of-Lenovo-T400.patch
index 96e2b4a..dee34fe 100644
--- a/resources/libreboot/patch/0022-New-mainboard-Lenovo-T500.patch
+++ b/resources/libreboot/patch/0014-lenovo-t500-Add-clone-of-Lenovo-T400.patch
@@ -1,53 +1,31 @@
-From 0413e35202f8336418fd9bdd19eb6e9e599f9dfc Mon Sep 17 00:00:00 2001
+From 44b02659da616c6d64445e5645684a68e7e5e742 Mon Sep 17 00:00:00 2001
 From: Francis Rowe <info@gluglug.org.uk>
-Date: Tue, 31 Mar 2015 22:51:22 +0100
-Subject: [PATCH 22/22] New mainboard: Lenovo T500
+Date: Sun, 14 Jun 2015 15:40:00 +0100
+Subject: [PATCH 14/17] lenovo/t500: Add clone of Lenovo T400
 
-Clone of Lenovo T400. It works/boots, but needs
-more testing.
+The existing code for the Lenovo T400 works without changes on the
+Lenovo T500.  Same HDA verbs are provided by Lenovo BIOS on both
+laptops.
 
-Change-Id: I7ace604ca7fede44ce78277561d31e3083fc6c8c
+Change-Id: I300408a8a0ed00476aee6061925befc2822fb505
 Signed-off-by: Francis Rowe <info@gluglug.org.uk>
 ---
- src/mainboard/lenovo/Kconfig             | 6 ++++++
  src/mainboard/lenovo/t400/Kconfig        | 2 +-
  src/mainboard/lenovo/t500/Kconfig        | 7 +++++++
+ src/mainboard/lenovo/t500/Kconfig.name   | 2 ++
  src/mainboard/lenovo/t500/board_info.txt | 6 ++++++
- 4 files changed, 20 insertions(+), 1 deletion(-)
+ 4 files changed, 16 insertions(+), 1 deletion(-)
  create mode 100644 src/mainboard/lenovo/t500/Kconfig
+ create mode 100644 src/mainboard/lenovo/t500/Kconfig.name
  create mode 100644 src/mainboard/lenovo/t500/board_info.txt
 
-diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig
-index 4fc56cd..3dee443 100644
---- a/src/mainboard/lenovo/Kconfig
-+++ b/src/mainboard/lenovo/Kconfig
-@@ -47,6 +47,11 @@ config BOARD_LENOVO_T430S
- 	help
- 	  Lenovo T430s laptop. Consult wiki for details.
- 
-+config BOARD_LENOVO_T500
-+	bool "ThinkPad T500"
-+	help
-+	  Lenovo T500 laptop. Consult wiki for details.
-+
- config BOARD_LENOVO_T520
- 	bool "ThinkPad T520"
- 	help
-@@ -85,6 +90,7 @@ source "src/mainboard/lenovo/x230/Kconfig"
- source "src/mainboard/lenovo/t400/Kconfig"
- source "src/mainboard/lenovo/t420s/Kconfig"
- source "src/mainboard/lenovo/t430s/Kconfig"
-+source "src/mainboard/lenovo/t500/Kconfig"
- source "src/mainboard/lenovo/t520/Kconfig"
- source "src/mainboard/lenovo/t530/Kconfig"
- source "src/mainboard/lenovo/t60/Kconfig"
 diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig
-index 719f6e4..9afb8ce 100644
+index 2ea592f..b1f7d28 100644
 --- a/src/mainboard/lenovo/t400/Kconfig
 +++ b/src/mainboard/lenovo/t400/Kconfig
 @@ -1,4 +1,4 @@
 -if BOARD_LENOVO_T400 || BOARD_LENOVO_R400
-+if BOARD_LENOVO_T400 || BOARD_LENOVO_R400 || BOARD_LENOVO_T500
++if BOARD_LENOVO_T400 || BOARD_LENOVO_T500 || BOARD_LENOVO_R400
  
  config BOARD_SPECIFIC_OPTIONS # dummy
  	def_bool y
@@ -64,6 +42,14 @@ index 0000000..e1e8420
 +	default "ThinkPad T500"
 +
 +endif
+diff --git a/src/mainboard/lenovo/t500/Kconfig.name b/src/mainboard/lenovo/t500/Kconfig.name
+new file mode 100644
+index 0000000..89c6087
+--- /dev/null
++++ b/src/mainboard/lenovo/t500/Kconfig.name
+@@ -0,0 +1,2 @@
++config BOARD_LENOVO_T500
++	bool "ThinkPad T500"
 diff --git a/src/mainboard/lenovo/t500/board_info.txt b/src/mainboard/lenovo/t500/board_info.txt
 new file mode 100644
 index 0000000..007ec6c
diff --git a/resources/libreboot/patch/0015-ec-lenovo-h8-re-factor-handling-of-power_management_.patch b/resources/libreboot/patch/0015-ec-lenovo-h8-re-factor-handling-of-power_management_.patch
new file mode 100644
index 0000000..e5d6deb
--- /dev/null
+++ b/resources/libreboot/patch/0015-ec-lenovo-h8-re-factor-handling-of-power_management_.patch
@@ -0,0 +1,53 @@
+From 5fdab56649a84249c8eecd30caa34318ebde6b1d Mon Sep 17 00:00:00 2001
+From: Francis Rowe <info@gluglug.org.uk>
+Date: Fri, 12 Jun 2015 23:10:52 +0100
+Subject: [PATCH 15/17] ec/lenovo/h8: re-factor handling of
+ power_management_beeps
+
+The current code duplicates the same check unnecessarily,
+and has no handling of when the option power_management_beeps
+is not set.
+
+Change-Id: I189c5ce382e1a270d24b9b6e897358268b9a141d
+Signed-off-by: Francis Rowe <info@gluglug.org.uk>
+---
+ src/ec/lenovo/h8/h8.c | 15 ++++++++-------
+ 1 file changed, 8 insertions(+), 7 deletions(-)
+
+diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c
+index b6bc406..fde408c 100644
+--- a/src/ec/lenovo/h8/h8.c
++++ b/src/ec/lenovo/h8/h8.c
+@@ -2,6 +2,7 @@
+  * This file is part of the coreboot project.
+  *
+  * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
++ * Copyright (C) 2015 Francis Rowe <info@gluglug.org.uk>
+  *
+  * This program is free software; you can redistribute it and/or modify
+  * it under the terms of the GNU General Public License as published by
+@@ -212,14 +213,14 @@ static void h8_enable(struct device *dev)
+ 	beepmask0 = conf->beepmask0;
+ 	beepmask1 = conf->beepmask1;
+ 
+-	if (conf->has_power_management_beeps
+-	    && get_option(&val, "power_management_beeps") == CB_SUCCESS
+-	    && val == 0) {
+-		beepmask0 = 0x00;
+-		beepmask1 = 0x00;
+-	}
+-
+ 	if (conf->has_power_management_beeps) {
++		if (get_option(&val, "power_management_beeps") != CB_SUCCESS)
++			val = 1;
++		if (!val) {
++			beepmask0 = 0x00;
++			beepmask1 = 0x00;
++		}
++
+ 		if (get_option(&val, "low_battery_beep") != CB_SUCCESS)
+ 			val = 1;
+ 		if (val)
+-- 
+1.9.1
+
diff --git a/resources/libreboot/patch/0016-buildgcc-Define-CMAKE-only-if-clang-package-is-built.patch b/resources/libreboot/patch/0016-buildgcc-Define-CMAKE-only-if-clang-package-is-built.patch
new file mode 100644
index 0000000..b303292
--- /dev/null
+++ b/resources/libreboot/patch/0016-buildgcc-Define-CMAKE-only-if-clang-package-is-built.patch
@@ -0,0 +1,41 @@
+From beb6138691594cd227a1b50079d14e6adc4e8ef5 Mon Sep 17 00:00:00 2001
+From: David Hendricks <dhendrix@chromium.org>
+Date: Mon, 15 Jun 2015 17:03:22 -0700
+Subject: [PATCH] buildgcc: Define $CMAKE only if clang package is built
+
+This moves the CMAKE definition down into the case statement
+for $PACKAGE so that it is only required when the user wants to
+build clang.
+
+With this approach, "./buildgcc -P clang" will error out with the
+"ERROR: Missing tool:" message if cmake is not installed.
+
+Change-Id: I1e5c1bd67ade8f93ba0390df7f234deb47b9b18a
+Signed-off-by: David Hendricks <dhendrix@chromium.org>
+---
+ util/crossgcc/buildgcc | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
+index 7f440f7..552a6a2 100755
+--- a/util/crossgcc/buildgcc
++++ b/util/crossgcc/buildgcc
+@@ -165,7 +165,6 @@ searchtool()
+ TAR=$(searchtool tar) || exit $?
+ PATCH=$(searchtool patch) || exit $?
+ MAKE=$(searchtool make) || exit $?
+-CMAKE=$(searchtool cmake "cmake") || exit $?
+ SHA1SUM=$(searchtool sha1sum)
+ SHA512SUM=$(searchtool sha512sum)
+ CHECKSUM=$SHA1SUM
+@@ -554,6 +553,7 @@ case "$PACKAGE" in
+ 	CLANG|clang)
+ 		NAME=clang
+ 		PACKAGES="LLVM CFE CRT CTE"
++		CMAKE=$(searchtool cmake "cmake") || exit $?
+ 		;;
+ 	IASL|iasl)
+ 		NAME="IASL ACPI compiler"
+-- 
+1.9.1
+
diff --git a/resources/libreboot/patch/0023-lenovo-x200-Enable-wacom-digitizer-support-for-x200t.patch b/resources/libreboot/patch/0023-lenovo-x200-Enable-wacom-digitizer-support-for-x200t.patch
deleted file mode 100644
index 6072af8..0000000
--- a/resources/libreboot/patch/0023-lenovo-x200-Enable-wacom-digitizer-support-for-x200t.patch
+++ /dev/null
@@ -1,117 +0,0 @@
-From 201f57c0a7dfa37bbb47a3f989d35ff00f6a9fe6 Mon Sep 17 00:00:00 2001
-From: Alex David <opdecirkel@gmail.com>
-Date: Sun, 17 May 2015 12:52:54 +0100
-Subject: [PATCH] lenovo/x200: Enable wacom digitizer support for x200t
-
-This patch is based on commit f2b3cd63
-(lenovo/x60: Support digitizer on X60t and X201t)
-
-Tested on Thinkpad X200 Tablet (7450): all pen functionallity
-works (i.e. movements, presure sensitivity and buttons)
-
-THIS IS A REBASE (BACKPORT)
-It's used on an older coreboot revision for this release.
-This patch will be deleted when libreboot next updates
-itself, because the patch is merged now in coreboot upstream.
-
-Signed-off-by: Alex David <opdecirkel@gmail.com>
-Signed-off-by: Francis Rowe <info@gluglug.org.uk>
----
- src/drivers/lenovo/wacom.c              |  3 ++-
- src/mainboard/lenovo/x200/Kconfig       |  2 ++
- src/mainboard/lenovo/x200/devicetree.cb | 16 ++++++++++++++++
- src/mainboard/lenovo/x200/mainboard.c   |  7 +++++++
- 4 files changed, 27 insertions(+), 1 deletion(-)
-
-diff --git a/src/drivers/lenovo/wacom.c b/src/drivers/lenovo/wacom.c
-index 7368afe..2e899f8 100644
---- a/src/drivers/lenovo/wacom.c
-+++ b/src/drivers/lenovo/wacom.c
-@@ -34,10 +34,11 @@ static const char tablet_numbers[][5] = {
- 	"6363", "6364", "6365", "6366",
- 	"6367", "6368", "7762", "7763",
- 	"7764", "7767", "7768", "7769",
-+	/* X200t. */
-+	"7448", "7449", "7450", "7453",
- 	/* X201t. */
- 	"0053", "0831", "2985", "3093",
- 	"3113", "3144", "3239", "4184",
--	"7448", "7449", "7450", "7453",
- 	"2263", "2266",
- };
- 
-diff --git a/src/mainboard/lenovo/x200/Kconfig b/src/mainboard/lenovo/x200/Kconfig
-index 01556b3..7bae12d 100644
---- a/src/mainboard/lenovo/x200/Kconfig
-+++ b/src/mainboard/lenovo/x200/Kconfig
-@@ -21,6 +21,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
- 	select MAINBOARD_HAS_NATIVE_VGA_INIT
- 	select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG
- 	select INTEL_INT15
-+	select SUPERIO_NSC_PC87382
-+	select DRIVERS_LENOVO_WACOM
- 
- config MAINBOARD_DIR
- 	string
-diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb
-index cc27d25..09bc08f 100644
---- a/src/mainboard/lenovo/x200/devicetree.cb
-+++ b/src/mainboard/lenovo/x200/devicetree.cb
-@@ -176,6 +176,22 @@ chip northbridge/intel/gm45
- 					register "eventc_enable" = "0xff"
- 					register "eventd_enable" = "0xff"
- 				end
-+
-+				chip superio/nsc/pc87382
-+					device pnp 164e.3 on # Digitizer
-+						io 0x60 = 0x200
-+						irq 0x29 = 0xb0
-+						irq 0x70 = 0x5
-+						irq 0xf0 = 0x82
-+					end
-+					# IR, not connected
-+					device pnp 164e.2 off end
-+					# GPIO, not connected
-+					device pnp 164e.7 off end
-+					# DLPC, not connected
-+					device pnp 164e.19 off end
-+				end
-+
- 			end
- 			device pci 1f.2 on # SATA/IDE 1
- 				subsystemid 0x17aa 0x20f8
-diff --git a/src/mainboard/lenovo/x200/mainboard.c b/src/mainboard/lenovo/x200/mainboard.c
-index 5354834..0ecffda 100644
---- a/src/mainboard/lenovo/x200/mainboard.c
-+++ b/src/mainboard/lenovo/x200/mainboard.c
-@@ -31,6 +31,7 @@
- #include <ec/lenovo/pmh7/pmh7.h>
- #include <ec/acpi/ec.h>
- #include <ec/lenovo/h8/h8.h>
-+#include "drivers/lenovo/lenovo.h"
- 
- #include "cstates.c" /* Include it, as the linker won't find
- 			the overloaded weak function in there. */
-@@ -49,6 +50,11 @@ const char *smbios_mainboard_bios_version(void)
- 	return s;
- }
- 
-+static void fill_ssdt(void)
-+{
-+	drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 0);
-+}
-+
- static void mainboard_init(device_t dev)
- {
- 	/* This sneaked in here, because X200 SuperIO chip isn't really
-@@ -62,6 +68,7 @@ static void mainboard_enable(device_t dev)
- 	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 2);
- 
- 	dev->ops->init = mainboard_init;
-+	dev->ops->acpi_fill_ssdt_generator = fill_ssdt;
- }
- 
- struct chip_operations mainboard_ops = {
--- 
-1.9.1
-