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authorLeah Rowe <info@minifree.org>2016-06-27 23:09:08 (EDT)
committer Leah Rowe <info@minifree.org>2016-06-27 23:09:08 (EDT)
commitd89e0ec8579e894c9ba8a846eafd7052171e497a (patch)
treec0a3ace528197b1e381f210ac63a2621c94b52ba /resources/libreboot/patch/misc/0006-northbridge-gm45-raminit.c-enable-GS45-high-performa.patch
parent104e26ba424d05e822ae58ff2c7b6f6f159588d5 (diff)
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Backport changes to master branch
Diffstat (limited to 'resources/libreboot/patch/misc/0006-northbridge-gm45-raminit.c-enable-GS45-high-performa.patch')
-rw-r--r--resources/libreboot/patch/misc/0006-northbridge-gm45-raminit.c-enable-GS45-high-performa.patch2
1 files changed, 1 insertions, 1 deletions
diff --git a/resources/libreboot/patch/misc/0006-northbridge-gm45-raminit.c-enable-GS45-high-performa.patch b/resources/libreboot/patch/misc/0006-northbridge-gm45-raminit.c-enable-GS45-high-performa.patch
index 95cf2c4..45623e7 100644
--- a/resources/libreboot/patch/misc/0006-northbridge-gm45-raminit.c-enable-GS45-high-performa.patch
+++ b/resources/libreboot/patch/misc/0006-northbridge-gm45-raminit.c-enable-GS45-high-performa.patch
@@ -19,7 +19,7 @@ compatibility to a whole new chipset (GS45), depending on the CPU.
Change-Id: I2719385e93c37d254ce38e0f5f486262160234e1
Signed-off-by: Steve Shenton <sgsit@libreboot.org>
-Signed-off-by: Leah Woods <info@minifree.org>
+Signed-off-by: Leah Rowe <info@minifree.org>
---
src/northbridge/intel/gm45/raminit.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)