diff options
| author | Francis Rowe <info@gluglug.org.uk> | 2015-11-06 02:45:49 (EST) |
|---|---|---|
| committer | Francis Rowe <info@gluglug.org.uk> | 2015-11-06 03:01:51 (EST) |
| commit | 60453ff2cbd1befe24959fba1d24f734406444e3 (patch) | |
| tree | 74a6080455b2b00184fbc4a00503188032773986 /resources/libreboot/patch/kgpe-d16/0118-southbridge-amd-sr5650-Use-correct-PCI-configuration.patch | |
| parent | 51f5487e7d2c8809bdc7690fe26948064257b34d (diff) | |
| download | libreboot-60453ff2cbd1befe24959fba1d24f734406444e3.zip libreboot-60453ff2cbd1befe24959fba1d24f734406444e3.tar.gz libreboot-60453ff2cbd1befe24959fba1d24f734406444e3.tar.bz2 | |
Update coreboot to new version (use latest stable kgpe-d16 tree)
Diffstat (limited to 'resources/libreboot/patch/kgpe-d16/0118-southbridge-amd-sr5650-Use-correct-PCI-configuration.patch')
| -rw-r--r-- | resources/libreboot/patch/kgpe-d16/0118-southbridge-amd-sr5650-Use-correct-PCI-configuration.patch | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/resources/libreboot/patch/kgpe-d16/0118-southbridge-amd-sr5650-Use-correct-PCI-configuration.patch b/resources/libreboot/patch/kgpe-d16/0118-southbridge-amd-sr5650-Use-correct-PCI-configuration.patch new file mode 100644 index 0000000..27fd1c2 --- /dev/null +++ b/resources/libreboot/patch/kgpe-d16/0118-southbridge-amd-sr5650-Use-correct-PCI-configuration.patch @@ -0,0 +1,30 @@ +From f5d5d25583a6aee7f725a6de8cc0a51753502666 Mon Sep 17 00:00:00 2001 +From: Timothy Pearson <tpearson@raptorengineeringinc.com> +Date: Fri, 14 Aug 2015 02:50:44 -0500 +Subject: [PATCH 118/143] southbridge/amd/sr5650: Use correct PCI + configuration block offset + +Change-Id: I4277d1788d8f9a501399218544aa6d4d11349ccc +Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> +--- + src/southbridge/amd/sr5650/acpi/sr5650.asl | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/src/southbridge/amd/sr5650/acpi/sr5650.asl b/src/southbridge/amd/sr5650/acpi/sr5650.asl +index a6ab114..1e0d5b0 100644 +--- a/src/southbridge/amd/sr5650/acpi/sr5650.asl ++++ b/src/southbridge/amd/sr5650/acpi/sr5650.asl +@@ -19,8 +19,8 @@ + */ + + Scope(\) { +- Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ +- Name(HPBA, 0xFED00000) /* Base address of HPET table */ ++ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ ++ Name(HPBA, 0xFED00000) /* Base address of HPET table */ + + /* PIC IRQ mapping registers, C00h-C01h */ + OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) +-- +1.7.9.5 + |