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| author | Francis Rowe <info@gluglug.org.uk> | 2015-10-17 11:10:53 (EDT) |
|---|---|---|
| committer | Francis Rowe <info@gluglug.org.uk> | 2015-10-17 14:07:35 (EDT) |
| commit | 5999dba5f71f1c05040a551d2420ab8c7f3a9da4 (patch) | |
| tree | 7313b1996a247bf938417d5cf2496f5f6625c0db /resources/libreboot/patch/kgpe-d16/0114-southbridge-amd-sr5650-Hide-clock-configuration-devi.patch | |
| parent | 4d909153e79661e54999e51693668f6d1ecc1cca (diff) | |
| download | libreboot-5999dba5f71f1c05040a551d2420ab8c7f3a9da4.zip libreboot-5999dba5f71f1c05040a551d2420ab8c7f3a9da4.tar.gz libreboot-5999dba5f71f1c05040a551d2420ab8c7f3a9da4.tar.bz2 | |
New board: ASUS KGPE-D16
coreboot build errors:
In file included from src/northbridge/amd/amdfam10/misc_control.c:35:0:
src/include/option.h:13:27: error: static declaration of 'get_option' follows non-static declaration
static inline enum cb_err get_option(void *dest, const char *name)
^
In file included from src/northbridge/amd/amdfam10/misc_control.c:34:0:
src/include/pc80/mc146818rtc.h:176:13: note: previous declaration of 'get_option' was here
enum cb_err get_option(void *dest, const char *name);
Ping tpearson about this.
Also ping him about the fact that there isn't actually an option to
enable or disable native graphics initialization, but that the option
MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG is in fact available and set to Y in the
Kconfig file. I think this is probably since there isn't even an option
ROM available for the machine, so it's pointless to offer the setting.
Diffstat (limited to 'resources/libreboot/patch/kgpe-d16/0114-southbridge-amd-sr5650-Hide-clock-configuration-devi.patch')
| -rw-r--r-- | resources/libreboot/patch/kgpe-d16/0114-southbridge-amd-sr5650-Hide-clock-configuration-devi.patch | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/resources/libreboot/patch/kgpe-d16/0114-southbridge-amd-sr5650-Hide-clock-configuration-devi.patch b/resources/libreboot/patch/kgpe-d16/0114-southbridge-amd-sr5650-Hide-clock-configuration-devi.patch new file mode 100644 index 0000000..ed6ae69 --- /dev/null +++ b/resources/libreboot/patch/kgpe-d16/0114-southbridge-amd-sr5650-Hide-clock-configuration-devi.patch @@ -0,0 +1,55 @@ +From f2495e7909302bd8cbc0633bde5a9ce60a6336c5 Mon Sep 17 00:00:00 2001 +From: Timothy Pearson <kb9vqf@pearsoncomputing.net> +Date: Thu, 13 Aug 2015 17:45:12 -0500 +Subject: [PATCH 114/146] southbridge/amd/sr5650: Hide clock configuration + device after setup is complete + +--- + src/southbridge/amd/sr5650/early_setup.c | 16 ++++++++-------- + src/southbridge/amd/sr5650/pcie.c | 3 +++ + 2 files changed, 11 insertions(+), 8 deletions(-) + +diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c +index e7cca06..cb666db 100644 +--- a/src/southbridge/amd/sr5650/early_setup.c ++++ b/src/southbridge/amd/sr5650/early_setup.c +@@ -414,14 +414,14 @@ static void sr5650_por_misc_index_init(device_t nb_dev) + set_nbmisc_enable_bits(nb_dev, 0x01, 0xFFFFFFFF, 0x00000310); + + /* NBCFG (NBMISCIND 0x0): NB_CNTL - +- * HIDE_NB_AGP_CAP ([0], default=1)HIDE +- * HIDE_P2P_AGP_CAP ([1], default=1)HIDE +- * HIDE_NB_GART_BAR ([2], default=1)HIDE +- * HIDE_MMCFG_BAR ([3], default=1)SHOW +- * AGPMODE30 ([4], default=0)DISABLE +- * AGP30ENCHANCED ([5], default=0)DISABLE +- * HIDE_AGP_CAP ([8], default=1)ENABLE */ +- set_nbmisc_enable_bits(nb_dev, 0x00, 0x0000FFFF, 0 << 0 | 1 << 1 | 1 << 2 | 0 << 3 | 0 << 6); ++ * HIDE_NB_AGP_CAP ([0], default=1)HIDE ++ * HIDE_P2P_AGP_CAP ([1], default=1)HIDE ++ * HIDE_NB_GART_BAR ([2], default=1)HIDE ++ * HIDE_MMCFG_BAR ([3], default=1)SHOW ++ * AGPMODE30 ([4], default=0)DISABLE ++ * AGP30ENCHANCED ([5], default=0)DISABLE ++ * HIDE_CLKCFG_HEADER ([8], default=0)SHOW */ ++ set_nbmisc_enable_bits(nb_dev, 0x00, 0x0000FFFF, 0 << 0 | 1 << 1 | 1 << 2 | 0 << 3 | 0 << 6 | 0 << 8); + + /* IOC_LAT_PERF_CNTR_CNTL */ + set_nbmisc_enable_bits(nb_dev, 0x30, 0xFF, 0x00); +diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c +index 09ce217..360e9cb 100644 +--- a/src/southbridge/amd/sr5650/pcie.c ++++ b/src/southbridge/amd/sr5650/pcie.c +@@ -854,6 +854,9 @@ void sr56x0_lock_hwinitreg(void) + + /* Lock HWInit Register NBMISCIND:0x0 NBCNTL[7] HWINIT_WR_LOCK */ + set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 7, 1 << 7); ++ ++ /* Hide clock configuration PCI device HIDE_CLKCFG_HEADER */ ++ set_nbmisc_enable_bits(nb_dev, 0x00, 0x00000100, 1 << 8); + } + + /***************************************** +-- +1.7.9.5 + |