Update coreboot to new version (use latest stable kgpe-d16 tree)

1 files changed, 0 insertions, 70 deletions

diff --git a/resources/libreboot/patch/kgpe-d16/0045-mainboard-asus-kgpe-d16-Enable-CC6.patch b/resources/libreboot/patch/kgpe-d16/0045-mainboard-asus-kgpe-d16-Enable-CC6.patch
deleted file mode 100644
index 26ddad6..0000000
--- a/resources/libreboot/patch/kgpe-d16/0045-mainboard-asus-kgpe-d16-Enable-CC6.patch
+++ /dev/null
@@ -1,70 +0,0 @@
-From 32b3afadc08bd155e25b12a0af8b11b629c064c3 Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <tpearson@raptorengineeringinc.com>
-Date: Fri, 5 Jun 2015 21:14:23 -0500
-Subject: [PATCH 045/139] mainboard/asus/kgpe-d16: Enable CC6
-
-Change-Id: Iae1cbe7d3a6471561abfdb8e182bc764c38bb222
-Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
----
- src/mainboard/asus/kgpe-d16/cmos.default      |  1 +
- src/mainboard/asus/kgpe-d16/cmos.layout       |  3 ++-
- src/northbridge/amd/amdmct/mct_ddr3/s3utils.c | 10 +++++++++-
- 3 files changed, 12 insertions(+), 2 deletions(-)
-
-diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default
-index 3e2ea3a..bfd2020 100644
---- a/src/mainboard/asus/kgpe-d16/cmos.default
-+++ b/src/mainboard/asus/kgpe-d16/cmos.default
-@@ -14,6 +14,7 @@ ecc_scrub_rate = 1.28us
- interleave_chip_selects = Enable
- interleave_nodes = Disable
- interleave_memory_channels = Enable
-+cpu_cc6_state = Enable
- ieee1394 = Enable
- power_on_after_fail = On
- boot_option = Fallback
-diff --git a/src/mainboard/asus/kgpe-d16/cmos.layout b/src/mainboard/asus/kgpe-d16/cmos.layout
-index 7944631..630219e 100644
---- a/src/mainboard/asus/kgpe-d16/cmos.layout
-+++ b/src/mainboard/asus/kgpe-d16/cmos.layout
-@@ -43,7 +43,8 @@ entries
- 458          4       e       11       hypertransport_speed_limit
- 462          2       e       12       minimum_memory_voltage
- 464          1       e       2        compute_unit_siblings
--465          1       r       0        allow_spd_nvram_cache_restore
-+465          1       e       1        cpu_cc6_state
-+466          1       r       0        allow_spd_nvram_cache_restore
- 477          1       e       1        ieee1394
- 728        256       h       0        user_data
- 984         16       h       0        check_sum
-diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
-index fa1873a..83c7b02 100644
---- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
-+++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
-@@ -625,7 +625,11 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste
- 			write_config32_dct(PCI_DEV(0, 0x18 + node, 1), node, channel, 0x124, data->f1x124);
- 			write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x10c, data->f2x10c);
- 			write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x114, data->f2x114);
--			write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x118, data->f2x118);
-+			if (is_fam15h())
-+				/* Do not set LockDramCfg or CC6SaveEn at this time */
-+				write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x118, data->f2x118 & ~(0x3 << 18));
-+			else
-+				write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x118, data->f2x118);
- 			write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x11c, data->f2x11c);
- 			write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x1b0, data->f2x1b0);
- 			write_config32_dct(PCI_DEV(0, 0x18 + node, 3), node, channel, 0x44, data->f3x44);
-@@ -1017,6 +1021,10 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste
- 
- 			/* ECC scrub rate control */
- 			pci_write_config32(PCI_DEV(0, 0x18 + node, 3), 0x58, data->f3x58);
-+
-+			if (is_fam15h())
-+				/* Set LockDramCfg and CC6SaveEn */
-+				write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x118, data->f2x118);
- 		}
- 	}
- }
--- 
-1.9.1
-