New board: ASUS KGPE-D16

coreboot build errors:

In file included from src/northbridge/amd/amdfam10/misc_control.c:35:0:
src/include/option.h:13:27: error: static declaration of 'get_option' follows non-static declaration
 static inline enum cb_err get_option(void *dest, const char *name)
                           ^
In file included from src/northbridge/amd/amdfam10/misc_control.c:34:0:
src/include/pc80/mc146818rtc.h:176:13: note: previous declaration of 'get_option' was here
 enum cb_err get_option(void *dest, const char *name);

Ping tpearson about this.

Also ping him about the fact that there isn't actually an option to
enable or disable native graphics initialization, but that the option
MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG is in fact available and set to Y in the
Kconfig file. I think this is probably since there isn't even an option
ROM available for the machine, so it's pointless to offer the setting.

1 files changed, 120 insertions, 0 deletions

diff --git a/resources/libreboot/patch/kgpe-d16/0013-northbridge-amd-amdfam10-Limit-maximum-RAM-clock-to-.patch b/resources/libreboot/patch/kgpe-d16/0013-northbridge-amd-amdfam10-Limit-maximum-RAM-clock-to-.patch
new file mode 100644
index 0000000..0d507c7
--- /dev/null
+++ b/resources/libreboot/patch/kgpe-d16/0013-northbridge-amd-amdfam10-Limit-maximum-RAM-clock-to-.patch
@@ -0,0 +1,120 @@
+From 818a658a290203625a65df4dde4901ea66fd72c8 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+Date: Sat, 5 Sep 2015 18:00:27 -0500
+Subject: [PATCH 013/146] northbridge/amd/amdfam10: Limit maximum RAM clock to
+ BKDG recommendations
+
+---
+ src/northbridge/amd/amdfam10/raminit_amdmct.c |   53 +++++++++++++++++++------
+ 1 file changed, 40 insertions(+), 13 deletions(-)
+
+diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c
+index a0d47f4..fa14e4f 100644
+--- a/src/northbridge/amd/amdfam10/raminit_amdmct.c
++++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c
+@@ -28,13 +28,6 @@ static  void print_tx(const char *strval, u32 val)
+ }
+ #endif
+ 
+-static  void print_t(const char *strval)
+-{
+-#if CONFIG_DEBUG_RAM_SETUP
+-	printk(BIOS_DEBUG, "%s", strval);
+-#endif
+-}
+-
+ static  void print_tf(const char *func, const char *strval)
+ {
+ #if CONFIG_DEBUG_RAM_SETUP
+@@ -42,30 +35,59 @@ static  void print_tf(const char *func, const char *strval)
+ #endif
+ }
+ 
+-static uint16_t mct_MaxLoadFreq(uint8_t count, uint16_t freq)
++static uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t registered, uint16_t freq)
+ {
+ 	/* Return limited maximum RAM frequency */
+ 	if (IS_ENABLED(CONFIG_DIMM_DDR2)) {
+-		if (IS_ENABLED(CONFIG_DIMM_REGISTERED)) {
++		if (IS_ENABLED(CONFIG_DIMM_REGISTERED) && registered) {
+ 			/* K10 BKDG Rev. 3.62 Table 53 */
+ 			if (count > 2) {
+ 				/* Limit to DDR2-533 */
+ 				if (freq > 266) {
+ 					freq = 266;
+-					print_tf(__func__, ": More than 2 DIMMs on channel; limiting to DDR2-533\n");
++					print_tf(__func__, ": More than 2 registered DIMMs on channel; limiting to DDR2-533\n");
+ 				}
+ 			}
+-		}
+-		else {
++		} else {
+ 			/* K10 BKDG Rev. 3.62 Table 52 */
+ 			if (count > 1) {
+ 				/* Limit to DDR2-800 */
+ 				if (freq > 400) {
+ 					freq = 400;
+-					print_tf(__func__, ": More than 1 DIMM on channel; limiting to DDR2-800\n");
++					print_tf(__func__, ": More than 1 unbuffered DIMM on channel; limiting to DDR2-800\n");
+ 				}
+ 			}
+ 		}
++	} else if (IS_ENABLED(CONFIG_DIMM_DDR3)) {
++		if (IS_ENABLED(CONFIG_DIMM_REGISTERED) && registered) {
++			/* K10 BKDG Rev. 3.62 Table 34 */
++			if (count > 2) {
++				/* Limit to DDR3-800 */
++				if (freq > 400) {
++					freq = 400;
++					print_tf(__func__, ": More than 2 registered DIMMs on channel; limiting to DDR3-800\n");
++				}
++			} else if (count == 2) {
++				/* Limit to DDR3-1066 */
++				if (freq > 533) {
++					freq = 533;
++					print_tf(__func__, ": 2 registered DIMMs on channel; limiting to DDR3-1066\n");
++				}
++			} else {
++				/* Limit to DDR3-1333 */
++				if (freq > 666) {
++					freq = 666;
++					print_tf(__func__, ": 1 registered DIMM on channel; limiting to DDR3-1333\n");
++				}
++			}
++		} else {
++			/* K10 BKDG Rev. 3.62 Table 33 */
++			/* Limit to DDR3-1333 */
++			if (freq > 666) {
++				freq = 666;
++				print_tf(__func__, ": unbuffered DIMMs on channel; limiting to DDR3-1333\n");
++			}
++		}
+ 	}
+ 
+ 	return freq;
+@@ -118,6 +140,9 @@ static uint16_t mct_MaxLoadFreq(uint8_t count, uint16_t freq)
+ //C32
+ #elif CONFIG_CPU_SOCKET_TYPE == 0x14
+ #include "../amdmct/mct_ddr3/mctardk5.c"
++//G34
++#elif CONFIG_CPU_SOCKET_TYPE == 0x15
++#include "../amdmct/mct_ddr3/mctardk5.c"
+ #endif
+ 
+ #else  /* DDR2 */
+@@ -205,6 +230,7 @@ static void raminit_amdmct(struct sys_info *sysinfo)
+ 	printk(BIOS_DEBUG, "raminit_amdmct end:\n");
+ }
+ 
++#if !IS_ENABLED(CONFIG_LATE_CBMEM_INIT)
+ static void amdmct_cbmem_store_info(struct sys_info *sysinfo)
+ {
+ 	if (!sysinfo)
+@@ -243,3 +269,4 @@ static void amdmct_cbmem_store_info(struct sys_info *sysinfo)
+ 	}
+ #endif
+ }
++#endif
+-- 
+1.7.9.5
+