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author | Francis Rowe <info@gluglug.org.uk> | 2016-03-08 01:00:09 (EST) |
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committer | Francis Rowe <info@gluglug.org.uk> | 2016-03-08 02:32:32 (EST) |
commit | dfa21bb8ee01eac21a2acee79011a634cb67e373 (patch) | |
tree | 21cd4f855aa03db13abba91400ad3be212b11602 /resources/libreboot/patch/coreboot/369b561315ca68d0cdedc38208105a513c7139b5/grub/kcma-d8/0015-nb-amd-mct_ddr3-Properly-set-MR0-WR-value.patch | |
parent | 2e5e505da125f9d90dd63c1cbcb08bf5316b21ae (diff) | |
download | libreboot-dfa21bb8ee01eac21a2acee79011a634cb67e373.zip libreboot-dfa21bb8ee01eac21a2acee79011a634cb67e373.tar.gz libreboot-dfa21bb8ee01eac21a2acee79011a634cb67e373.tar.bz2 |
Update coreboot (kgpe-d16,kcma-d8,kfsn4-dre,d510mo,ga-g41m-es2l)
Update to the latest coreboot and vboot versions at the time of writing:
coreboot 2a3434757ef425dbdfedf1fc69e1a033a6e7310d
vboot d187cd3fc792f8bcefbee4587c83eafbd08441fc
Diffstat (limited to 'resources/libreboot/patch/coreboot/369b561315ca68d0cdedc38208105a513c7139b5/grub/kcma-d8/0015-nb-amd-mct_ddr3-Properly-set-MR0-WR-value.patch')
-rw-r--r-- | resources/libreboot/patch/coreboot/369b561315ca68d0cdedc38208105a513c7139b5/grub/kcma-d8/0015-nb-amd-mct_ddr3-Properly-set-MR0-WR-value.patch | 30 |
1 files changed, 0 insertions, 30 deletions
diff --git a/resources/libreboot/patch/coreboot/369b561315ca68d0cdedc38208105a513c7139b5/grub/kcma-d8/0015-nb-amd-mct_ddr3-Properly-set-MR0-WR-value.patch b/resources/libreboot/patch/coreboot/369b561315ca68d0cdedc38208105a513c7139b5/grub/kcma-d8/0015-nb-amd-mct_ddr3-Properly-set-MR0-WR-value.patch deleted file mode 100644 index dd76550..0000000 --- a/resources/libreboot/patch/coreboot/369b561315ca68d0cdedc38208105a513c7139b5/grub/kcma-d8/0015-nb-amd-mct_ddr3-Properly-set-MR0-WR-value.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 5f5614ca862cecec27a3cf1fe843a4c30cbde69b Mon Sep 17 00:00:00 2001 -From: Timothy Pearson <tpearson@raptorengineeringinc.com> -Date: Tue, 24 Nov 2015 14:11:52 -0600 -Subject: [PATCH 15/45] nb/amd/mct_ddr3: Properly set MR0 WR value - -The existing code accidentally truncated the MSB from the MR0 -WR value. While this probably had a minimal effect in reality, -it should be configured correctly for maximal system stability. - -Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> ---- - src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c -index 822d813..bcf6031 100644 ---- a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c -+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c -@@ -967,7 +967,7 @@ static u32 mct_MR0(struct MCTStatStruc *pMCTstat, - - /* Load data into MRS word */ - ret |= (ppd & 0x1) << 12; -- ret |= (wr_ap & 0x3) << 9; -+ ret |= (wr_ap & 0x7) << 9; - ret |= (dll_reset & 0x1) << 8; - ret |= (test_mode & 0x1) << 7; - ret |= ((cas_latency & 0xe) >> 1) << 4; --- -2.1.4 - |