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author | Francis Rowe <info@gluglug.org.uk> | 2016-03-09 17:24:22 (EST) |
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committer | Francis Rowe <info@gluglug.org.uk> | 2016-03-09 17:24:22 (EST) |
commit | 735b6a3e7250a52c5fa04cdd400cb7f44f37b89e (patch) | |
tree | ed18f19984727efc2d4fdf321f50dce4ed36b2fd /resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/kfsn4-dre/0002-nb-amd-mct_ddr3-Train-correct-receiver-in-TrainDQSRd.patch | |
parent | 7b3449e35aa99310d4f247952a1e4fbd8f76ef2e (diff) | |
download | libreboot-735b6a3e7250a52c5fa04cdd400cb7f44f37b89e.zip libreboot-735b6a3e7250a52c5fa04cdd400cb7f44f37b89e.tar.gz libreboot-735b6a3e7250a52c5fa04cdd400cb7f44f37b89e.tar.bz2 |
kgpe-d6,kcma-d8,kfsn4-dre: use cb 67e11d1e4f5fa4ba7e864bb0487bf5a835fb2919
This revision is reported to work correctly.
Diffstat (limited to 'resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/kfsn4-dre/0002-nb-amd-mct_ddr3-Train-correct-receiver-in-TrainDQSRd.patch')
-rw-r--r-- | resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/kfsn4-dre/0002-nb-amd-mct_ddr3-Train-correct-receiver-in-TrainDQSRd.patch | 35 |
1 files changed, 0 insertions, 35 deletions
diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/kfsn4-dre/0002-nb-amd-mct_ddr3-Train-correct-receiver-in-TrainDQSRd.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/kfsn4-dre/0002-nb-amd-mct_ddr3-Train-correct-receiver-in-TrainDQSRd.patch deleted file mode 100644 index f866dda..0000000 --- a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/kfsn4-dre/0002-nb-amd-mct_ddr3-Train-correct-receiver-in-TrainDQSRd.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 3119f40c2e0abc36630a92fc5cee58b8d0f9087c Mon Sep 17 00:00:00 2001 -From: Timothy Pearson <tpearson@raptorengineeringinc.com> -Date: Mon, 7 Mar 2016 13:29:24 -0600 -Subject: [PATCH 2/2] nb/amd/mct_ddr3: Train correct receiver in - TrainDQSRdWrPos_D_Fam15 - -Change-Id: Ia26950a8297f0a7125c21e995c89a3fc68d9d8a9 -Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> ---- - src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 5 +---- - 1 file changed, 1 insertion(+), 4 deletions(-) - -diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c -index 1a3c7c1..ad81c3d 100644 ---- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c -+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c -@@ -1340,14 +1340,11 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, - - Errors = 0; - dual_rank = 0; -- Receiver = mct_InitReceiver_D(pDCTstat, dct); -- if (receiver_start > Receiver) -- Receiver = receiver_start; - - /* There are four receiver pairs, loosely associated with chipselects. - * This is essentially looping over each rank within each DIMM. - */ -- for (; Receiver < receiver_end; Receiver++) { -+ for (Receiver = receiver_start; Receiver < receiver_end; Receiver++) { - dimm = (Receiver >> 1); - if ((Receiver & 0x1) == 0) { - /* Even rank of DIMM */ --- -1.9.1 - |