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author | Francis Rowe <info@gluglug.org.uk> | 2016-03-09 18:04:24 (EST) |
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committer | Francis Rowe <info@gluglug.org.uk> | 2016-03-09 18:04:24 (EST) |
commit | c7d2a776aeb9b1b4210c187b705e8d8e79918419 (patch) | |
tree | 666d339be5c497991b73cf261323b9492dbc8caa /resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/kfsn4-dre/0002-nb-amd-mct_ddr3-Train-correct-receiver-in-TrainDQSRd.patch | |
parent | a37ceb2405d51098a5e70065af47ba2c5eec5a8c (diff) | |
download | libreboot-c7d2a776aeb9b1b4210c187b705e8d8e79918419.zip libreboot-c7d2a776aeb9b1b4210c187b705e8d8e79918419.tar.gz libreboot-c7d2a776aeb9b1b4210c187b705e8d8e79918419.tar.bz2 |
Revert "kgpe-d6,kcma-d8,kfsn4-dre: use cb 67e11d1e4f5fa4ba7e864bb0487bf5a835fb2919"
This reverts commit 735b6a3e7250a52c5fa04cdd400cb7f44f37b89e.
Diffstat (limited to 'resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/kfsn4-dre/0002-nb-amd-mct_ddr3-Train-correct-receiver-in-TrainDQSRd.patch')
-rw-r--r-- | resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/kfsn4-dre/0002-nb-amd-mct_ddr3-Train-correct-receiver-in-TrainDQSRd.patch | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/kfsn4-dre/0002-nb-amd-mct_ddr3-Train-correct-receiver-in-TrainDQSRd.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/kfsn4-dre/0002-nb-amd-mct_ddr3-Train-correct-receiver-in-TrainDQSRd.patch new file mode 100644 index 0000000..f866dda --- /dev/null +++ b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/kfsn4-dre/0002-nb-amd-mct_ddr3-Train-correct-receiver-in-TrainDQSRd.patch @@ -0,0 +1,35 @@ +From 3119f40c2e0abc36630a92fc5cee58b8d0f9087c Mon Sep 17 00:00:00 2001 +From: Timothy Pearson <tpearson@raptorengineeringinc.com> +Date: Mon, 7 Mar 2016 13:29:24 -0600 +Subject: [PATCH 2/2] nb/amd/mct_ddr3: Train correct receiver in + TrainDQSRdWrPos_D_Fam15 + +Change-Id: Ia26950a8297f0a7125c21e995c89a3fc68d9d8a9 +Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> +--- + src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 5 +---- + 1 file changed, 1 insertion(+), 4 deletions(-) + +diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +index 1a3c7c1..ad81c3d 100644 +--- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c ++++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +@@ -1340,14 +1340,11 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, + + Errors = 0; + dual_rank = 0; +- Receiver = mct_InitReceiver_D(pDCTstat, dct); +- if (receiver_start > Receiver) +- Receiver = receiver_start; + + /* There are four receiver pairs, loosely associated with chipselects. + * This is essentially looping over each rank within each DIMM. + */ +- for (; Receiver < receiver_end; Receiver++) { ++ for (Receiver = receiver_start; Receiver < receiver_end; Receiver++) { + dimm = (Receiver >> 1); + if ((Receiver & 0x1) == 0) { + /* Even rank of DIMM */ +-- +1.9.1 + |