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author | Paul Kocialkowski <contact@paulk.fr> | 2016-04-19 12:09:30 (EDT) |
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committer | Minifree Ltd <info@minifree.org> | 2016-04-19 18:50:21 (EDT) |
commit | 8e3b064430300bba4ef15e99ddcda3d861e8e264 (patch) | |
tree | ad02570aaf5d6da37a48726c0751e708ef8f50b2 /resources/libreboot/patch/coreboot/1bf5e6409678d04fd15f9625460078853118521c/depthcharge/veyron_speedy/0003-rockchip-rk3288-UART-uses-32bit-wide-registers.patch | |
parent | d0e903dac630b5d05e4b21dd90e410540ab55b6d (diff) | |
download | libreboot-8e3b064430300bba4ef15e99ddcda3d861e8e264.zip libreboot-8e3b064430300bba4ef15e99ddcda3d861e8e264.tar.gz libreboot-8e3b064430300bba4ef15e99ddcda3d861e8e264.tar.bz2 |
Coreboot, vboot and depthcharge updates to Coreboot 4.3 for CrOS devices
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Diffstat (limited to 'resources/libreboot/patch/coreboot/1bf5e6409678d04fd15f9625460078853118521c/depthcharge/veyron_speedy/0003-rockchip-rk3288-UART-uses-32bit-wide-registers.patch')
-rw-r--r-- | resources/libreboot/patch/coreboot/1bf5e6409678d04fd15f9625460078853118521c/depthcharge/veyron_speedy/0003-rockchip-rk3288-UART-uses-32bit-wide-registers.patch | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/resources/libreboot/patch/coreboot/1bf5e6409678d04fd15f9625460078853118521c/depthcharge/veyron_speedy/0003-rockchip-rk3288-UART-uses-32bit-wide-registers.patch b/resources/libreboot/patch/coreboot/1bf5e6409678d04fd15f9625460078853118521c/depthcharge/veyron_speedy/0003-rockchip-rk3288-UART-uses-32bit-wide-registers.patch new file mode 100644 index 0000000..8a2d253 --- /dev/null +++ b/resources/libreboot/patch/coreboot/1bf5e6409678d04fd15f9625460078853118521c/depthcharge/veyron_speedy/0003-rockchip-rk3288-UART-uses-32bit-wide-registers.patch @@ -0,0 +1,31 @@ +From 02bc24a863a9b580d5eb32b780296ff8a5c3d2c1 Mon Sep 17 00:00:00 2001 +From: Patrick Georgi <pgeorgi@chromium.org> +Date: Mon, 8 Feb 2016 20:28:32 +0100 +Subject: [PATCH 3/4] rockchip/rk3288: UART uses 32bit wide registers + +Change-Id: I084eb4694a2aa8f66afc1f3148480608ac3ff02b +Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> +Reviewed-on: https://review.coreboot.org/13635 +Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> +Tested-by: build bot (Jenkins) +Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> +--- + src/soc/rockchip/rk3288/uart.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/soc/rockchip/rk3288/uart.c b/src/soc/rockchip/rk3288/uart.c +index 9847734..8576dc1 100644 +--- a/src/soc/rockchip/rk3288/uart.c ++++ b/src/soc/rockchip/rk3288/uart.c +@@ -155,7 +155,7 @@ void uart_fill_lb(void *data) + serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial.baseaddr = CONFIG_CONSOLE_SERIAL_UART_ADDRESS; + serial.baud = default_baudrate(); +- serial.regwidth = 1; ++ serial.regwidth = 4; + lb_add_serial(&serial, data); + + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); +-- +2.8.0 + |